From 0ec51a460a308f10a21bbaa9d96cd6c3e8e6d834 Mon Sep 17 00:00:00 2001 From: Dmitry Borisenkov Date: Thu, 29 Dec 2022 18:04:55 -0500 Subject: [PATCH] DAG: Prevent store value forwarding to distinct addrspace load DAGCombiner replaces (load const_addr1) directly chained with (store (val, const_addr2)) with val if address space stripped const_addr1 == const_addr2. The patch fixes the issue by checking address spaces as well. However, it might makes sense to not to chain together side effects that belong to different address spaces in the first place and make SelectionDAG::root address space aware. --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +- llvm/test/CodeGen/NVPTX/chain-different-as.ll | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/NVPTX/chain-different-as.ll diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 48e4f24..e6f8b98 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -17113,7 +17113,7 @@ SDValue DAGCombiner::ForwardStoreValueToDirectLoad(LoadSDNode *LD) { SDValue Chain = LD->getOperand(0); StoreSDNode *ST = dyn_cast(Chain.getNode()); // TODO: Relax this restriction for unordered atomics (see D66309) - if (!ST || !ST->isSimple()) + if (!ST || !ST->isSimple() || ST->getAddressSpace() != LD->getAddressSpace()) return SDValue(); EVT LDType = LD->getValueType(0); diff --git a/llvm/test/CodeGen/NVPTX/chain-different-as.ll b/llvm/test/CodeGen/NVPTX/chain-different-as.ll new file mode 100644 index 0000000..18d0664 --- /dev/null +++ b/llvm/test/CodeGen/NVPTX/chain-different-as.ll @@ -0,0 +1,21 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=nvptx64 < %s | FileCheck %s + +define i64 @test() nounwind readnone { +; CHECK-LABEL: test( +; CHECK: { +; CHECK-NEXT: .reg .b64 %rd<4>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: mov.u64 %rd1, 1; +; CHECK-NEXT: mov.u64 %rd2, 42; +; CHECK-NEXT: st.u64 [%rd1], %rd2; +; CHECK-NEXT: ld.global.u64 %rd3, [%rd1]; +; CHECK-NEXT: st.param.b64 [func_retval0+0], %rd3; +; CHECK-NEXT: ret; + %addr0 = inttoptr i64 1 to ptr + %addr1 = inttoptr i64 1 to ptr addrspace(1) + store i64 42, ptr %addr0 + %res = load i64, ptr addrspace(1) %addr1 + ret i64 %res +} -- 2.7.4