From 0e7db6285cff60a07593c2ba3377ac4317c2c095 Mon Sep 17 00:00:00 2001 From: Shunzhou Jiang Date: Wed, 25 Jul 2018 16:42:42 +0800 Subject: [PATCH] clk: clock: Fix PCIE100M clock output some corner chip swing small issue PD#170610: clock: Fix PCIE100M clock output Change-Id: I8ada918f6910b537374115260ebaea7a4489e9d6 Signed-off-by: Shunzhou Jiang --- drivers/amlogic/clk/g12a/g12a_clk-pll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/amlogic/clk/g12a/g12a_clk-pll.c b/drivers/amlogic/clk/g12a/g12a_clk-pll.c index 660428b..90d3942 100644 --- a/drivers/amlogic/clk/g12a/g12a_clk-pll.c +++ b/drivers/amlogic/clk/g12a/g12a_clk-pll.c @@ -61,8 +61,8 @@ #define G12A_PCIE_PLL_CNTL3 0x10058e00 #define G12A_PCIE_PLL_CNTL4 0x000100c0 #define G12A_PCIE_PLL_CNTL4_ 0x008100c0 -#define G12A_PCIE_PLL_CNTL5 0x28000048 -#define G12A_PCIE_PLL_CNTL5_ 0x28000068 +#define G12A_PCIE_PLL_CNTL5 0x68000048 +#define G12A_PCIE_PLL_CNTL5_ 0x68000068 #define G12A_SYS_PLL_CNTL1 0x00000000 #define G12A_SYS_PLL_CNTL2 0x00000000 -- 2.7.4