From 0e6d6d54cee6708561b169b40f7fe51dfd3d8833 Mon Sep 17 00:00:00 2001
From: Elena Demikhovsky <elena.demikhovsky@intel.com>
Date: Tue, 21 Apr 2015 14:38:31 +0000
Subject: [PATCH] AVX-512: Added VPMOVx2M instructions for SKX, fixed encoding
 of VPMOVM2x.

llvm-svn: 235385
---
 llvm/lib/Target/X86/X86InstrAVX512.td        | 31 ++++++++++++++++++++++++++-
 llvm/test/MC/X86/avx512bw-encoding.s         | 17 +++++++++++++++
 llvm/test/MC/X86/avx512vl-encoding.s         | 32 ++++++++++++++++++++++++++++
 llvm/utils/TableGen/X86RecognizableInstr.cpp |  6 ++++++
 4 files changed, 85 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index c578f61..60b6310 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -5544,7 +5544,7 @@ def : Pat<(truncstorei1 GR8:$src, addr:$dst),
           (MOV8mr addr:$dst, GR8:$src)>;
 
 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
-def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
+def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
                   !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
                   [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
 }
@@ -5573,6 +5573,35 @@ multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
 
 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
 
+multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
+def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
+                  !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+                  [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
+}
+
+multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
+                        AVX512VLVectorVTInfo VTInfo, Predicate prd> {
+let Predicates = [prd] in
+  defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
+   EVEX_V512;
+
+  let Predicates = [prd, HasVLX] in {
+    defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
+     EVEX_V256;
+    defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
+     EVEX_V128;
+  }
+}
+
+defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
+                                              avx512vl_i8_info, HasBWI>;
+defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
+                                              avx512vl_i16_info, HasBWI>, VEX_W;
+defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
+                                              avx512vl_i32_info, HasDQI>;
+defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
+                                              avx512vl_i64_info, HasDQI>, VEX_W;
+
 //===----------------------------------------------------------------------===//
 // AVX-512 - COMPRESS and EXPAND
 //
diff --git a/llvm/test/MC/X86/avx512bw-encoding.s b/llvm/test/MC/X86/avx512bw-encoding.s
index b33847e..954e0bd 100644
--- a/llvm/test/MC/X86/avx512bw-encoding.s
+++ b/llvm/test/MC/X86/avx512bw-encoding.s
@@ -263,3 +263,20 @@
 // CHECK: vptestnmw -8256(%rdx), %zmm17, %k2
 // CHECK:  encoding: [0x62,0xf2,0xf6,0x40,0x26,0x92,0xc0,0xdf,0xff,0xff]
           vptestnmw -8256(%rdx), %zmm17, %k2
+
+// CHECK: vpmovb2m %zmm28, %k5
+// CHECK:  encoding: [0x62,0x92,0x7e,0x48,0x29,0xec]
+          vpmovb2m %zmm28, %k5
+
+// CHECK: vpmovw2m %zmm30, %k3
+// CHECK:  encoding: [0x62,0x92,0xfe,0x48,0x29,0xde]
+          vpmovw2m %zmm30, %k3
+
+// CHECK: vpmovm2b %k3, %zmm18
+// CHECK:  encoding: [0x62,0xe2,0x7e,0x48,0x28,0xd3]
+          vpmovm2b %k3, %zmm18
+
+// CHECK: vpmovm2w %k5, %zmm24
+// CHECK:  encoding: [0x62,0x62,0xfe,0x48,0x28,0xc5]
+          vpmovm2w %k5, %zmm24
+
diff --git a/llvm/test/MC/X86/avx512vl-encoding.s b/llvm/test/MC/X86/avx512vl-encoding.s
index 15d3a77..dd1ac24 100644
--- a/llvm/test/MC/X86/avx512vl-encoding.s
+++ b/llvm/test/MC/X86/avx512vl-encoding.s
@@ -859,3 +859,35 @@
 // CHECK: vptestnmq -1032(%rdx){1to4}, %ymm24, %k4
 // CHECK:  encoding: [0x62,0xf2,0xbe,0x30,0x27,0xa2,0xf8,0xfb,0xff,0xff]
           vptestnmq -1032(%rdx){1to4}, %ymm24, %k4
+
+// CHECK: vpmovd2m %xmm27, %k3
+// CHECK:  encoding: [0x62,0x92,0x7e,0x08,0x39,0xdb]
+          vpmovd2m %xmm27, %k3
+
+// CHECK: vpmovd2m %ymm28, %k4
+// CHECK:  encoding: [0x62,0x92,0x7e,0x28,0x39,0xe4]
+          vpmovd2m %ymm28, %k4
+
+// CHECK: vpmovq2m %xmm28, %k5
+// CHECK:  encoding: [0x62,0x92,0xfe,0x08,0x39,0xec]
+          vpmovq2m %xmm28, %k5
+
+// CHECK: vpmovq2m %ymm29, %k4
+// CHECK:  encoding: [0x62,0x92,0xfe,0x28,0x39,0xe5]
+          vpmovq2m %ymm29, %k4
+
+// CHECK: vpmovm2d %k2, %xmm29
+// CHECK:  encoding: [0x62,0x62,0x7e,0x08,0x38,0xea]
+          vpmovm2d %k2, %xmm29
+
+// CHECK: vpmovm2d %k5, %ymm20
+// CHECK:  encoding: [0x62,0xe2,0x7e,0x28,0x38,0xe5]
+          vpmovm2d %k5, %ymm20
+
+// CHECK: vpmovm2q %k5, %xmm17
+// CHECK:  encoding: [0x62,0xe2,0xfe,0x08,0x38,0xcd]
+          vpmovm2q %k5, %xmm17
+
+// CHECK: vpmovm2q %k2, %ymm30
+// CHECK:  encoding: [0x62,0x62,0xfe,0x28,0x38,0xf2]
+          vpmovm2q %k2, %ymm30
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index 5f12965..ae461bc 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -1096,6 +1096,8 @@ RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
   ENCODING("VR256X",          ENCODING_RM)
   ENCODING("VR512",           ENCODING_RM)
   ENCODING("VK1",             ENCODING_RM)
+  ENCODING("VK2",             ENCODING_RM)
+  ENCODING("VK4",             ENCODING_RM)
   ENCODING("VK8",             ENCODING_RM)
   ENCODING("VK16",            ENCODING_RM)
   ENCODING("VK32",            ENCODING_RM)
@@ -1133,8 +1135,12 @@ RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
   ENCODING("VK32",            ENCODING_REG)
   ENCODING("VK64",            ENCODING_REG)
   ENCODING("VK1WM",           ENCODING_REG)
+  ENCODING("VK2WM",           ENCODING_REG)
+  ENCODING("VK4WM",           ENCODING_REG)
   ENCODING("VK8WM",           ENCODING_REG)
   ENCODING("VK16WM",          ENCODING_REG)
+  ENCODING("VK32WM",          ENCODING_REG)
+  ENCODING("VK64WM",          ENCODING_REG)
   errs() << "Unhandled reg/opcode register encoding " << s << "\n";
   llvm_unreachable("Unhandled reg/opcode register encoding");
 }
-- 
2.7.4