From 0e66ca6fb96f3e0940a985c94ac65f7e5fedd072 Mon Sep 17 00:00:00 2001 From: SooChan Lim Date: Fri, 24 Mar 2017 21:28:02 +0900 Subject: [PATCH] use g_enable_cache_ctrl for cache control use it instead of ENABLE_CACHECTRL define Change-Id: I36b3a4320205fa5b41582583973f863f138e0523 --- src/tbm_bufmgr_exynos.c | 47 ++++++++++++++++++++++++++++++----------------- src/tbm_bufmgr_tgl.h | 5 ----- 2 files changed, 30 insertions(+), 22 deletions(-) diff --git a/src/tbm_bufmgr_exynos.c b/src/tbm_bufmgr_exynos.c index d7566ef..3e7c3e7 100644 --- a/src/tbm_bufmgr_exynos.c +++ b/src/tbm_bufmgr_exynos.c @@ -146,6 +146,9 @@ static unsigned int g_tbm_surface_alignment_pitch_rgb; } \ } +/* cache control at backend */ +static unsigned int g_enable_cache_ctrl = 0; + struct dma_buf_info { unsigned long size; unsigned int fence_supported; @@ -264,7 +267,6 @@ uint32_t tbm_exynos_color_format_list[TBM_COLOR_FORMAT_COUNT] = { TBM_FORMAT_YUV420 }; -#ifdef ENABLE_CACHECTRL #ifdef TGL_GET_VERSION static inline int _tgl_get_version(int fd) @@ -463,12 +465,14 @@ _exynos_cache_flush(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, in return 1; } -#endif static int _bo_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, int import) { -#ifdef ENABLE_CACHECTRL + /* check whether cache control do or not */ + if (!g_enable_cache_ctrl) + return 1; + EXYNOS_RETURN_VAL_IF_FAIL(bufmgr_exynos != NULL, 0); EXYNOS_RETURN_VAL_IF_FAIL(bo_exynos != NULL, 0); @@ -486,7 +490,6 @@ _bo_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, i _tgl_set_data(bufmgr_exynos->tgl_fd, bo_exynos->name, cache_state.val); } -#endif return 1; } @@ -494,7 +497,10 @@ _bo_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, i static int _bo_set_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, int device, int opt) { -#ifdef ENABLE_CACHECTRL + /* check whether cache control do or not */ + if (!g_enable_cache_ctrl) + return 1; + EXYNOS_RETURN_VAL_IF_FAIL(bufmgr_exynos != NULL, 0); EXYNOS_RETURN_VAL_IF_FAIL(bo_exynos != NULL, 0); @@ -553,7 +559,6 @@ _bo_set_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, in need_flush, cntFlush); } -#endif return 1; } @@ -561,7 +566,10 @@ _bo_set_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, in static int _bo_save_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos) { -#ifdef ENABLE_CACHECTRL + /* check whether cache control do or not */ + if (!g_enable_cache_ctrl) + return 1; + EXYNOS_RETURN_VAL_IF_FAIL(bufmgr_exynos != NULL, 0); EXYNOS_RETURN_VAL_IF_FAIL(bo_exynos != NULL, 0); @@ -577,7 +585,6 @@ _bo_save_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos) bo_exynos->cache_state.data.cntFlush = cntFlush; _tgl_set_data(bufmgr_exynos->tgl_fd, bo_exynos->name, bo_exynos->cache_state.val); -#endif return 1; } @@ -585,7 +592,10 @@ _bo_save_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos) static void _bo_destroy_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos) { -#ifdef ENABLE_CACHECTRL + /* check whether cache control do or not */ + if (!g_enable_cache_ctrl) + return; + EXYNOS_RETURN_IF_FAIL(bufmgr_exynos != NULL); EXYNOS_RETURN_IF_FAIL(bo_exynos != NULL); @@ -593,13 +603,15 @@ _bo_destroy_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos return ; _tgl_destroy(bufmgr_exynos->tgl_fd, bo_exynos->name); -#endif } static int _bufmgr_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos) { -#ifdef ENABLE_CACHECTRL + /* check whether cache control do or not */ + if (!g_enable_cache_ctrl) + return 1; + EXYNOS_RETURN_VAL_IF_FAIL(bufmgr_exynos != NULL, 0); if (bufmgr_exynos->use_dma_fence) @@ -630,7 +642,6 @@ _bufmgr_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos) close(bufmgr_exynos->tgl_fd); return 0; } -#endif return 1; } @@ -638,7 +649,10 @@ _bufmgr_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos) static void _bufmgr_deinit_cache_state(tbm_bufmgr_exynos bufmgr_exynos) { -#ifdef ENABLE_CACHECTRL + /* check whether cache control do or not */ + if (!g_enable_cache_ctrl) + return; + EXYNOS_RETURN_IF_FAIL(bufmgr_exynos != NULL); if (bufmgr_exynos->use_dma_fence) @@ -646,7 +660,6 @@ _bufmgr_deinit_cache_state(tbm_bufmgr_exynos bufmgr_exynos) if (bufmgr_exynos->tgl_fd >= 0) close(bufmgr_exynos->tgl_fd); -#endif } static int @@ -1494,10 +1507,9 @@ tbm_exynos_bo_unmap(tbm_bo bo) if (bo_exynos->map_cnt == 0) _bo_save_cache_state(bufmgr_exynos, bo_exynos); -#ifdef ENABLE_CACHECTRL - if (bo_exynos->last_map_device == TBM_DEVICE_CPU) + /* check whether cache control do or not */ + if (g_enable_cache_ctrl && bo_exynos->last_map_device == TBM_DEVICE_CPU) _exynos_cache_flush(bufmgr_exynos, bo_exynos, TBM_EXYNOS_CACHE_FLUSH_ALL); -#endif bo_exynos->last_map_device = -1; @@ -2240,6 +2252,7 @@ init_tbm_bufmgr_priv(tbm_bufmgr bufmgr, int fd) if (!strncmp(value, "TW1", 4)) { g_tbm_surface_alignment_plane = 8; g_tbm_surface_alignment_pitch_rgb = 8; + g_enable_cache_ctrl = 1; } else { g_tbm_surface_alignment_plane = 64; g_tbm_surface_alignment_pitch_rgb = 64; diff --git a/src/tbm_bufmgr_tgl.h b/src/tbm_bufmgr_tgl.h index 0ad453c..b442f73 100644 --- a/src/tbm_bufmgr_tgl.h +++ b/src/tbm_bufmgr_tgl.h @@ -34,10 +34,8 @@ #include -#ifdef ENABLE_CACHECTRL static char tgl_devfile[] = "/dev/slp_global_lock"; static char tgl_devfile1[] = "/dev/tgl"; -#endif #define TGL_IOCTL_BASE 0x32 #define TGL_IO(nr) _IO(TGL_IOCTL_BASE, nr) @@ -125,7 +123,6 @@ enum { /* get user data with key */ #define TGL_IOCTL_GET_DATA TGL_IOR(_TGL_GET_DATA, struct tgl_usr_data) -#ifdef ENABLE_CACHECTRL /* indicate cache units. */ enum e_drm_exynos_gem_cache_sel { EXYNOS_DRM_L1_CACHE = 1 << 0, @@ -175,6 +172,4 @@ struct drm_exynos_gem_cache_op { #define DRM_IOCTL_EXYNOS_GEM_CACHE_OP DRM_IOWR(DRM_COMMAND_BASE + \ DRM_EXYNOS_GEM_CACHE_OP, struct drm_exynos_gem_cache_op) -#endif - #endif /* __TBM_BUFMGR_TGL_H__ */ -- 2.7.4