From 0e54dbd4c7c26c4279f3e8b0af81f772ed076aab Mon Sep 17 00:00:00 2001 From: Ivan Safonov Date: Wed, 2 Mar 2016 15:07:46 +0700 Subject: [PATCH] staging: rtl8188eu: remove PWR_INTF_*_MSK macro definitions and interface_mask of wl_pwr_cfg structure This driver is intended only for usb devices. Signed-off-by: Ivan Safonov Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8188eu/hal/pwrseqcmd.c | 10 +- drivers/staging/rtl8188eu/hal/usb_halinit.c | 6 +- drivers/staging/rtl8188eu/include/pwrseq.h | 139 +++++++++----------------- drivers/staging/rtl8188eu/include/pwrseqcmd.h | 10 +- 4 files changed, 57 insertions(+), 108 deletions(-) diff --git a/drivers/staging/rtl8188eu/hal/pwrseqcmd.c b/drivers/staging/rtl8188eu/hal/pwrseqcmd.c index 7eb1fdb..99d89f9 100644 --- a/drivers/staging/rtl8188eu/hal/pwrseqcmd.c +++ b/drivers/staging/rtl8188eu/hal/pwrseqcmd.c @@ -24,7 +24,7 @@ * for RTL8723/RTL8188E Series IC. */ u8 rtl88eu_pwrseqcmdparsing(struct adapter *padapter, u8 cut_vers, - u8 ifacetype, struct wl_pwr_cfg pwrseqcmd[]) + struct wl_pwr_cfg pwrseqcmd[]) { struct wl_pwr_cfg pwrcfgcmd = {0}; u8 poll_bit = false; @@ -39,19 +39,17 @@ u8 rtl88eu_pwrseqcmdparsing(struct adapter *padapter, u8 cut_vers, RT_TRACE(_module_hal_init_c_, _drv_info_, ("rtl88eu_pwrseqcmdparsing: offset(%#x) cut_msk(%#x)" - "interface_msk(%#x) base(%#x) cmd(%#x)" + " base(%#x) cmd(%#x)" "msk(%#x) value(%#x)\n", GET_PWR_CFG_OFFSET(pwrcfgcmd), GET_PWR_CFG_CUT_MASK(pwrcfgcmd), - GET_PWR_CFG_INTF_MASK(pwrcfgcmd), GET_PWR_CFG_BASE(pwrcfgcmd), GET_PWR_CFG_CMD(pwrcfgcmd), GET_PWR_CFG_MASK(pwrcfgcmd), GET_PWR_CFG_VALUE(pwrcfgcmd))); - /* Only Handle the command whose CUT and Interface are matched */ - if ((GET_PWR_CFG_CUT_MASK(pwrcfgcmd) & cut_vers) && - (GET_PWR_CFG_INTF_MASK(pwrcfgcmd) & ifacetype)) { + /* Only Handle the command whose CUT is matched */ + if (GET_PWR_CFG_CUT_MASK(pwrcfgcmd) & cut_vers) { switch (GET_PWR_CFG_CMD(pwrcfgcmd)) { case PWR_CMD_READ: RT_TRACE(_module_hal_init_c_, _drv_info_, diff --git a/drivers/staging/rtl8188eu/hal/usb_halinit.c b/drivers/staging/rtl8188eu/hal/usb_halinit.c index 0868635..07a61b8 100644 --- a/drivers/staging/rtl8188eu/hal/usb_halinit.c +++ b/drivers/staging/rtl8188eu/hal/usb_halinit.c @@ -107,7 +107,7 @@ static u32 rtl8188eu_InitPowerOn(struct adapter *adapt) if (haldata->bMacPwrCtrlOn) return _SUCCESS; - if (!rtl88eu_pwrseqcmdparsing(adapt, PWR_CUT_ALL_MSK, PWR_INTF_USB_MSK, + if (!rtl88eu_pwrseqcmdparsing(adapt, PWR_CUT_ALL_MSK, Rtl8188E_NIC_PWR_ON_FLOW)) { DBG_88E(KERN_ERR "%s: run power on flow fail\n", __func__); return _FAIL; @@ -924,7 +924,7 @@ static void CardDisableRTL8188EU(struct adapter *Adapter) usb_write8(Adapter, REG_CR, 0x0); /* Run LPS WL RFOFF flow */ - rtl88eu_pwrseqcmdparsing(Adapter, PWR_CUT_ALL_MSK, PWR_INTF_USB_MSK, + rtl88eu_pwrseqcmdparsing(Adapter, PWR_CUT_ALL_MSK, Rtl8188E_NIC_LPS_ENTER_FLOW); /* 2. 0x1F[7:0] = 0 turn off RF */ @@ -946,7 +946,7 @@ static void CardDisableRTL8188EU(struct adapter *Adapter) usb_write8(Adapter, REG_32K_CTRL, val8&(~BIT(0))); /* Card disable power action flow */ - rtl88eu_pwrseqcmdparsing(Adapter, PWR_CUT_ALL_MSK, PWR_INTF_USB_MSK, + rtl88eu_pwrseqcmdparsing(Adapter, PWR_CUT_ALL_MSK, Rtl8188E_NIC_DISABLE_FLOW); /* Reset MCU IO Wrapper */ diff --git a/drivers/staging/rtl8188eu/include/pwrseq.h b/drivers/staging/rtl8188eu/include/pwrseq.h index bf89d7c..889565e 100644 --- a/drivers/staging/rtl8188eu/include/pwrseq.h +++ b/drivers/staging/rtl8188eu/include/pwrseq.h @@ -64,33 +64,30 @@ * }, * comment here */ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0006, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ /* wait till 0x04[17] = 1 power ready*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0002, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) | BIT(1), 0}, \ /* 0x02[1:0] = 0 reset BB*/ \ - {0x0026, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0026, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \ /*0x24[23] = 2b'01 schmit trigger */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0005, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \ /* 0x04[15] = 0 disable HWPDN (control by DRV)*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0005, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, \ /*0x04[12:11] = 2b'00 disable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0005, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ /*0x04[8] = 1 polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0005, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \ /*wait till 0x04[8] = 0*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0023, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ - /*LDO normal mode*/ \ - {0x0074, PWR_CUT_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ - /*SDIO Driving*/ + /*LDO normal mode*/ #define RTL8188E_TRANS_ACT_TO_CARDEMU \ /* format @@ -98,16 +95,16 @@ * }, * comments here */ \ - {0x001F, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x001F, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \ /*0x1F[7:0] = 0 turn off RF*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0023, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ /*LDO Sleep mode*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0005, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0005, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \ /*wait till 0x04[9] = 0 polling until return 0 to disable*/ @@ -117,31 +114,18 @@ * value }, * comments here */ \ - {0x0005, PWR_CUT_ALL_MSK, \ - PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ + {0x0005, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC, \ PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \ /* 0x04[12:11] = 2b'01enable WL suspend */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_INTF_PCI_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)}, \ - /* 0x04[12:11] = 2b'11enable WL suspend for PCIe */ \ - {0x0007, PWR_CUT_ALL_MSK, \ - PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ + {0x0007, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC, \ PWR_CMD_WRITE, 0xFF, BIT(7)}, \ /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\ - {0x0041, PWR_CUT_ALL_MSK, \ - PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ + {0x0041, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC, \ PWR_CMD_WRITE, BIT(4), 0}, \ /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ - {0xfe10, PWR_CUT_ALL_MSK, \ - PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ + {0xfe10, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC, \ PWR_CMD_WRITE, BIT(4), BIT(4)}, \ - /*Set USB suspend enable local register 0xfe10[4]=1 */ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ - /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, \ - /*wait power state to suspend*/ + /*Set USB suspend enable local register 0xfe10[4]=1 */ #define RTL8188E_TRANS_SUS_TO_CARDEMU \ /* format @@ -149,13 +133,7 @@ * value }, * comments here */ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \ - /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ - /*wait power state to suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0005, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \ /*0x04[12:11] = 2b'01enable WL suspend*/ @@ -165,30 +143,21 @@ * value }, * comments here */ \ - {0x0026, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0026, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \ /*0x24[23] = 2b'01 schmit trigger */ \ - {0x0005, PWR_CUT_ALL_MSK, \ - PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ + {0x0005, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC, \ PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \ /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0007, PWR_CUT_ALL_MSK, \ - PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ + {0x0007, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC, \ PWR_CMD_WRITE, 0xFF, 0}, \ /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\ - {0x0041, PWR_CUT_ALL_MSK, \ - PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ + {0x0041, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC, \ PWR_CMD_WRITE, BIT(4), 0}, \ /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ - {0xfe10, PWR_CUT_ALL_MSK, PWR_INTF_USB_MSK, \ + {0xfe10, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ - /*Set USB suspend enable local register 0xfe10[4]=1 */ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ - /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, \ - /*wait power state to suspend*/ + /*Set USB suspend enable local register 0xfe10[4]=1 */ #define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \ /* format @@ -196,13 +165,7 @@ * value }, * comments here */ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \ - /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ - /*wait power state to suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0005, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \ /*0x04[12:11] = 2b'01enable WL suspend*/ @@ -212,10 +175,10 @@ * value }, * comments here */ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0006, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ /* 0x04[16] = 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0005, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \ /* 0x04[15] = 1*/ @@ -225,7 +188,7 @@ * value }, * comments here */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0005, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \ /* 0x04[15] = 0*/ @@ -236,31 +199,31 @@ * value }, * comments here */ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0522, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x05F8, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ /*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x05F9, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ /*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x05FA, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ /*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x05FB, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ /*Should be zero if no packet is transmitting*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0002, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ /*CCK and OFDM are disabled,and clock are gated*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0002, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, \ PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0100, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0101, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/\ - {0x0553, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0553, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)}, \ /*Respond TxOK to scheduler*/ @@ -271,33 +234,29 @@ * value }, * comments here */ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_INTF_SDIO_MSK, \ - PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \ - {0xFE58, PWR_CUT_ALL_MSK, PWR_INTF_USB_MSK, \ + {0xFE58, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \ - {0x0361, PWR_CUT_ALL_MSK, PWR_INTF_PCI_MSK, \ - PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0002, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0008, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ /* 0x08[4] = 0 switch TSF to 40M */ \ - {0x0109, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0109, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \ /* Polling 0x109[7]=0 TSF in 40M */ \ - {0x0029, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0029, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, \ /* 0x29[7:6] = 2b'00 enable BB clock */ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0101, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ /* 0x101[1] = 1 */ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0100, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \ /* 0x100[7:0] = 0xFF enable WMAC TRX */ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0002, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \ /* 0x02[1:0] = 2b'11 enable BB macro */ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, \ + {0x0522, PWR_CUT_ALL_MSK, \ PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ #define RTL8188E_TRANS_END \ @@ -306,7 +265,7 @@ * value }, * comments here */ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_INTF_ALL_MSK, 0, \ + {0xFFFF, PWR_CUT_ALL_MSK, 0, \ PWR_CMD_END, 0, 0}, diff --git a/drivers/staging/rtl8188eu/include/pwrseqcmd.h b/drivers/staging/rtl8188eu/include/pwrseqcmd.h index ccc066a..9dd5ce5 100644 --- a/drivers/staging/rtl8188eu/include/pwrseqcmd.h +++ b/drivers/staging/rtl8188eu/include/pwrseqcmd.h @@ -36,12 +36,6 @@ #define PWR_BASEADDR_PCIE 0x02 #define PWR_BASEADDR_SDIO 0x03 -/* The value of interface_msk: 4 bits */ -#define PWR_INTF_SDIO_MSK BIT(0) -#define PWR_INTF_USB_MSK BIT(1) -#define PWR_INTF_PCI_MSK BIT(2) -#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) - /* The value of cut_msk: 8 bits */ #define PWR_CUT_TESTCHIP_MSK BIT(0) #define PWR_CUT_A_MSK BIT(1) @@ -62,7 +56,6 @@ enum pwrseq_cmd_delat_unit { struct wl_pwr_cfg { u16 offset; u8 cut_msk; - u8 interface_msk:4; u8 base:4; u8 cmd:4; u8 msk; @@ -71,13 +64,12 @@ struct wl_pwr_cfg { #define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset #define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk -#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk #define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base #define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd #define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk #define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value u8 rtl88eu_pwrseqcmdparsing(struct adapter *padapter, u8 cut_vers, - u8 ifacetype, struct wl_pwr_cfg pwrcfgCmd[]); + struct wl_pwr_cfg pwrcfgCmd[]); #endif -- 2.7.4