From 0e520300580a77f1d7c01ada9a047a7fadb5eb1f Mon Sep 17 00:00:00 2001 From: Dinar Temirbulatov Date: Thu, 10 Nov 2022 00:38:28 +0000 Subject: [PATCH] [AArch64][SVE] Migrate tests to use opaque pointers (NFC) Test updates were performed using: https://gist.github.com/nikic/98357b71fd67756b0f064c9517b62a34 --- llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll | 7 +- .../AArch64/sve-fixed-length-bit-counting.ll | 288 ++++----- .../CodeGen/AArch64/sve-fixed-length-bitcast.ll | 108 ++-- .../CodeGen/AArch64/sve-fixed-length-bitselect.ll | 8 +- .../CodeGen/AArch64/sve-fixed-length-concat.ll | 272 ++++---- .../CodeGen/AArch64/sve-fixed-length-ext-loads.ll | 68 +- .../AArch64/sve-fixed-length-extract-subvector.ll | 168 ++--- .../AArch64/sve-fixed-length-extract-vector-elt.ll | 48 +- .../CodeGen/AArch64/sve-fixed-length-fp-arith.ll | 720 ++++++++++----------- .../AArch64/sve-fixed-length-fp-compares.ll | 248 +++---- .../CodeGen/AArch64/sve-fixed-length-fp-convert.ll | 6 +- .../AArch64/sve-fixed-length-fp-extend-trunc.ll | 212 +++--- .../CodeGen/AArch64/sve-fixed-length-fp-fma.ll | 120 ++-- .../CodeGen/AArch64/sve-fixed-length-fp-minmax.ll | 384 +++++------ .../CodeGen/AArch64/sve-fixed-length-fp-reduce.ll | 192 +++--- .../AArch64/sve-fixed-length-fp-rounding.ll | 504 +++++++-------- .../CodeGen/AArch64/sve-fixed-length-fp-select.ll | 96 +-- .../CodeGen/AArch64/sve-fixed-length-fp-to-int.ll | 428 ++++++------ .../CodeGen/AArch64/sve-fixed-length-fp-vselect.ll | 96 +-- .../sve-fixed-length-frame-offests-crash.ll | 36 +- .../AArch64/sve-fixed-length-frame-offests.ll | 8 +- .../AArch64/sve-fixed-length-insert-vector-elt.ll | 48 +- .../CodeGen/AArch64/sve-fixed-length-int-arith.ll | 480 +++++++------- .../AArch64/sve-fixed-length-int-compares.ll | 200 +++--- .../CodeGen/AArch64/sve-fixed-length-int-div.ll | 262 ++++---- .../AArch64/sve-fixed-length-int-extends.ll | 256 ++++---- .../AArch64/sve-fixed-length-int-immediates.ll | 336 +++++----- .../CodeGen/AArch64/sve-fixed-length-int-log.ll | 384 +++++------ .../CodeGen/AArch64/sve-fixed-length-int-minmax.ll | 512 +++++++-------- .../CodeGen/AArch64/sve-fixed-length-int-mulh.ll | 256 ++++---- .../CodeGen/AArch64/sve-fixed-length-int-reduce.ll | 320 ++++----- .../CodeGen/AArch64/sve-fixed-length-int-rem.ll | 256 ++++---- .../CodeGen/AArch64/sve-fixed-length-int-select.ll | 128 ++-- .../CodeGen/AArch64/sve-fixed-length-int-shifts.ll | 384 +++++------ .../CodeGen/AArch64/sve-fixed-length-int-to-fp.ll | 428 ++++++------ .../AArch64/sve-fixed-length-int-vselect.ll | 128 ++-- .../AArch64/sve-fixed-length-limit-duplane.ll | 16 +- .../test/CodeGen/AArch64/sve-fixed-length-loads.ll | 24 +- .../CodeGen/AArch64/sve-fixed-length-log-reduce.ll | 192 +++--- .../CodeGen/AArch64/sve-fixed-length-mask-opt.ll | 200 +++--- .../AArch64/sve-fixed-length-masked-gather.ll | 608 ++++++++--------- .../AArch64/sve-fixed-length-masked-loads.ll | 374 +++++------ .../AArch64/sve-fixed-length-masked-scatter.ll | 500 +++++++------- .../AArch64/sve-fixed-length-masked-stores.ll | 130 ++-- .../AArch64/sve-fixed-length-optimize-ptrue.ll | 52 +- .../AArch64/sve-fixed-length-permute-rev.ll | 124 ++-- .../sve-fixed-length-permute-zip-uzp-trn.ll | 200 +++--- .../test/CodeGen/AArch64/sve-fixed-length-ptest.ll | 39 +- llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll | 168 ++--- .../CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll | 96 +-- .../CodeGen/AArch64/sve-fixed-length-shuffles.ll | 10 +- .../AArch64/sve-fixed-length-splat-vector.ll | 140 ++-- .../CodeGen/AArch64/sve-fixed-length-stores.ll | 24 +- .../CodeGen/AArch64/sve-fixed-length-subvector.ll | 144 ++--- .../AArch64/sve-fixed-length-trunc-stores.ll | 60 +- .../test/CodeGen/AArch64/sve-fixed-length-trunc.ll | 124 ++-- .../AArch64/sve-fixed-length-vector-shuffle.ll | 240 +++---- 57 files changed, 5925 insertions(+), 5935 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll b/llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll index f59891c3..0ec5c60 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll @@ -3,7 +3,7 @@ target triple = "aarch64-unknown-linux-gnu" -define void @st1d_fixed(<8 x double>* %ptr) #0 { +define void @st1d_fixed(ptr %ptr) #0 { ; CHECK-LABEL: st1d_fixed: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #16 @@ -17,10 +17,9 @@ define void @st1d_fixed(<8 x double>* %ptr) #0 { ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret %alloc = alloca [16 x double], i32 0 - %bc = bitcast [16 x double]* %alloc to <8 x double>* - %load = load <8 x double>, <8 x double>* %bc + %load = load <8 x double>, ptr %alloc %strided.vec = shufflevector <8 x double> %load, <8 x double> poison, <4 x i32> - store <8 x double> zeroinitializer, <8 x double>* %ptr + store <8 x double> zeroinitializer, ptr %ptr ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll index f2dc770..6174ae3 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll @@ -29,7 +29,7 @@ define <16 x i8> @ctlz_v16i8(<16 x i8> %op) vscale_range(2,0) #0 { ret <16 x i8> %res } -define void @ctlz_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { +define void @ctlz_v32i8(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: ctlz_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -37,13 +37,13 @@ define void @ctlz_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: clz z0.b, p0/m, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x i8>, <32 x i8>* %a + %op = load <32 x i8>, ptr %a %res = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> %op) - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @ctlz_v64i8(<64 x i8>* %a) #0 { +define void @ctlz_v64i8(ptr %a) #0 { ; VBITS_GE_256-LABEL: ctlz_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -63,13 +63,13 @@ define void @ctlz_v64i8(<64 x i8>* %a) #0 { ; VBITS_GE_512-NEXT: clz z0.b, p0/m, z0.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <64 x i8>, <64 x i8>* %a + %op = load <64 x i8>, ptr %a %res = call <64 x i8> @llvm.ctlz.v64i8(<64 x i8> %op) - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @ctlz_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { +define void @ctlz_v128i8(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: ctlz_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -77,13 +77,13 @@ define void @ctlz_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: clz z0.b, p0/m, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x i8>, <128 x i8>* %a + %op = load <128 x i8>, ptr %a %res = call <128 x i8> @llvm.ctlz.v128i8(<128 x i8> %op) - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @ctlz_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { +define void @ctlz_v256i8(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: ctlz_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -91,9 +91,9 @@ define void @ctlz_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: clz z0.b, p0/m, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op = load <256 x i8>, <256 x i8>* %a + %op = load <256 x i8>, ptr %a %res = call <256 x i8> @llvm.ctlz.v256i8(<256 x i8> %op) - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -117,7 +117,7 @@ define <8 x i16> @ctlz_v8i16(<8 x i16> %op) vscale_range(2,0) #0 { ret <8 x i16> %res } -define void @ctlz_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { +define void @ctlz_v16i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: ctlz_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -125,13 +125,13 @@ define void @ctlz_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: clz z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x i16>, <16 x i16>* %a + %op = load <16 x i16>, ptr %a %res = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> %op) - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @ctlz_v32i16(<32 x i16>* %a) #0 { +define void @ctlz_v32i16(ptr %a) #0 { ; VBITS_GE_256-LABEL: ctlz_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -151,13 +151,13 @@ define void @ctlz_v32i16(<32 x i16>* %a) #0 { ; VBITS_GE_512-NEXT: clz z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <32 x i16>, <32 x i16>* %a + %op = load <32 x i16>, ptr %a %res = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %op) - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @ctlz_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { +define void @ctlz_v64i16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: ctlz_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -165,13 +165,13 @@ define void @ctlz_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: clz z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x i16>, <64 x i16>* %a + %op = load <64 x i16>, ptr %a %res = call <64 x i16> @llvm.ctlz.v64i16(<64 x i16> %op) - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @ctlz_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { +define void @ctlz_v128i16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: ctlz_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -179,9 +179,9 @@ define void @ctlz_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: clz z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x i16>, <128 x i16>* %a + %op = load <128 x i16>, ptr %a %res = call <128 x i16> @llvm.ctlz.v128i16(<128 x i16> %op) - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -205,7 +205,7 @@ define <4 x i32> @ctlz_v4i32(<4 x i32> %op) vscale_range(2,0) #0 { ret <4 x i32> %res } -define void @ctlz_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { +define void @ctlz_v8i32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: ctlz_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -213,13 +213,13 @@ define void @ctlz_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: clz z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <8 x i32>, <8 x i32>* %a + %op = load <8 x i32>, ptr %a %res = call <8 x i32> @llvm.ctlz.v8i32(<8 x i32> %op) - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @ctlz_v16i32(<16 x i32>* %a) #0 { +define void @ctlz_v16i32(ptr %a) #0 { ; VBITS_GE_256-LABEL: ctlz_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -239,13 +239,13 @@ define void @ctlz_v16i32(<16 x i32>* %a) #0 { ; VBITS_GE_512-NEXT: clz z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <16 x i32>, <16 x i32>* %a + %op = load <16 x i32>, ptr %a %res = call <16 x i32> @llvm.ctlz.v16i32(<16 x i32> %op) - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @ctlz_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { +define void @ctlz_v32i32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: ctlz_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -253,13 +253,13 @@ define void @ctlz_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: clz z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x i32>, <32 x i32>* %a + %op = load <32 x i32>, ptr %a %res = call <32 x i32> @llvm.ctlz.v32i32(<32 x i32> %op) - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @ctlz_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { +define void @ctlz_v64i32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: ctlz_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -267,9 +267,9 @@ define void @ctlz_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: clz z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x i32>, <64 x i32>* %a + %op = load <64 x i32>, ptr %a %res = call <64 x i32> @llvm.ctlz.v64i32(<64 x i32> %op) - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -297,7 +297,7 @@ define <2 x i64> @ctlz_v2i64(<2 x i64> %op) vscale_range(2,0) #0 { ret <2 x i64> %res } -define void @ctlz_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { +define void @ctlz_v4i64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: ctlz_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -305,13 +305,13 @@ define void @ctlz_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: clz z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <4 x i64>, <4 x i64>* %a + %op = load <4 x i64>, ptr %a %res = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> %op) - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @ctlz_v8i64(<8 x i64>* %a) #0 { +define void @ctlz_v8i64(ptr %a) #0 { ; VBITS_GE_256-LABEL: ctlz_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -331,13 +331,13 @@ define void @ctlz_v8i64(<8 x i64>* %a) #0 { ; VBITS_GE_512-NEXT: clz z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <8 x i64>, <8 x i64>* %a + %op = load <8 x i64>, ptr %a %res = call <8 x i64> @llvm.ctlz.v8i64(<8 x i64> %op) - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @ctlz_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { +define void @ctlz_v16i64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: ctlz_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -345,13 +345,13 @@ define void @ctlz_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: clz z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x i64>, <16 x i64>* %a + %op = load <16 x i64>, ptr %a %res = call <16 x i64> @llvm.ctlz.v16i64(<16 x i64> %op) - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @ctlz_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { +define void @ctlz_v32i64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: ctlz_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -359,9 +359,9 @@ define void @ctlz_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: clz z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x i64>, <32 x i64>* %a + %op = load <32 x i64>, ptr %a %res = call <32 x i64> @llvm.ctlz.v32i64(<32 x i64> %op) - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } @@ -389,7 +389,7 @@ define <16 x i8> @ctpop_v16i8(<16 x i8> %op) vscale_range(2,0) #0 { ret <16 x i8> %res } -define void @ctpop_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { +define void @ctpop_v32i8(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: ctpop_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -397,13 +397,13 @@ define void @ctpop_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: cnt z0.b, p0/m, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x i8>, <32 x i8>* %a + %op = load <32 x i8>, ptr %a %res = call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %op) - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @ctpop_v64i8(<64 x i8>* %a) #0 { +define void @ctpop_v64i8(ptr %a) #0 { ; VBITS_GE_256-LABEL: ctpop_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -423,13 +423,13 @@ define void @ctpop_v64i8(<64 x i8>* %a) #0 { ; VBITS_GE_512-NEXT: cnt z0.b, p0/m, z0.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <64 x i8>, <64 x i8>* %a + %op = load <64 x i8>, ptr %a %res = call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %op) - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @ctpop_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { +define void @ctpop_v128i8(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: ctpop_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -437,13 +437,13 @@ define void @ctpop_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: cnt z0.b, p0/m, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x i8>, <128 x i8>* %a + %op = load <128 x i8>, ptr %a %res = call <128 x i8> @llvm.ctpop.v128i8(<128 x i8> %op) - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @ctpop_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { +define void @ctpop_v256i8(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: ctpop_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -451,9 +451,9 @@ define void @ctpop_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: cnt z0.b, p0/m, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op = load <256 x i8>, <256 x i8>* %a + %op = load <256 x i8>, ptr %a %res = call <256 x i8> @llvm.ctpop.v256i8(<256 x i8> %op) - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -479,7 +479,7 @@ define <8 x i16> @ctpop_v8i16(<8 x i16> %op) vscale_range(2,0) #0 { ret <8 x i16> %res } -define void @ctpop_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { +define void @ctpop_v16i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: ctpop_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -487,13 +487,13 @@ define void @ctpop_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: cnt z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x i16>, <16 x i16>* %a + %op = load <16 x i16>, ptr %a %res = call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %op) - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @ctpop_v32i16(<32 x i16>* %a) #0 { +define void @ctpop_v32i16(ptr %a) #0 { ; VBITS_GE_256-LABEL: ctpop_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -513,13 +513,13 @@ define void @ctpop_v32i16(<32 x i16>* %a) #0 { ; VBITS_GE_512-NEXT: cnt z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <32 x i16>, <32 x i16>* %a + %op = load <32 x i16>, ptr %a %res = call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %op) - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @ctpop_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { +define void @ctpop_v64i16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: ctpop_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -527,13 +527,13 @@ define void @ctpop_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: cnt z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x i16>, <64 x i16>* %a + %op = load <64 x i16>, ptr %a %res = call <64 x i16> @llvm.ctpop.v64i16(<64 x i16> %op) - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @ctpop_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { +define void @ctpop_v128i16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: ctpop_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -541,9 +541,9 @@ define void @ctpop_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: cnt z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x i16>, <128 x i16>* %a + %op = load <128 x i16>, ptr %a %res = call <128 x i16> @llvm.ctpop.v128i16(<128 x i16> %op) - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -571,7 +571,7 @@ define <4 x i32> @ctpop_v4i32(<4 x i32> %op) vscale_range(2,0) #0 { ret <4 x i32> %res } -define void @ctpop_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { +define void @ctpop_v8i32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: ctpop_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -579,13 +579,13 @@ define void @ctpop_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: cnt z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <8 x i32>, <8 x i32>* %a + %op = load <8 x i32>, ptr %a %res = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %op) - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @ctpop_v16i32(<16 x i32>* %a) #0 { +define void @ctpop_v16i32(ptr %a) #0 { ; VBITS_GE_256-LABEL: ctpop_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -605,13 +605,13 @@ define void @ctpop_v16i32(<16 x i32>* %a) #0 { ; VBITS_GE_512-NEXT: cnt z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <16 x i32>, <16 x i32>* %a + %op = load <16 x i32>, ptr %a %res = call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %op) - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @ctpop_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { +define void @ctpop_v32i32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: ctpop_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -619,13 +619,13 @@ define void @ctpop_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: cnt z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x i32>, <32 x i32>* %a + %op = load <32 x i32>, ptr %a %res = call <32 x i32> @llvm.ctpop.v32i32(<32 x i32> %op) - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @ctpop_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { +define void @ctpop_v64i32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: ctpop_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -633,9 +633,9 @@ define void @ctpop_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: cnt z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x i32>, <64 x i32>* %a + %op = load <64 x i32>, ptr %a %res = call <64 x i32> @llvm.ctpop.v64i32(<64 x i32> %op) - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -665,7 +665,7 @@ define <2 x i64> @ctpop_v2i64(<2 x i64> %op) vscale_range(2,0) #0 { ret <2 x i64> %res } -define void @ctpop_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { +define void @ctpop_v4i64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: ctpop_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -673,13 +673,13 @@ define void @ctpop_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: cnt z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <4 x i64>, <4 x i64>* %a + %op = load <4 x i64>, ptr %a %res = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %op) - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @ctpop_v8i64(<8 x i64>* %a) #0 { +define void @ctpop_v8i64(ptr %a) #0 { ; VBITS_GE_256-LABEL: ctpop_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -699,13 +699,13 @@ define void @ctpop_v8i64(<8 x i64>* %a) #0 { ; VBITS_GE_512-NEXT: cnt z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <8 x i64>, <8 x i64>* %a + %op = load <8 x i64>, ptr %a %res = call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %op) - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @ctpop_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { +define void @ctpop_v16i64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: ctpop_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -713,13 +713,13 @@ define void @ctpop_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: cnt z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x i64>, <16 x i64>* %a + %op = load <16 x i64>, ptr %a %res = call <16 x i64> @llvm.ctpop.v16i64(<16 x i64> %op) - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @ctpop_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { +define void @ctpop_v32i64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: ctpop_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -727,9 +727,9 @@ define void @ctpop_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: cnt z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x i64>, <32 x i64>* %a + %op = load <32 x i64>, ptr %a %res = call <32 x i64> @llvm.ctpop.v32i64(<32 x i64> %op) - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } @@ -761,7 +761,7 @@ define <16 x i8> @cttz_v16i8(<16 x i8> %op) vscale_range(2,0) #0 { ret <16 x i8> %res } -define void @cttz_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { +define void @cttz_v32i8(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: cttz_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -770,13 +770,13 @@ define void @cttz_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: clz z0.b, p0/m, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x i8>, <32 x i8>* %a + %op = load <32 x i8>, ptr %a %res = call <32 x i8> @llvm.cttz.v32i8(<32 x i8> %op) - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @cttz_v64i8(<64 x i8>* %a) #0 { +define void @cttz_v64i8(ptr %a) #0 { ; VBITS_GE_256-LABEL: cttz_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -799,13 +799,13 @@ define void @cttz_v64i8(<64 x i8>* %a) #0 { ; VBITS_GE_512-NEXT: clz z0.b, p0/m, z0.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <64 x i8>, <64 x i8>* %a + %op = load <64 x i8>, ptr %a %res = call <64 x i8> @llvm.cttz.v64i8(<64 x i8> %op) - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @cttz_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { +define void @cttz_v128i8(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: cttz_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -814,13 +814,13 @@ define void @cttz_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: clz z0.b, p0/m, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x i8>, <128 x i8>* %a + %op = load <128 x i8>, ptr %a %res = call <128 x i8> @llvm.cttz.v128i8(<128 x i8> %op) - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @cttz_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { +define void @cttz_v256i8(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: cttz_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -829,9 +829,9 @@ define void @cttz_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: clz z0.b, p0/m, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op = load <256 x i8>, <256 x i8>* %a + %op = load <256 x i8>, ptr %a %res = call <256 x i8> @llvm.cttz.v256i8(<256 x i8> %op) - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -859,7 +859,7 @@ define <8 x i16> @cttz_v8i16(<8 x i16> %op) vscale_range(2,0) #0 { ret <8 x i16> %res } -define void @cttz_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { +define void @cttz_v16i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: cttz_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -868,13 +868,13 @@ define void @cttz_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: clz z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x i16>, <16 x i16>* %a + %op = load <16 x i16>, ptr %a %res = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> %op) - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @cttz_v32i16(<32 x i16>* %a) #0 { +define void @cttz_v32i16(ptr %a) #0 { ; VBITS_GE_256-LABEL: cttz_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -897,13 +897,13 @@ define void @cttz_v32i16(<32 x i16>* %a) #0 { ; VBITS_GE_512-NEXT: clz z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <32 x i16>, <32 x i16>* %a + %op = load <32 x i16>, ptr %a %res = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %op) - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @cttz_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { +define void @cttz_v64i16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: cttz_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -912,13 +912,13 @@ define void @cttz_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: clz z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x i16>, <64 x i16>* %a + %op = load <64 x i16>, ptr %a %res = call <64 x i16> @llvm.cttz.v64i16(<64 x i16> %op) - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @cttz_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { +define void @cttz_v128i16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: cttz_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -927,9 +927,9 @@ define void @cttz_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: clz z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x i16>, <128 x i16>* %a + %op = load <128 x i16>, ptr %a %res = call <128 x i16> @llvm.cttz.v128i16(<128 x i16> %op) - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -959,7 +959,7 @@ define <4 x i32> @cttz_v4i32(<4 x i32> %op) vscale_range(2,0) #0 { ret <4 x i32> %res } -define void @cttz_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { +define void @cttz_v8i32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: cttz_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -968,13 +968,13 @@ define void @cttz_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: clz z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <8 x i32>, <8 x i32>* %a + %op = load <8 x i32>, ptr %a %res = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> %op) - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @cttz_v16i32(<16 x i32>* %a) #0 { +define void @cttz_v16i32(ptr %a) #0 { ; VBITS_GE_256-LABEL: cttz_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -997,13 +997,13 @@ define void @cttz_v16i32(<16 x i32>* %a) #0 { ; VBITS_GE_512-NEXT: clz z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <16 x i32>, <16 x i32>* %a + %op = load <16 x i32>, ptr %a %res = call <16 x i32> @llvm.cttz.v16i32(<16 x i32> %op) - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @cttz_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { +define void @cttz_v32i32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: cttz_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1012,13 +1012,13 @@ define void @cttz_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: clz z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x i32>, <32 x i32>* %a + %op = load <32 x i32>, ptr %a %res = call <32 x i32> @llvm.cttz.v32i32(<32 x i32> %op) - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @cttz_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { +define void @cttz_v64i32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: cttz_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1027,9 +1027,9 @@ define void @cttz_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: clz z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x i32>, <64 x i32>* %a + %op = load <64 x i32>, ptr %a %res = call <64 x i32> @llvm.cttz.v64i32(<64 x i32> %op) - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -1059,7 +1059,7 @@ define <2 x i64> @cttz_v2i64(<2 x i64> %op) vscale_range(2,0) #0 { ret <2 x i64> %res } -define void @cttz_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { +define void @cttz_v4i64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: cttz_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1068,13 +1068,13 @@ define void @cttz_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: clz z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <4 x i64>, <4 x i64>* %a + %op = load <4 x i64>, ptr %a %res = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %op) - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @cttz_v8i64(<8 x i64>* %a) #0 { +define void @cttz_v8i64(ptr %a) #0 { ; VBITS_GE_256-LABEL: cttz_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1097,13 +1097,13 @@ define void @cttz_v8i64(<8 x i64>* %a) #0 { ; VBITS_GE_512-NEXT: clz z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <8 x i64>, <8 x i64>* %a + %op = load <8 x i64>, ptr %a %res = call <8 x i64> @llvm.cttz.v8i64(<8 x i64> %op) - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @cttz_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { +define void @cttz_v16i64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: cttz_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1112,13 +1112,13 @@ define void @cttz_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: clz z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x i64>, <16 x i64>* %a + %op = load <16 x i64>, ptr %a %res = call <16 x i64> @llvm.cttz.v16i64(<16 x i64> %op) - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @cttz_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { +define void @cttz_v32i64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: cttz_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1127,9 +1127,9 @@ define void @cttz_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: clz z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x i64>, <32 x i64>* %a + %op = load <32 x i64>, ptr %a %res = call <32 x i64> @llvm.cttz.v32i64(<32 x i64> %op) - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-bitcast.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-bitcast.ll index 45008aa..a7ac7a8 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-bitcast.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-bitcast.ll @@ -6,45 +6,45 @@ target triple = "aarch64-unknown-linux-gnu" ; Don't use SVE for 64-bit vectors. -define void @bitcast_v4i16(<4 x i16> *%a, <4 x half>* %b) vscale_range(2,0) #0 { +define void @bitcast_v4i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: bitcast_v4i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret - %load = load volatile <4 x i16>, <4 x i16>* %a + %load = load volatile <4 x i16>, ptr %a %cast = bitcast <4 x i16> %load to <4 x half> - store volatile <4 x half> %cast, <4 x half>* %b + store volatile <4 x half> %cast, ptr %b ret void } ; Don't use SVE for 128-bit vectors. -define void @bitcast_v8i16(<8 x i16> *%a, <8 x half>* %b) vscale_range(2,0) #0 { +define void @bitcast_v8i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: bitcast_v8i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %load = load volatile <8 x i16>, <8 x i16>* %a + %load = load volatile <8 x i16>, ptr %a %cast = bitcast <8 x i16> %load to <8 x half> - store volatile <8 x half> %cast, <8 x half>* %b + store volatile <8 x half> %cast, ptr %b ret void } -define void @bitcast_v16i16(<16 x i16> *%a, <16 x half>* %b) vscale_range(2,0) #0 { +define void @bitcast_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: bitcast_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %load = load volatile <16 x i16>, <16 x i16>* %a + %load = load volatile <16 x i16>, ptr %a %cast = bitcast <16 x i16> %load to <16 x half> - store volatile <16 x half> %cast, <16 x half>* %b + store volatile <16 x half> %cast, ptr %b ret void } -define void @bitcast_v32i16(<32 x i16> *%a, <32 x half>* %b) #0 { +define void @bitcast_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: bitcast_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -61,78 +61,78 @@ define void @bitcast_v32i16(<32 x i16> *%a, <32 x half>* %b) #0 { ; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0] ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %load = load volatile <32 x i16>, <32 x i16>* %a + %load = load volatile <32 x i16>, ptr %a %cast = bitcast <32 x i16> %load to <32 x half> - store volatile <32 x half> %cast, <32 x half>* %b + store volatile <32 x half> %cast, ptr %b ret void } -define void @bitcast_v64i16(<64 x i16> *%a, <64 x half>* %b) vscale_range(8,0) #0 { +define void @bitcast_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: bitcast_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %load = load volatile <64 x i16>, <64 x i16>* %a + %load = load volatile <64 x i16>, ptr %a %cast = bitcast <64 x i16> %load to <64 x half> - store volatile <64 x half> %cast, <64 x half>* %b + store volatile <64 x half> %cast, ptr %b ret void } -define void @bitcast_v128i16(<128 x i16> *%a, <128 x half>* %b) vscale_range(16,0) #0 { +define void @bitcast_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: bitcast_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %load = load volatile <128 x i16>, <128 x i16>* %a + %load = load volatile <128 x i16>, ptr %a %cast = bitcast <128 x i16> %load to <128 x half> - store volatile <128 x half> %cast, <128 x half>* %b + store volatile <128 x half> %cast, ptr %b ret void } ; Don't use SVE for 64-bit vectors. -define void @bitcast_v2i32(<2 x i32> *%a, <2 x float>* %b) vscale_range(2,0) #0 { +define void @bitcast_v2i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: bitcast_v2i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret - %load = load volatile <2 x i32>, <2 x i32>* %a + %load = load volatile <2 x i32>, ptr %a %cast = bitcast <2 x i32> %load to <2 x float> - store volatile <2 x float> %cast, <2 x float>* %b + store volatile <2 x float> %cast, ptr %b ret void } ; Don't use SVE for 128-bit vectors. -define void @bitcast_v4i32(<4 x i32> *%a, <4 x float>* %b) vscale_range(2,0) #0 { +define void @bitcast_v4i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: bitcast_v4i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %load = load volatile <4 x i32>, <4 x i32>* %a + %load = load volatile <4 x i32>, ptr %a %cast = bitcast <4 x i32> %load to <4 x float> - store volatile <4 x float> %cast, <4 x float>* %b + store volatile <4 x float> %cast, ptr %b ret void } -define void @bitcast_v8i32(<8 x i32> *%a, <8 x float>* %b) vscale_range(2,0) #0 { +define void @bitcast_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: bitcast_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %load = load volatile <8 x i32>, <8 x i32>* %a + %load = load volatile <8 x i32>, ptr %a %cast = bitcast <8 x i32> %load to <8 x float> - store volatile <8 x float> %cast, <8 x float>* %b + store volatile <8 x float> %cast, ptr %b ret void } -define void @bitcast_v16i32(<16 x i32> *%a, <16 x float>* %b) #0 { +define void @bitcast_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: bitcast_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -149,78 +149,78 @@ define void @bitcast_v16i32(<16 x i32> *%a, <16 x float>* %b) #0 { ; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0] ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %load = load volatile <16 x i32>, <16 x i32>* %a + %load = load volatile <16 x i32>, ptr %a %cast = bitcast <16 x i32> %load to <16 x float> - store volatile <16 x float> %cast, <16 x float>* %b + store volatile <16 x float> %cast, ptr %b ret void } -define void @bitcast_v32i32(<32 x i32> *%a, <32 x float>* %b) vscale_range(8,0) #0 { +define void @bitcast_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: bitcast_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %load = load volatile <32 x i32>, <32 x i32>* %a + %load = load volatile <32 x i32>, ptr %a %cast = bitcast <32 x i32> %load to <32 x float> - store volatile <32 x float> %cast, <32 x float>* %b + store volatile <32 x float> %cast, ptr %b ret void } -define void @bitcast_v64i32(<64 x i32> *%a, <64 x float>* %b) vscale_range(16,0) #0 { +define void @bitcast_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: bitcast_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %load = load volatile <64 x i32>, <64 x i32>* %a + %load = load volatile <64 x i32>, ptr %a %cast = bitcast <64 x i32> %load to <64 x float> - store volatile <64 x float> %cast, <64 x float>* %b + store volatile <64 x float> %cast, ptr %b ret void } ; Don't use SVE for 64-bit vectors. -define void @bitcast_v1i64(<1 x i64> *%a, <1 x double>* %b) vscale_range(2,0) #0 { +define void @bitcast_v1i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: bitcast_v1i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret - %load = load volatile <1 x i64>, <1 x i64>* %a + %load = load volatile <1 x i64>, ptr %a %cast = bitcast <1 x i64> %load to <1 x double> - store volatile <1 x double> %cast, <1 x double>* %b + store volatile <1 x double> %cast, ptr %b ret void } ; Don't use SVE for 128-bit vectors. -define void @bitcast_v2i64(<2 x i64> *%a, <2 x double>* %b) vscale_range(2,0) #0 { +define void @bitcast_v2i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: bitcast_v2i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %load = load volatile <2 x i64>, <2 x i64>* %a + %load = load volatile <2 x i64>, ptr %a %cast = bitcast <2 x i64> %load to <2 x double> - store volatile <2 x double> %cast, <2 x double>* %b + store volatile <2 x double> %cast, ptr %b ret void } -define void @bitcast_v4i64(<4 x i64> *%a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @bitcast_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: bitcast_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %load = load volatile <4 x i64>, <4 x i64>* %a + %load = load volatile <4 x i64>, ptr %a %cast = bitcast <4 x i64> %load to <4 x double> - store volatile <4 x double> %cast, <4 x double>* %b + store volatile <4 x double> %cast, ptr %b ret void } -define void @bitcast_v8i64(<8 x i64> *%a, <8 x double>* %b) #0 { +define void @bitcast_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: bitcast_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -237,35 +237,35 @@ define void @bitcast_v8i64(<8 x i64> *%a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %load = load volatile <8 x i64>, <8 x i64>* %a + %load = load volatile <8 x i64>, ptr %a %cast = bitcast <8 x i64> %load to <8 x double> - store volatile <8 x double> %cast, <8 x double>* %b + store volatile <8 x double> %cast, ptr %b ret void } -define void @bitcast_v16i64(<16 x i64> *%a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @bitcast_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: bitcast_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %load = load volatile <16 x i64>, <16 x i64>* %a + %load = load volatile <16 x i64>, ptr %a %cast = bitcast <16 x i64> %load to <16 x double> - store volatile <16 x double> %cast, <16 x double>* %b + store volatile <16 x double> %cast, ptr %b ret void } -define void @bitcast_v32i64(<32 x i64> *%a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @bitcast_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: bitcast_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %load = load volatile <32 x i64>, <32 x i64>* %a + %load = load volatile <32 x i64>, ptr %a %cast = bitcast <32 x i64> %load to <32 x double> - store volatile <32 x double> %cast, <32 x double>* %b + store volatile <32 x double> %cast, ptr %b ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll index 0d484c9..ec3e1d8 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll @@ -9,7 +9,7 @@ target triple = "aarch64" ; this is implemented, this test will be fleshed out. ; -define <8 x i32> @fixed_bitselect_v8i32(<8 x i32>* %pre_cond_ptr, <8 x i32>* %left_ptr, <8 x i32>* %right_ptr) #0 { +define <8 x i32> @fixed_bitselect_v8i32(ptr %pre_cond_ptr, ptr %left_ptr, ptr %right_ptr) #0 { ; CHECK-LABEL: fixed_bitselect_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -24,9 +24,9 @@ define <8 x i32> @fixed_bitselect_v8i32(<8 x i32>* %pre_cond_ptr, <8 x i32>* %le ; CHECK-NEXT: orr z0.d, z1.d, z0.d ; CHECK-NEXT: st1w { z0.s }, p0, [x8] ; CHECK-NEXT: ret - %pre_cond = load <8 x i32>, <8 x i32>* %pre_cond_ptr - %left = load <8 x i32>, <8 x i32>* %left_ptr - %right = load <8 x i32>, <8 x i32>* %right_ptr + %pre_cond = load <8 x i32>, ptr %pre_cond_ptr + %left = load <8 x i32>, ptr %left_ptr + %right = load <8 x i32>, ptr %right_ptr %neg_cond = sub <8 x i32> zeroinitializer, %pre_cond %min_cond = add <8 x i32> %pre_cond, diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll index 50b0be2..41f6c1f 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll @@ -32,7 +32,7 @@ define <16 x i8> @concat_v16i8(<8 x i8> %op1, <8 x i8> %op2) vscale_range(2,0) # ret <16 x i8> %res } -define void @concat_v32i8(<16 x i8>* %a, <16 x i8>* %b, <32 x i8>* %c) vscale_range(2,0) #0 { +define void @concat_v32i8(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: concat_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x1] @@ -42,17 +42,17 @@ define void @concat_v32i8(<16 x i8>* %a, <16 x i8>* %b, <32 x i8>* %c) vscale_ra ; CHECK-NEXT: ptrue p0.b, vl32 ; CHECK-NEXT: st1b { z1.b }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x i8>, <16 x i8>* %a - %op2 = load <16 x i8>, <16 x i8>* %b + %op1 = load <16 x i8>, ptr %a + %op2 = load <16 x i8>, ptr %b %res = shufflevector <16 x i8> %op1, <16 x i8> %op2, <32 x i32> - store <32 x i8> %res, <32 x i8>* %c + store <32 x i8> %res, ptr %c ret void } -define void @concat_v64i8(<32 x i8>* %a, <32 x i8>* %b, <64 x i8>* %c) #0 { +define void @concat_v64i8(ptr %a, ptr %b, ptr %c) #0 { ; VBITS_GE_256-LABEL: concat_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.b, vl32 @@ -72,8 +72,8 @@ define void @concat_v64i8(<32 x i8>* %a, <32 x i8>* %b, <64 x i8>* %c) #0 { ; VBITS_GE_512-NEXT: ptrue p0.b, vl64 ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x2] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %res = shufflevector <32 x i8> %op1, <32 x i8> %op2, <64 x i32> * %a, <32 x i8>* %b, <64 x i8>* %c) #0 { i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63> - store <64 x i8> %res, <64 x i8>* %c + store <64 x i8> %res, ptr %c ret void } -define void @concat_v128i8(<64 x i8>* %a, <64 x i8>* %b, <128 x i8>* %c) vscale_range(8,0) #0 { +define void @concat_v128i8(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 { ; CHECK-LABEL: concat_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -96,8 +96,8 @@ define void @concat_v128i8(<64 x i8>* %a, <64 x i8>* %b, <128 x i8>* %c) vscale_ ; CHECK-NEXT: ptrue p0.b, vl128 ; CHECK-NEXT: st1b { z0.b }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = shufflevector <64 x i8> %op1, <64 x i8> %op2, <128 x i32> * %a, <64 x i8>* %b, <128 x i8>* %c) vscale_ i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127> - store <128 x i8> %res, <128 x i8>* %c + store <128 x i8> %res, ptr %c ret void } -define void @concat_v256i8(<128 x i8>* %a, <128 x i8>* %b, <256 x i8>* %c) vscale_range(16,0) #0 { +define void @concat_v256i8(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 { ; CHECK-LABEL: concat_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -128,8 +128,8 @@ define void @concat_v256i8(<128 x i8>* %a, <128 x i8>* %b, <256 x i8>* %c) vscal ; CHECK-NEXT: ptrue p0.b, vl256 ; CHECK-NEXT: st1b { z0.b }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %res = shufflevector <128 x i8> %op1, <128 x i8> %op2, <256 x i32> * %a, <128 x i8>* %b, <256 x i8>* %c) vscal i32 232, i32 233, i32 234, i32 235, i32 236, i32 237, i32 238, i32 239, i32 240, i32 241, i32 242, i32 243, i32 244, i32 245, i32 246, i32 247, i32 248, i32 249, i32 250, i32 251, i32 252, i32 253, i32 254, i32 255> - store <256 x i8> %res, <256 x i8>* %c + store <256 x i8> %res, ptr %c ret void } @@ -192,7 +192,7 @@ define <8 x i16> @concat_v8i16(<4 x i16> %op1, <4 x i16> %op2) vscale_range(2,0) ret <8 x i16> %res } -define void @concat_v16i16(<8 x i16>* %a, <8 x i16>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @concat_v16i16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: concat_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x1] @@ -202,15 +202,15 @@ define void @concat_v16i16(<8 x i16>* %a, <8 x i16>* %b, <16 x i16>* %c) vscale_ ; CHECK-NEXT: ptrue p0.h, vl16 ; CHECK-NEXT: st1h { z1.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <8 x i16>, <8 x i16>* %a - %op2 = load <8 x i16>, <8 x i16>* %b + %op1 = load <8 x i16>, ptr %a + %op2 = load <8 x i16>, ptr %b %res = shufflevector <8 x i16> %op1, <8 x i16> %op2, <16 x i32> - store <16 x i16> %res, <16 x i16>* %c + store <16 x i16> %res, ptr %c ret void } -define void @concat_v32i16(<16 x i16>* %a, <16 x i16>* %b, <32 x i16>* %c) #0 { +define void @concat_v32i16(ptr %a, ptr %b, ptr %c) #0 { ; VBITS_GE_256-LABEL: concat_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.h, vl16 @@ -230,17 +230,17 @@ define void @concat_v32i16(<16 x i16>* %a, <16 x i16>* %b, <32 x i16>* %c) #0 { ; VBITS_GE_512-NEXT: ptrue p0.h, vl32 ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x2] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %res = shufflevector <16 x i16> %op1, <16 x i16> %op2, <32 x i32> - store <32 x i16> %res, <32 x i16>* %c + store <32 x i16> %res, ptr %c ret void } -define void @concat_v64i16(<32 x i16>* %a, <32 x i16>* %b, <64 x i16>* %c) vscale_range(8,0) #0 { +define void @concat_v64i16(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 { ; CHECK-LABEL: concat_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -250,8 +250,8 @@ define void @concat_v64i16(<32 x i16>* %a, <32 x i16>* %b, <64 x i16>* %c) vscal ; CHECK-NEXT: ptrue p0.h, vl64 ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = shufflevector <32 x i16> %op1, <32 x i16> %op2, <64 x i32> * %a, <32 x i16>* %b, <64 x i16>* %c) vscal i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63> - store <64 x i16> %res, <64 x i16>* %c + store <64 x i16> %res, ptr %c ret void } -define void @concat_v128i16(<64 x i16>* %a, <64 x i16>* %b, <128 x i16>* %c) vscale_range(16,0) #0 { +define void @concat_v128i16(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 { ; CHECK-LABEL: concat_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -274,8 +274,8 @@ define void @concat_v128i16(<64 x i16>* %a, <64 x i16>* %b, <128 x i16>* %c) vsc ; CHECK-NEXT: ptrue p0.h, vl128 ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %res = shufflevector <64 x i16> %op1, <64 x i16> %op2, <128 x i32> * %a, <64 x i16>* %b, <128 x i16>* %c) vsc i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127> - store <128 x i16> %res, <128 x i16>* %c + store <128 x i16> %res, ptr %c ret void } @@ -322,7 +322,7 @@ define <4 x i32> @concat_v4i32(<2 x i32> %op1, <2 x i32> %op2) vscale_range(2,0) ret <4 x i32> %res } -define void @concat_v8i32(<4 x i32>* %a, <4 x i32>* %b, <8 x i32>* %c) vscale_range(2,0) #0 { +define void @concat_v8i32(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: concat_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x1] @@ -332,14 +332,14 @@ define void @concat_v8i32(<4 x i32>* %a, <4 x i32>* %b, <8 x i32>* %c) vscale_ra ; CHECK-NEXT: ptrue p0.s, vl8 ; CHECK-NEXT: st1w { z1.s }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <4 x i32>, <4 x i32>* %a - %op2 = load <4 x i32>, <4 x i32>* %b + %op1 = load <4 x i32>, ptr %a + %op2 = load <4 x i32>, ptr %b %res = shufflevector <4 x i32> %op1, <4 x i32> %op2, <8 x i32> - store <8 x i32> %res, <8 x i32>* %c + store <8 x i32> %res, ptr %c ret void } -define void @concat_v16i32(<8 x i32>* %a, <8 x i32>* %b, <16 x i32>* %c) #0 { +define void @concat_v16i32(ptr %a, ptr %b, ptr %c) #0 { ; VBITS_GE_256-LABEL: concat_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.s, vl8 @@ -359,15 +359,15 @@ define void @concat_v16i32(<8 x i32>* %a, <8 x i32>* %b, <16 x i32>* %c) #0 { ; VBITS_GE_512-NEXT: ptrue p0.s, vl16 ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x2] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %res = shufflevector <8 x i32> %op1, <8 x i32> %op2, <16 x i32> - store <16 x i32> %res, <16 x i32>* %c + store <16 x i32> %res, ptr %c ret void } -define void @concat_v32i32(<16 x i32>* %a, <16 x i32>* %b, <32 x i32>* %c) vscale_range(8,0) #0 { +define void @concat_v32i32(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 { ; CHECK-LABEL: concat_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -377,17 +377,17 @@ define void @concat_v32i32(<16 x i32>* %a, <16 x i32>* %b, <32 x i32>* %c) vscal ; CHECK-NEXT: ptrue p0.s, vl32 ; CHECK-NEXT: st1w { z0.s }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %res = shufflevector <16 x i32> %op1, <16 x i32> %op2, <32 x i32> - store <32 x i32> %res, <32 x i32>* %c + store <32 x i32> %res, ptr %c ret void } -define void @concat_v64i32(<32 x i32>* %a, <32 x i32>* %b, <64 x i32>* %c) vscale_range(16,0) #0 { +define void @concat_v64i32(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 { ; CHECK-LABEL: concat_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -397,8 +397,8 @@ define void @concat_v64i32(<32 x i32>* %a, <32 x i32>* %b, <64 x i32>* %c) vscal ; CHECK-NEXT: ptrue p0.s, vl64 ; CHECK-NEXT: st1w { z0.s }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %res = shufflevector <32 x i32> %op1, <32 x i32> %op2, <64 x i32> * %a, <32 x i32>* %b, <64 x i32>* %c) vscal i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63> - store <64 x i32> %res, <64 x i32>* %c + store <64 x i32> %res, ptr %c ret void } @@ -427,7 +427,7 @@ define <2 x i64> @concat_v2i64(<1 x i64> %op1, <1 x i64> %op2) vscale_range(2,0) ret <2 x i64> %res } -define void @concat_v4i64(<2 x i64>* %a, <2 x i64>* %b, <4 x i64>* %c) vscale_range(2,0) #0 { +define void @concat_v4i64(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: concat_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x1] @@ -437,14 +437,14 @@ define void @concat_v4i64(<2 x i64>* %a, <2 x i64>* %b, <4 x i64>* %c) vscale_ra ; CHECK-NEXT: ptrue p0.d, vl4 ; CHECK-NEXT: st1d { z1.d }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <2 x i64>, <2 x i64>* %a - %op2 = load <2 x i64>, <2 x i64>* %b + %op1 = load <2 x i64>, ptr %a + %op2 = load <2 x i64>, ptr %b %res = shufflevector <2 x i64> %op1, <2 x i64> %op2, <4 x i32> - store <4 x i64> %res, <4 x i64>* %c + store <4 x i64> %res, ptr %c ret void } -define void @concat_v8i64(<4 x i64>* %a, <4 x i64>* %b, <8 x i64>* %c) #0 { +define void @concat_v8i64(ptr %a, ptr %b, ptr %c) #0 { ; VBITS_GE_256-LABEL: concat_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.d, vl4 @@ -464,14 +464,14 @@ define void @concat_v8i64(<4 x i64>* %a, <4 x i64>* %b, <8 x i64>* %c) #0 { ; VBITS_GE_512-NEXT: ptrue p0.d, vl8 ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x2] ; VBITS_GE_512-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %res = shufflevector <4 x i64> %op1, <4 x i64> %op2, <8 x i32> - store <8 x i64> %res, <8 x i64>* %c + store <8 x i64> %res, ptr %c ret void } -define void @concat_v16i64(<8 x i64>* %a, <8 x i64>* %b, <16 x i64>* %c) vscale_range(8,0) #0 { +define void @concat_v16i64(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 { ; CHECK-LABEL: concat_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl8 @@ -481,15 +481,15 @@ define void @concat_v16i64(<8 x i64>* %a, <8 x i64>* %b, <16 x i64>* %c) vscale_ ; CHECK-NEXT: ptrue p0.d, vl16 ; CHECK-NEXT: st1d { z0.d }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %res = shufflevector <8 x i64> %op1, <8 x i64> %op2, <16 x i32> - store <16 x i64> %res, <16 x i64>* %c + store <16 x i64> %res, ptr %c ret void } -define void @concat_v32i64(<16 x i64>* %a, <16 x i64>* %b, <32 x i64>* %c) vscale_range(16,0) #0 { +define void @concat_v32i64(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 { ; CHECK-LABEL: concat_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -499,13 +499,13 @@ define void @concat_v32i64(<16 x i64>* %a, <16 x i64>* %b, <32 x i64>* %c) vscal ; CHECK-NEXT: ptrue p0.d, vl32 ; CHECK-NEXT: st1d { z0.d }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %res = shufflevector <16 x i64> %op1, <16 x i64> %op2, <32 x i32> - store <32 x i64> %res, <32 x i64>* %c + store <32 x i64> %res, ptr %c ret void } @@ -535,7 +535,7 @@ define <8 x half> @concat_v8f16(<4 x half> %op1, <4 x half> %op2) vscale_range(2 ret <8 x half> %res } -define void @concat_v16f16(<8 x half>* %a, <8 x half>* %b, <16 x half>* %c) vscale_range(2,0) #0 { +define void @concat_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: concat_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x1] @@ -545,15 +545,15 @@ define void @concat_v16f16(<8 x half>* %a, <8 x half>* %b, <16 x half>* %c) vsca ; CHECK-NEXT: ptrue p0.h, vl16 ; CHECK-NEXT: st1h { z1.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <8 x half>, <8 x half>* %a - %op2 = load <8 x half>, <8 x half>* %b + %op1 = load <8 x half>, ptr %a + %op2 = load <8 x half>, ptr %b %res = shufflevector <8 x half> %op1, <8 x half> %op2, <16 x i32> - store <16 x half> %res, <16 x half>* %c + store <16 x half> %res, ptr %c ret void } -define void @concat_v32f16(<16 x half>* %a, <16 x half>* %b, <32 x half>* %c) #0 { +define void @concat_v32f16(ptr %a, ptr %b, ptr %c) #0 { ; VBITS_GE_256-LABEL: concat_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.h, vl16 @@ -573,17 +573,17 @@ define void @concat_v32f16(<16 x half>* %a, <16 x half>* %b, <32 x half>* %c) #0 ; VBITS_GE_512-NEXT: ptrue p0.h, vl32 ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x2] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %res = shufflevector <16 x half> %op1, <16 x half> %op2, <32 x i32> - store <32 x half> %res, <32 x half>* %c + store <32 x half> %res, ptr %c ret void } -define void @concat_v64f16(<32 x half>* %a, <32 x half>* %b, <64 x half>* %c) vscale_range(8,0) #0 { +define void @concat_v64f16(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 { ; CHECK-LABEL: concat_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -593,8 +593,8 @@ define void @concat_v64f16(<32 x half>* %a, <32 x half>* %b, <64 x half>* %c) vs ; CHECK-NEXT: ptrue p0.h, vl64 ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a - %op2 = load <32 x half>, <32 x half>* %b + %op1 = load <32 x half>, ptr %a + %op2 = load <32 x half>, ptr %b %res = shufflevector <32 x half> %op1, <32 x half> %op2, <64 x i32> * %a, <32 x half>* %b, <64 x half>* %c) vs i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63> - store <64 x half> %res, <64 x half>* %c + store <64 x half> %res, ptr %c ret void } -define void @concat_v128f16(<64 x half>* %a, <64 x half>* %b, <128 x half>* %c) vscale_range(16,0) #0 { +define void @concat_v128f16(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 { ; CHECK-LABEL: concat_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -617,8 +617,8 @@ define void @concat_v128f16(<64 x half>* %a, <64 x half>* %b, <128 x half>* %c) ; CHECK-NEXT: ptrue p0.h, vl128 ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a - %op2 = load <64 x half>, <64 x half>* %b + %op1 = load <64 x half>, ptr %a + %op2 = load <64 x half>, ptr %b %res = shufflevector <64 x half> %op1, <64 x half> %op2, <128 x i32> * %a, <64 x half>* %b, <128 x half>* %c) i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127> - store <128 x half> %res, <128 x half>* %c + store <128 x half> %res, ptr %c ret void } @@ -665,7 +665,7 @@ define <4 x float> @concat_v4f32(<2 x float> %op1, <2 x float> %op2) vscale_rang ret <4 x float> %res } -define void @concat_v8f32(<4 x float>* %a, <4 x float>* %b, <8 x float>* %c) vscale_range(2,0) #0 { +define void @concat_v8f32(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: concat_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x1] @@ -675,14 +675,14 @@ define void @concat_v8f32(<4 x float>* %a, <4 x float>* %b, <8 x float>* %c) vsc ; CHECK-NEXT: ptrue p0.s, vl8 ; CHECK-NEXT: st1w { z1.s }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <4 x float>, <4 x float>* %a - %op2 = load <4 x float>, <4 x float>* %b + %op1 = load <4 x float>, ptr %a + %op2 = load <4 x float>, ptr %b %res = shufflevector <4 x float> %op1, <4 x float> %op2, <8 x i32> - store <8 x float> %res, <8 x float>* %c + store <8 x float> %res, ptr %c ret void } -define void @concat_v16f32(<8 x float>* %a, <8 x float>* %b, <16 x float>* %c) #0 { +define void @concat_v16f32(ptr %a, ptr %b, ptr %c) #0 { ; VBITS_GE_256-LABEL: concat_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.s, vl8 @@ -702,15 +702,15 @@ define void @concat_v16f32(<8 x float>* %a, <8 x float>* %b, <16 x float>* %c) # ; VBITS_GE_512-NEXT: ptrue p0.s, vl16 ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x2] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a - %op2 = load <8 x float>, <8 x float>* %b + %op1 = load <8 x float>, ptr %a + %op2 = load <8 x float>, ptr %b %res = shufflevector <8 x float> %op1, <8 x float> %op2, <16 x i32> - store <16 x float> %res, <16 x float>* %c + store <16 x float> %res, ptr %c ret void } -define void @concat_v32f32(<16 x float>* %a, <16 x float>* %b, <32 x float>* %c) vscale_range(8,0) #0 { +define void @concat_v32f32(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 { ; CHECK-LABEL: concat_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -720,17 +720,17 @@ define void @concat_v32f32(<16 x float>* %a, <16 x float>* %b, <32 x float>* %c) ; CHECK-NEXT: ptrue p0.s, vl32 ; CHECK-NEXT: st1w { z0.s }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a - %op2 = load <16 x float>, <16 x float>* %b + %op1 = load <16 x float>, ptr %a + %op2 = load <16 x float>, ptr %b %res = shufflevector <16 x float> %op1, <16 x float> %op2, <32 x i32> - store <32 x float> %res, <32 x float>* %c + store <32 x float> %res, ptr %c ret void } -define void @concat_v64f32(<32 x float>* %a, <32 x float>* %b, <64 x float>* %c) vscale_range(16,0) #0 { +define void @concat_v64f32(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 { ; CHECK-LABEL: concat_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -740,8 +740,8 @@ define void @concat_v64f32(<32 x float>* %a, <32 x float>* %b, <64 x float>* %c) ; CHECK-NEXT: ptrue p0.s, vl64 ; CHECK-NEXT: st1w { z0.s }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a - %op2 = load <32 x float>, <32 x float>* %b + %op1 = load <32 x float>, ptr %a + %op2 = load <32 x float>, ptr %b %res = shufflevector <32 x float> %op1, <32 x float> %op2, <64 x i32> * %a, <32 x float>* %b, <64 x float>* %c) i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63> - store <64 x float> %res, <64 x float>* %c + store <64 x float> %res, ptr %c ret void } @@ -770,7 +770,7 @@ define <2 x double> @concat_v2f64(<1 x double> %op1, <1 x double> %op2) vscale_r ret <2 x double> %res } -define void @concat_v4f64(<2 x double>* %a, <2 x double>* %b, <4 x double>* %c) vscale_range(2,0) #0 { +define void @concat_v4f64(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: concat_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x1] @@ -780,14 +780,14 @@ define void @concat_v4f64(<2 x double>* %a, <2 x double>* %b, <4 x double>* %c) ; CHECK-NEXT: ptrue p0.d, vl4 ; CHECK-NEXT: st1d { z1.d }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <2 x double>, <2 x double>* %a - %op2 = load <2 x double>, <2 x double>* %b + %op1 = load <2 x double>, ptr %a + %op2 = load <2 x double>, ptr %b %res = shufflevector <2 x double> %op1, <2 x double> %op2, <4 x i32> - store <4 x double> %res, <4 x double>* %c + store <4 x double> %res, ptr %c ret void } -define void @concat_v8f64(<4 x double>* %a, <4 x double>* %b, <8 x double>* %c) #0 { +define void @concat_v8f64(ptr %a, ptr %b, ptr %c) #0 { ; VBITS_GE_256-LABEL: concat_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.d, vl4 @@ -807,14 +807,14 @@ define void @concat_v8f64(<4 x double>* %a, <4 x double>* %b, <8 x double>* %c) ; VBITS_GE_512-NEXT: ptrue p0.d, vl8 ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x2] ; VBITS_GE_512-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a - %op2 = load <4 x double>, <4 x double>* %b + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b %res = shufflevector <4 x double> %op1, <4 x double> %op2, <8 x i32> - store <8 x double> %res, <8 x double>* %c + store <8 x double> %res, ptr %c ret void } -define void @concat_v16f64(<8 x double>* %a, <8 x double>* %b, <16 x double>* %c) vscale_range(8,0) #0 { +define void @concat_v16f64(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 { ; CHECK-LABEL: concat_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl8 @@ -824,15 +824,15 @@ define void @concat_v16f64(<8 x double>* %a, <8 x double>* %b, <16 x double>* %c ; CHECK-NEXT: ptrue p0.d, vl16 ; CHECK-NEXT: st1d { z0.d }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a - %op2 = load <8 x double>, <8 x double>* %b + %op1 = load <8 x double>, ptr %a + %op2 = load <8 x double>, ptr %b %res = shufflevector <8 x double> %op1, <8 x double> %op2, <16 x i32> - store <16 x double> %res, <16 x double>* %c + store <16 x double> %res, ptr %c ret void } -define void @concat_v32f64(<16 x double>* %a, <16 x double>* %b, <32 x double>* %c) vscale_range(16,0) #0 { +define void @concat_v32f64(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 { ; CHECK-LABEL: concat_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -842,13 +842,13 @@ define void @concat_v32f64(<16 x double>* %a, <16 x double>* %b, <32 x double>* ; CHECK-NEXT: ptrue p0.d, vl32 ; CHECK-NEXT: st1d { z0.d }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a - %op2 = load <16 x double>, <16 x double>* %b + %op1 = load <16 x double>, ptr %a + %op2 = load <16 x double>, ptr %b %res = shufflevector <16 x double> %op1, <16 x double> %op2, <32 x i32> - store <32 x double> %res, <32 x double>* %c + store <32 x double> %res, ptr %c ret void } @@ -856,59 +856,59 @@ define void @concat_v32f64(<16 x double>* %a, <16 x double>* %b, <32 x double>* ; undef ; -define void @concat_v32i8_undef(<16 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @concat_v32i8_undef(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: concat_v32i8_undef: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ptrue p0.b, vl32 ; CHECK-NEXT: st1b { z0.b }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x i8>, <16 x i8>* %a + %op1 = load <16 x i8>, ptr %a %res = shufflevector <16 x i8> %op1, <16 x i8> undef, <32 x i32> - store <32 x i8> %res, <32 x i8>* %b + store <32 x i8> %res, ptr %b ret void } -define void @concat_v16i16_undef(<8 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @concat_v16i16_undef(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: concat_v16i16_undef: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ptrue p0.h, vl16 ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <8 x i16>, <8 x i16>* %a + %op1 = load <8 x i16>, ptr %a %res = shufflevector <8 x i16> %op1, <8 x i16> undef, <16 x i32> - store <16 x i16> %res, <16 x i16>* %b + store <16 x i16> %res, ptr %b ret void } -define void @concat_v8i32_undef(<4 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @concat_v8i32_undef(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: concat_v8i32_undef: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ptrue p0.s, vl8 ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x i32>, <4 x i32>* %a + %op1 = load <4 x i32>, ptr %a %res = shufflevector <4 x i32> %op1, <4 x i32> undef, <8 x i32> - store <8 x i32> %res, <8 x i32>* %b + store <8 x i32> %res, ptr %b ret void } -define void @concat_v4i64_undef(<2 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @concat_v4i64_undef(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: concat_v4i64_undef: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ptrue p0.d, vl4 ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <2 x i64>, <2 x i64>* %a + %op1 = load <2 x i64>, ptr %a %res = shufflevector <2 x i64> %op1, <2 x i64> undef, <4 x i32> - store <4 x i64> %res, <4 x i64>* %b + store <4 x i64> %res, ptr %b ret void } @@ -916,64 +916,64 @@ define void @concat_v4i64_undef(<2 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) ; > 2 operands ; -define void @concat_v32i8_4op(<8 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @concat_v32i8_4op(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: concat_v32i8_4op: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ptrue p0.b, vl32 ; CHECK-NEXT: st1b { z0.b }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <8 x i8>, <8 x i8>* %a + %op1 = load <8 x i8>, ptr %a %shuffle = shufflevector <8 x i8> %op1, <8 x i8> undef, <16 x i32> %res = shufflevector <16 x i8> %shuffle, <16 x i8> undef, <32 x i32> - store <32 x i8> %res, <32 x i8>* %b + store <32 x i8> %res, ptr %b ret void } -define void @concat_v16i16_4op(<4 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @concat_v16i16_4op(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: concat_v16i16_4op: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ptrue p0.h, vl16 ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x i16>, <4 x i16>* %a + %op1 = load <4 x i16>, ptr %a %shuffle = shufflevector <4 x i16> %op1, <4 x i16> undef, <8 x i32> %res = shufflevector <8 x i16> %shuffle, <8 x i16> undef, <16 x i32> - store <16 x i16> %res, <16 x i16>* %b + store <16 x i16> %res, ptr %b ret void } -define void @concat_v8i32_4op(<2 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @concat_v8i32_4op(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: concat_v8i32_4op: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ptrue p0.s, vl8 ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <2 x i32>, <2 x i32>* %a + %op1 = load <2 x i32>, ptr %a %shuffle = shufflevector <2 x i32> %op1, <2 x i32> undef, <4 x i32> %res = shufflevector <4 x i32> %shuffle, <4 x i32> undef, <8 x i32> - store <8 x i32> %res, <8 x i32>* %b + store <8 x i32> %res, ptr %b ret void } -define void @concat_v4i64_4op(<1 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @concat_v4i64_4op(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: concat_v4i64_4op: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ptrue p0.d, vl4 ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <1 x i64>, <1 x i64>* %a + %op1 = load <1 x i64>, ptr %a %shuffle = shufflevector <1 x i64> %op1, <1 x i64> undef, <2 x i32> %res = shufflevector <2 x i64> %shuffle, <2 x i64> undef, <4 x i32> - store <4 x i64> %res, <4 x i64>* %b + store <4 x i64> %res, ptr %b ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll index fde767a..2aec28e 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll @@ -4,19 +4,19 @@ target triple = "aarch64-unknown-linux-gnu" -define <4 x i32> @load_zext_v4i16i32(<4 x i16>* %ap) vscale_range(2,0) #0 { +define <4 x i32> @load_zext_v4i16i32(ptr %ap) vscale_range(2,0) #0 { ; CHECK-LABEL: load_zext_v4i16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ushll v0.4s, v0.4h, #0 ; CHECK-NEXT: ret - %a = load <4 x i16>, <4 x i16>* %ap + %a = load <4 x i16>, ptr %ap %val = zext <4 x i16> %a to <4 x i32> ret <4 x i32> %val } ; Don't try to use SVE for irregular types. -define <2 x i256> @load_zext_v2i64i256(<2 x i64>* %ap) #0 { +define <2 x i256> @load_zext_v2i64i256(ptr %ap) #0 { ; CHECK-LABEL: load_zext_v2i64i256: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -29,48 +29,48 @@ define <2 x i256> @load_zext_v2i64i256(<2 x i64>* %ap) #0 { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: mov x7, xzr ; CHECK-NEXT: ret - %a = load <2 x i64>, <2 x i64>* %ap + %a = load <2 x i64>, ptr %ap %val = zext <2 x i64> %a to <2 x i256> ret <2 x i256> %val } -define <8 x i32> @load_zext_v8i16i32(<8 x i16>* %ap) vscale_range(2,0) #0 { +define <8 x i32> @load_zext_v8i16i32(ptr %ap) vscale_range(2,0) #0 { ; CHECK-LABEL: load_zext_v8i16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x8] ; CHECK-NEXT: ret - %a = load <8 x i16>, <8 x i16>* %ap + %a = load <8 x i16>, ptr %ap %val = zext <8 x i16> %a to <8 x i32> ret <8 x i32> %val } -define <16 x i32> @load_zext_v16i16i32(<16 x i16>* %ap) vscale_range(4,0) #0 { +define <16 x i32> @load_zext_v16i16i32(ptr %ap) vscale_range(4,0) #0 { ; CHECK-LABEL: load_zext_v16i16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x8] ; CHECK-NEXT: ret - %a = load <16 x i16>, <16 x i16>* %ap + %a = load <16 x i16>, ptr %ap %val = zext <16 x i16> %a to <16 x i32> ret <16 x i32> %val } -define <32 x i32> @load_zext_v32i16i32(<32 x i16>* %ap) vscale_range(8,0) #0 { +define <32 x i32> @load_zext_v32i16i32(ptr %ap) vscale_range(8,0) #0 { ; CHECK-LABEL: load_zext_v32i16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x8] ; CHECK-NEXT: ret - %a = load <32 x i16>, <32 x i16>* %ap + %a = load <32 x i16>, ptr %ap %val = zext <32 x i16> %a to <32 x i32> ret <32 x i32> %val } -define <64 x i32> @load_zext_v64i16i32(<64 x i16>* %ap) #0 { +define <64 x i32> @load_zext_v64i16i32(ptr %ap) #0 { ; VBITS_GE_1024-LABEL: load_zext_v64i16i32: ; VBITS_GE_1024: // %bb.0: ; VBITS_GE_1024-NEXT: ptrue p0.h, vl64 @@ -90,59 +90,59 @@ define <64 x i32> @load_zext_v64i16i32(<64 x i16>* %ap) #0 { ; VBITS_GE_2048-NEXT: ld1h { z0.s }, p0/z, [x0] ; VBITS_GE_2048-NEXT: st1w { z0.s }, p0, [x8] ; VBITS_GE_2048-NEXT: ret - %a = load <64 x i16>, <64 x i16>* %ap + %a = load <64 x i16>, ptr %ap %val = zext <64 x i16> %a to <64 x i32> ret <64 x i32> %val } -define <4 x i32> @load_sext_v4i16i32(<4 x i16>* %ap) vscale_range(2,0) #0 { +define <4 x i32> @load_sext_v4i16i32(ptr %ap) vscale_range(2,0) #0 { ; CHECK-LABEL: load_sext_v4i16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: sshll v0.4s, v0.4h, #0 ; CHECK-NEXT: ret - %a = load <4 x i16>, <4 x i16>* %ap + %a = load <4 x i16>, ptr %ap %val = sext <4 x i16> %a to <4 x i32> ret <4 x i32> %val } -define <8 x i32> @load_sext_v8i16i32(<8 x i16>* %ap) vscale_range(2,0) #0 { +define <8 x i32> @load_sext_v8i16i32(ptr %ap) vscale_range(2,0) #0 { ; CHECK-LABEL: load_sext_v8i16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 ; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x8] ; CHECK-NEXT: ret - %a = load <8 x i16>, <8 x i16>* %ap + %a = load <8 x i16>, ptr %ap %val = sext <8 x i16> %a to <8 x i32> ret <8 x i32> %val } -define <16 x i32> @load_sext_v16i16i32(<16 x i16>* %ap) vscale_range(4,0) #0 { +define <16 x i32> @load_sext_v16i16i32(ptr %ap) vscale_range(4,0) #0 { ; CHECK-LABEL: load_sext_v16i16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 ; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x8] ; CHECK-NEXT: ret - %a = load <16 x i16>, <16 x i16>* %ap + %a = load <16 x i16>, ptr %ap %val = sext <16 x i16> %a to <16 x i32> ret <16 x i32> %val } -define <32 x i32> @load_sext_v32i16i32(<32 x i16>* %ap) vscale_range(8,0) #0 { +define <32 x i32> @load_sext_v32i16i32(ptr %ap) vscale_range(8,0) #0 { ; CHECK-LABEL: load_sext_v32i16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 ; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x8] ; CHECK-NEXT: ret - %a = load <32 x i16>, <32 x i16>* %ap + %a = load <32 x i16>, ptr %ap %val = sext <32 x i16> %a to <32 x i32> ret <32 x i32> %val } -define <64 x i32> @load_sext_v64i16i32(<64 x i16>* %ap) #0 { +define <64 x i32> @load_sext_v64i16i32(ptr %ap) #0 { ; VBITS_GE_1024-LABEL: load_sext_v64i16i32: ; VBITS_GE_1024: // %bb.0: ; VBITS_GE_1024-NEXT: ptrue p0.h, vl64 @@ -162,12 +162,12 @@ define <64 x i32> @load_sext_v64i16i32(<64 x i16>* %ap) #0 { ; VBITS_GE_2048-NEXT: ld1sh { z0.s }, p0/z, [x0] ; VBITS_GE_2048-NEXT: st1w { z0.s }, p0, [x8] ; VBITS_GE_2048-NEXT: ret - %a = load <64 x i16>, <64 x i16>* %ap + %a = load <64 x i16>, ptr %ap %val = sext <64 x i16> %a to <64 x i32> ret <64 x i32> %val } -define <32 x i64> @load_zext_v32i8i64(<32 x i8>* %ap) #0 { +define <32 x i64> @load_zext_v32i8i64(ptr %ap) #0 { ; VBITS_GE_1024-LABEL: load_zext_v32i8i64: ; VBITS_GE_1024: // %bb.0: ; VBITS_GE_1024-NEXT: ptrue p0.b, vl32 @@ -191,12 +191,12 @@ define <32 x i64> @load_zext_v32i8i64(<32 x i8>* %ap) #0 { ; VBITS_GE_2048-NEXT: ld1b { z0.d }, p0/z, [x0] ; VBITS_GE_2048-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_2048-NEXT: ret - %a = load <32 x i8>, <32 x i8>* %ap + %a = load <32 x i8>, ptr %ap %val = zext <32 x i8> %a to <32 x i64> ret <32 x i64> %val } -define <32 x i64> @load_sext_v32i8i64(<32 x i8>* %ap) #0 { +define <32 x i64> @load_sext_v32i8i64(ptr %ap) #0 { ; VBITS_GE_1024-LABEL: load_sext_v32i8i64: ; VBITS_GE_1024: // %bb.0: ; VBITS_GE_1024-NEXT: ptrue p0.b, vl32 @@ -220,12 +220,12 @@ define <32 x i64> @load_sext_v32i8i64(<32 x i8>* %ap) #0 { ; VBITS_GE_2048-NEXT: ld1sb { z0.d }, p0/z, [x0] ; VBITS_GE_2048-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_2048-NEXT: ret - %a = load <32 x i8>, <32 x i8>* %ap + %a = load <32 x i8>, ptr %ap %val = sext <32 x i8> %a to <32 x i64> ret <32 x i64> %val } -define <32 x i64> @load_zext_v32i16i64(<32 x i16>* %ap) #0 { +define <32 x i64> @load_zext_v32i16i64(ptr %ap) #0 { ; VBITS_GE_1024-LABEL: load_zext_v32i16i64: ; VBITS_GE_1024: // %bb.0: ; VBITS_GE_1024-NEXT: ptrue p0.h, vl32 @@ -247,12 +247,12 @@ define <32 x i64> @load_zext_v32i16i64(<32 x i16>* %ap) #0 { ; VBITS_GE_2048-NEXT: ld1h { z0.d }, p0/z, [x0] ; VBITS_GE_2048-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_2048-NEXT: ret - %a = load <32 x i16>, <32 x i16>* %ap + %a = load <32 x i16>, ptr %ap %val = zext <32 x i16> %a to <32 x i64> ret <32 x i64> %val } -define <32 x i64> @load_sext_v32i16i64(<32 x i16>* %ap) #0 { +define <32 x i64> @load_sext_v32i16i64(ptr %ap) #0 { ; VBITS_GE_1024-LABEL: load_sext_v32i16i64: ; VBITS_GE_1024: // %bb.0: ; VBITS_GE_1024-NEXT: ptrue p0.h, vl32 @@ -274,12 +274,12 @@ define <32 x i64> @load_sext_v32i16i64(<32 x i16>* %ap) #0 { ; VBITS_GE_2048-NEXT: ld1sh { z0.d }, p0/z, [x0] ; VBITS_GE_2048-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_2048-NEXT: ret - %a = load <32 x i16>, <32 x i16>* %ap + %a = load <32 x i16>, ptr %ap %val = sext <32 x i16> %a to <32 x i64> ret <32 x i64> %val } -define <32 x i64> @load_zext_v32i32i64(<32 x i32>* %ap) #0 { +define <32 x i64> @load_zext_v32i32i64(ptr %ap) #0 { ; VBITS_GE_1024-LABEL: load_zext_v32i32i64: ; VBITS_GE_1024: // %bb.0: ; VBITS_GE_1024-NEXT: ptrue p0.s, vl32 @@ -299,12 +299,12 @@ define <32 x i64> @load_zext_v32i32i64(<32 x i32>* %ap) #0 { ; VBITS_GE_2048-NEXT: ld1w { z0.d }, p0/z, [x0] ; VBITS_GE_2048-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_2048-NEXT: ret - %a = load <32 x i32>, <32 x i32>* %ap + %a = load <32 x i32>, ptr %ap %val = zext <32 x i32> %a to <32 x i64> ret <32 x i64> %val } -define <32 x i64> @load_sext_v32i32i64(<32 x i32>* %ap) #0 { +define <32 x i64> @load_sext_v32i32i64(ptr %ap) #0 { ; VBITS_GE_1024-LABEL: load_sext_v32i32i64: ; VBITS_GE_1024: // %bb.0: ; VBITS_GE_1024-NEXT: ptrue p0.s, vl32 @@ -324,7 +324,7 @@ define <32 x i64> @load_sext_v32i32i64(<32 x i32>* %ap) #0 { ; VBITS_GE_2048-NEXT: ld1sw { z0.d }, p0/z, [x0] ; VBITS_GE_2048-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_2048-NEXT: ret - %a = load <32 x i32>, <32 x i32>* %ap + %a = load <32 x i32>, ptr %ap %val = sext <32 x i32> %a to <32 x i64> ret <32 x i64> %val } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll index f1057fc..6f80ce1 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll @@ -28,7 +28,7 @@ define <8 x i8> @extract_subvector_v16i8(<16 x i8> %op) vscale_range(2,0) #0 { ret <8 x i8> %ret } -define void @extract_subvector_v32i8(<32 x i8>* %a, <16 x i8>* %b) vscale_range(2,0) #0 { +define void @extract_subvector_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: extract_subvector_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -36,13 +36,13 @@ define void @extract_subvector_v32i8(<32 x i8>* %a, <16 x i8>* %b) vscale_range( ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16 ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %op = load <32 x i8>, <32 x i8>* %a + %op = load <32 x i8>, ptr %a %ret = call <16 x i8> @llvm.vector.extract.v16i8.v32i8(<32 x i8> %op, i64 16) - store <16 x i8> %ret, <16 x i8>* %b + store <16 x i8> %ret, ptr %b ret void } -define void @extract_subvector_v64i8(<64 x i8>* %a, <32 x i8>* %b) #0 { +define void @extract_subvector_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: extract_subvector_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -59,13 +59,13 @@ define void @extract_subvector_v64i8(<64 x i8>* %a, <32 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: ext z0.b, z0.b, z0.b, #32 ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op = load <64 x i8>, <64 x i8>* %a + %op = load <64 x i8>, ptr %a %ret = call <32 x i8> @llvm.vector.extract.v32i8.v64i8(<64 x i8> %op, i64 32) - store <32 x i8> %ret, <32 x i8>* %b + store <32 x i8> %ret, ptr %b ret void } -define void @extract_subvector_v128i8(<128 x i8>* %a, <64 x i8>* %b) vscale_range(8,0) #0 { +define void @extract_subvector_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: extract_subvector_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -74,13 +74,13 @@ define void @extract_subvector_v128i8(<128 x i8>* %a, <64 x i8>* %b) vscale_rang ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64 ; CHECK-NEXT: st1b { z0.b }, p0, [x1] ; CHECK-NEXT: ret - %op = load <128 x i8>, <128 x i8>* %a + %op = load <128 x i8>, ptr %a %ret = call <64 x i8> @llvm.vector.extract.v64i8.v128i8(<128 x i8> %op, i64 64) - store <64 x i8> %ret, <64 x i8>* %b + store <64 x i8> %ret, ptr %b ret void } -define void @extract_subvector_v256i8(<256 x i8>* %a, <128 x i8>* %b) vscale_range(16,0) #0 { +define void @extract_subvector_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: extract_subvector_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -89,9 +89,9 @@ define void @extract_subvector_v256i8(<256 x i8>* %a, <128 x i8>* %b) vscale_ran ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128 ; CHECK-NEXT: st1b { z0.b }, p0, [x1] ; CHECK-NEXT: ret - %op = load <256 x i8>, <256 x i8>* %a + %op = load <256 x i8>, ptr %a %ret = call <128 x i8> @llvm.vector.extract.v128i8.v256i8(<256 x i8> %op, i64 128) - store <128 x i8> %ret, <128 x i8>* %b + store <128 x i8> %ret, ptr %b ret void } @@ -120,7 +120,7 @@ define <4 x i16> @extract_subvector_v8i16(<8 x i16> %op) vscale_range(2,0) #0 { ret <4 x i16> %ret } -define void @extract_subvector_v16i16(<16 x i16>* %a, <8 x i16>* %b) vscale_range(2,0) #0 { +define void @extract_subvector_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: extract_subvector_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -128,13 +128,13 @@ define void @extract_subvector_v16i16(<16 x i16>* %a, <8 x i16>* %b) vscale_rang ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16 ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %op = load <16 x i16>, <16 x i16>* %a + %op = load <16 x i16>, ptr %a %ret = call <8 x i16> @llvm.vector.extract.v8i16.v16i16(<16 x i16> %op, i64 8) - store <8 x i16> %ret, <8 x i16>* %b + store <8 x i16> %ret, ptr %b ret void } -define void @extract_subvector_v32i16(<32 x i16>* %a, <16 x i16>* %b) #0 { +define void @extract_subvector_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: extract_subvector_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -151,13 +151,13 @@ define void @extract_subvector_v32i16(<32 x i16>* %a, <16 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: ext z0.b, z0.b, z0.b, #32 ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op = load <32 x i16>, <32 x i16>* %a + %op = load <32 x i16>, ptr %a %ret = call <16 x i16> @llvm.vector.extract.v16i16.v32i16(<32 x i16> %op, i64 16) - store <16 x i16> %ret, <16 x i16>* %b + store <16 x i16> %ret, ptr %b ret void } -define void @extract_subvector_v64i16(<64 x i16>* %a, <32 x i16>* %b) vscale_range(8,0) #0 { +define void @extract_subvector_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: extract_subvector_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -166,13 +166,13 @@ define void @extract_subvector_v64i16(<64 x i16>* %a, <32 x i16>* %b) vscale_ran ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64 ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op = load <64 x i16>, <64 x i16>* %a + %op = load <64 x i16>, ptr %a %ret = call <32 x i16> @llvm.vector.extract.v32i16.v64i16(<64 x i16> %op, i64 32) - store <32 x i16> %ret, <32 x i16>* %b + store <32 x i16> %ret, ptr %b ret void } -define void @extract_subvector_v128i16(<128 x i16>* %a, <64 x i16>* %b) vscale_range(16,0) #0 { +define void @extract_subvector_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: extract_subvector_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -181,9 +181,9 @@ define void @extract_subvector_v128i16(<128 x i16>* %a, <64 x i16>* %b) vscale_r ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128 ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op = load <128 x i16>, <128 x i16>* %a + %op = load <128 x i16>, ptr %a %ret = call <64 x i16> @llvm.vector.extract.v64i16.v128i16(<128 x i16> %op, i64 64) - store <64 x i16> %ret, <64 x i16>* %b + store <64 x i16> %ret, ptr %b ret void } @@ -211,7 +211,7 @@ define <2 x i32> @extract_subvector_v4i32(<4 x i32> %op) vscale_range(2,0) #0 { ret <2 x i32> %ret } -define void @extract_subvector_v8i32(<8 x i32>* %a, <4 x i32>* %b) vscale_range(2,0) #0 { +define void @extract_subvector_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: extract_subvector_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -219,13 +219,13 @@ define void @extract_subvector_v8i32(<8 x i32>* %a, <4 x i32>* %b) vscale_range( ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16 ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %op = load <8 x i32>, <8 x i32>* %a + %op = load <8 x i32>, ptr %a %ret = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %op, i64 4) - store <4 x i32> %ret, <4 x i32>* %b + store <4 x i32> %ret, ptr %b ret void } -define void @extract_subvector_v16i32(<16 x i32>* %a, <8 x i32>* %b) #0 { +define void @extract_subvector_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: extract_subvector_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -242,13 +242,13 @@ define void @extract_subvector_v16i32(<16 x i32>* %a, <8 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: ext z0.b, z0.b, z0.b, #32 ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op = load <16 x i32>, <16 x i32>* %a + %op = load <16 x i32>, ptr %a %ret = call <8 x i32> @llvm.vector.extract.v8i32.v16i32(<16 x i32> %op, i64 8) - store <8 x i32> %ret, <8 x i32>* %b + store <8 x i32> %ret, ptr %b ret void } -define void @extract_subvector_v32i32(<32 x i32>* %a, <16 x i32>* %b) vscale_range(8,0) #0 { +define void @extract_subvector_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: extract_subvector_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -257,13 +257,13 @@ define void @extract_subvector_v32i32(<32 x i32>* %a, <16 x i32>* %b) vscale_ran ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64 ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op = load <32 x i32>, <32 x i32>* %a + %op = load <32 x i32>, ptr %a %ret = call <16 x i32> @llvm.vector.extract.v16i32.v32i32(<32 x i32> %op, i64 16) - store <16 x i32> %ret, <16 x i32>* %b + store <16 x i32> %ret, ptr %b ret void } -define void @extract_subvector_v64i32(<64 x i32>* %a, <32 x i32>* %b) vscale_range(16,0) #0 { +define void @extract_subvector_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: extract_subvector_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -272,9 +272,9 @@ define void @extract_subvector_v64i32(<64 x i32>* %a, <32 x i32>* %b) vscale_ran ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128 ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op = load <64 x i32>, <64 x i32>* %a + %op = load <64 x i32>, ptr %a %ret = call <32 x i32> @llvm.vector.extract.v32i32.v64i32(<64 x i32> %op, i64 32) - store <32 x i32> %ret, <32 x i32>* %b + store <32 x i32> %ret, ptr %b ret void } @@ -291,7 +291,7 @@ define <1 x i64> @extract_subvector_v2i64(<2 x i64> %op) vscale_range(2,0) #0 { ret <1 x i64> %ret } -define void @extract_subvector_v4i64(<4 x i64>* %a, <2 x i64>* %b) vscale_range(2,0) #0 { +define void @extract_subvector_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: extract_subvector_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -299,13 +299,13 @@ define void @extract_subvector_v4i64(<4 x i64>* %a, <2 x i64>* %b) vscale_range( ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16 ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %op = load <4 x i64>, <4 x i64>* %a + %op = load <4 x i64>, ptr %a %ret = call <2 x i64> @llvm.vector.extract.v2i64.v4i64(<4 x i64> %op, i64 2) - store <2 x i64> %ret, <2 x i64>* %b + store <2 x i64> %ret, ptr %b ret void } -define void @extract_subvector_v8i64(<8 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @extract_subvector_v8i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: extract_subvector_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: mov x8, #4 @@ -313,13 +313,13 @@ define void @extract_subvector_v8i64(<8 x i64>* %a, <4 x i64>* %b) vscale_range( ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3] ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op = load <8 x i64>, <8 x i64>* %a + %op = load <8 x i64>, ptr %a %ret = call <4 x i64> @llvm.vector.extract.v4i64.v8i64(<8 x i64> %op, i64 4) - store <4 x i64> %ret, <4 x i64>* %b + store <4 x i64> %ret, ptr %b ret void } -define void @extract_subvector_v16i64(<16 x i64>* %a, <8 x i64>* %b) #0 { +define void @extract_subvector_v16i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: extract_subvector_v16i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -331,13 +331,13 @@ define void @extract_subvector_v16i64(<16 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x1, x8, lsl #3] ; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_256-NEXT: ret - %op = load <16 x i64>, <16 x i64>* %a + %op = load <16 x i64>, ptr %a %ret = call <8 x i64> @llvm.vector.extract.v8i64.v16i64(<16 x i64> %op, i64 8) - store <8 x i64> %ret, <8 x i64>* %b + store <8 x i64> %ret, ptr %b ret void } -define void @extract_subvector_v32i64(<32 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @extract_subvector_v32i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: extract_subvector_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: mov x8, #16 @@ -345,9 +345,9 @@ define void @extract_subvector_v32i64(<32 x i64>* %a, <16 x i64>* %b) vscale_ran ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3] ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op = load <32 x i64>, <32 x i64>* %a + %op = load <32 x i64>, ptr %a %ret = call <16 x i64> @llvm.vector.extract.v16i64.v32i64(<32 x i64> %op, i64 16) - store <16 x i64> %ret, <16 x i64>* %b + store <16 x i64> %ret, ptr %b ret void } @@ -375,7 +375,7 @@ define <4 x half> @extract_subvector_v8f16(<8 x half> %op) vscale_range(2,0) #0 ret <4 x half> %ret } -define void @extract_subvector_v16f16(<16 x half>* %a, <8 x half>* %b) vscale_range(2,0) #0 { +define void @extract_subvector_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: extract_subvector_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -383,13 +383,13 @@ define void @extract_subvector_v16f16(<16 x half>* %a, <8 x half>* %b) vscale_ra ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16 ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %op = load <16 x half>, <16 x half>* %a + %op = load <16 x half>, ptr %a %ret = call <8 x half> @llvm.vector.extract.v8f16.v16f16(<16 x half> %op, i64 8) - store <8 x half> %ret, <8 x half>* %b + store <8 x half> %ret, ptr %b ret void } -define void @extract_subvector_v32f16(<32 x half>* %a, <16 x half>* %b) #0 { +define void @extract_subvector_v32f16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: extract_subvector_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -406,13 +406,13 @@ define void @extract_subvector_v32f16(<32 x half>* %a, <16 x half>* %b) #0 { ; VBITS_GE_512-NEXT: ext z0.b, z0.b, z0.b, #32 ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op = load <32 x half>, <32 x half>* %a + %op = load <32 x half>, ptr %a %ret = call <16 x half> @llvm.vector.extract.v16f16.v32f16(<32 x half> %op, i64 16) - store <16 x half> %ret, <16 x half>* %b + store <16 x half> %ret, ptr %b ret void } -define void @extract_subvector_v64f16(<64 x half>* %a, <32 x half>* %b) vscale_range(8,0) #0 { +define void @extract_subvector_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: extract_subvector_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -421,13 +421,13 @@ define void @extract_subvector_v64f16(<64 x half>* %a, <32 x half>* %b) vscale_r ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64 ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op = load <64 x half>, <64 x half>* %a + %op = load <64 x half>, ptr %a %ret = call <32 x half> @llvm.vector.extract.v32f16.v64f16(<64 x half> %op, i64 32) - store <32 x half> %ret, <32 x half>* %b + store <32 x half> %ret, ptr %b ret void } -define void @extract_subvector_v128f16(<128 x half>* %a, <64 x half>* %b) vscale_range(16,0) #0 { +define void @extract_subvector_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: extract_subvector_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -436,9 +436,9 @@ define void @extract_subvector_v128f16(<128 x half>* %a, <64 x half>* %b) vscale ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128 ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op = load <128 x half>, <128 x half>* %a + %op = load <128 x half>, ptr %a %ret = call <64 x half> @llvm.vector.extract.v64f16.v128f16(<128 x half> %op, i64 64) - store <64 x half> %ret, <64 x half>* %b + store <64 x half> %ret, ptr %b ret void } @@ -466,7 +466,7 @@ define <2 x float> @extract_subvector_v4f32(<4 x float> %op) vscale_range(2,0) # ret <2 x float> %ret } -define void @extract_subvector_v8f32(<8 x float>* %a, <4 x float>* %b) vscale_range(2,0) #0 { +define void @extract_subvector_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: extract_subvector_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -474,13 +474,13 @@ define void @extract_subvector_v8f32(<8 x float>* %a, <4 x float>* %b) vscale_ra ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16 ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %op = load <8 x float>, <8 x float>* %a + %op = load <8 x float>, ptr %a %ret = call <4 x float> @llvm.vector.extract.v4f32.v8f32(<8 x float> %op, i64 4) - store <4 x float> %ret, <4 x float>* %b + store <4 x float> %ret, ptr %b ret void } -define void @extract_subvector_v16f32(<16 x float>* %a, <8 x float>* %b) #0 { +define void @extract_subvector_v16f32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: extract_subvector_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -497,13 +497,13 @@ define void @extract_subvector_v16f32(<16 x float>* %a, <8 x float>* %b) #0 { ; VBITS_GE_512-NEXT: ext z0.b, z0.b, z0.b, #32 ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op = load <16 x float>, <16 x float>* %a + %op = load <16 x float>, ptr %a %ret = call <8 x float> @llvm.vector.extract.v8f32.v16f32(<16 x float> %op, i64 8) - store <8 x float> %ret, <8 x float>* %b + store <8 x float> %ret, ptr %b ret void } -define void @extract_subvector_v32f32(<32 x float>* %a, <16 x float>* %b) vscale_range(8,0) #0 { +define void @extract_subvector_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: extract_subvector_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -512,13 +512,13 @@ define void @extract_subvector_v32f32(<32 x float>* %a, <16 x float>* %b) vscale ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64 ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op = load <32 x float>, <32 x float>* %a + %op = load <32 x float>, ptr %a %ret = call <16 x float> @llvm.vector.extract.v16f32.v32f32(<32 x float> %op, i64 16) - store <16 x float> %ret, <16 x float>* %b + store <16 x float> %ret, ptr %b ret void } -define void @extract_subvector_v64f32(<64 x float>* %a, <32 x float>* %b) vscale_range(16,0) #0 { +define void @extract_subvector_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: extract_subvector_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -527,9 +527,9 @@ define void @extract_subvector_v64f32(<64 x float>* %a, <32 x float>* %b) vscale ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128 ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op = load <64 x float>, <64 x float>* %a + %op = load <64 x float>, ptr %a %ret = call <32 x float> @llvm.vector.extract.v32f32.v64f32(<64 x float> %op, i64 32) - store <32 x float> %ret, <32 x float>* %b + store <32 x float> %ret, ptr %b ret void } @@ -546,7 +546,7 @@ define <1 x double> @extract_subvector_v2f64(<2 x double> %op) vscale_range(2,0) ret <1 x double> %ret } -define void @extract_subvector_v4f64(<4 x double>* %a, <2 x double>* %b) vscale_range(2,0) #0 { +define void @extract_subvector_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: extract_subvector_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -554,13 +554,13 @@ define void @extract_subvector_v4f64(<4 x double>* %a, <2 x double>* %b) vscale_ ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16 ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %op = load <4 x double>, <4 x double>* %a + %op = load <4 x double>, ptr %a %ret = call <2 x double> @llvm.vector.extract.v2f64.v4f64(<4 x double> %op, i64 2) - store <2 x double> %ret, <2 x double>* %b + store <2 x double> %ret, ptr %b ret void } -define void @extract_subvector_v8f64(<8 x double>* %a, <4 x double>* %b) #0 { +define void @extract_subvector_v8f64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: extract_subvector_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -577,13 +577,13 @@ define void @extract_subvector_v8f64(<8 x double>* %a, <4 x double>* %b) #0 { ; VBITS_GE_512-NEXT: ext z0.b, z0.b, z0.b, #32 ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op = load <8 x double>, <8 x double>* %a + %op = load <8 x double>, ptr %a %ret = call <4 x double> @llvm.vector.extract.v4f64.v8f64(<8 x double> %op, i64 4) - store <4 x double> %ret, <4 x double>* %b + store <4 x double> %ret, ptr %b ret void } -define void @extract_subvector_v16f64(<16 x double>* %a, <8 x double>* %b) vscale_range(8,0) #0 { +define void @extract_subvector_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: extract_subvector_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -592,13 +592,13 @@ define void @extract_subvector_v16f64(<16 x double>* %a, <8 x double>* %b) vscal ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64 ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op = load <16 x double>, <16 x double>* %a + %op = load <16 x double>, ptr %a %ret = call <8 x double> @llvm.vector.extract.v8f64.v16f64(<16 x double> %op, i64 8) - store <8 x double> %ret, <8 x double>* %b + store <8 x double> %ret, ptr %b ret void } -define void @extract_subvector_v32f64(<32 x double>* %a, <16 x double>* %b) vscale_range(16,0) #0 { +define void @extract_subvector_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: extract_subvector_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -607,9 +607,9 @@ define void @extract_subvector_v32f64(<32 x double>* %a, <16 x double>* %b) vsca ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128 ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op = load <32 x double>, <32 x double>* %a + %op = load <32 x double>, ptr %a %ret = call <16 x double> @llvm.vector.extract.v16f64.v32f64(<32 x double> %op, i64 16) - store <16 x double> %ret, <16 x double>* %b + store <16 x double> %ret, ptr %b ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll index d8de704..b8cac79 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll @@ -30,7 +30,7 @@ define half @extractelement_v8f16(<8 x half> %op1) vscale_range(2,0) #0 { ret half %r } -define half @extractelement_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { +define half @extractelement_v16f16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: extractelement_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -38,12 +38,12 @@ define half @extractelement_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: mov z0.h, z0.h[15] ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a + %op1 = load <16 x half>, ptr %a %r = extractelement <16 x half> %op1, i64 15 ret half %r } -define half @extractelement_v32f16(<32 x half>* %a) #0 { +define half @extractelement_v32f16(ptr %a) #0 { ; VBITS_GE_256-LABEL: extractelement_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -60,12 +60,12 @@ define half @extractelement_v32f16(<32 x half>* %a) #0 { ; VBITS_GE_512-NEXT: mov z0.h, z0.h[31] ; VBITS_GE_512-NEXT: // kill: def $h0 killed $h0 killed $z0 ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a + %op1 = load <32 x half>, ptr %a %r = extractelement <32 x half> %op1, i64 31 ret half %r } -define half @extractelement_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { +define half @extractelement_v64f16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: extractelement_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -74,12 +74,12 @@ define half @extractelement_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: whilels p0.h, xzr, x8 ; CHECK-NEXT: lastb h0, p0, z0.h ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a + %op1 = load <64 x half>, ptr %a %r = extractelement <64 x half> %op1, i64 63 ret half %r } -define half @extractelement_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { +define half @extractelement_v128f16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: extractelement_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -88,7 +88,7 @@ define half @extractelement_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: whilels p0.h, xzr, x8 ; CHECK-NEXT: lastb h0, p0, z0.h ; CHECK-NEXT: ret - %op1 = load <128 x half>, <128 x half>* %a + %op1 = load <128 x half>, ptr %a %r = extractelement <128 x half> %op1, i64 127 ret half %r } @@ -114,7 +114,7 @@ define float @extractelement_v4f32(<4 x float> %op1) vscale_range(2,0) #0 { ret float %r } -define float @extractelement_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { +define float @extractelement_v8f32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: extractelement_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -122,12 +122,12 @@ define float @extractelement_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: mov z0.s, z0.s[7] ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a + %op1 = load <8 x float>, ptr %a %r = extractelement <8 x float> %op1, i64 7 ret float %r } -define float @extractelement_v16f32(<16 x float>* %a) #0 { +define float @extractelement_v16f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: extractelement_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -144,12 +144,12 @@ define float @extractelement_v16f32(<16 x float>* %a) #0 { ; VBITS_GE_512-NEXT: mov z0.s, z0.s[15] ; VBITS_GE_512-NEXT: // kill: def $s0 killed $s0 killed $z0 ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a + %op1 = load <16 x float>, ptr %a %r = extractelement <16 x float> %op1, i64 15 ret float %r } -define float @extractelement_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { +define float @extractelement_v32f32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: extractelement_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -158,12 +158,12 @@ define float @extractelement_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: whilels p0.s, xzr, x8 ; CHECK-NEXT: lastb s0, p0, z0.s ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a + %op1 = load <32 x float>, ptr %a %r = extractelement <32 x float> %op1, i64 31 ret float %r } -define float @extractelement_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { +define float @extractelement_v64f32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: extractelement_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -172,7 +172,7 @@ define float @extractelement_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: whilels p0.s, xzr, x8 ; CHECK-NEXT: lastb s0, p0, z0.s ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a + %op1 = load <64 x float>, ptr %a %r = extractelement <64 x float> %op1, i64 63 ret float %r } @@ -196,7 +196,7 @@ define double @extractelement_v2f64(<2 x double> %op1) vscale_range(2,0) #0 { ret double %r } -define double @extractelement_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { +define double @extractelement_v4f64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: extractelement_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -204,12 +204,12 @@ define double @extractelement_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: mov z0.d, z0.d[3] ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a + %op1 = load <4 x double>, ptr %a %r = extractelement <4 x double> %op1, i64 3 ret double %r } -define double @extractelement_v8f64(<8 x double>* %a) #0 { +define double @extractelement_v8f64(ptr %a) #0 { ; VBITS_GE_256-LABEL: extractelement_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -226,12 +226,12 @@ define double @extractelement_v8f64(<8 x double>* %a) #0 { ; VBITS_GE_512-NEXT: mov z0.d, z0.d[7] ; VBITS_GE_512-NEXT: // kill: def $d0 killed $d0 killed $z0 ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a + %op1 = load <8 x double>, ptr %a %r = extractelement <8 x double> %op1, i64 7 ret double %r } -define double @extractelement_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { +define double @extractelement_v16f64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: extractelement_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -240,12 +240,12 @@ define double @extractelement_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: whilels p0.d, xzr, x8 ; CHECK-NEXT: lastb d0, p0, z0.d ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a + %op1 = load <16 x double>, ptr %a %r = extractelement <16 x double> %op1, i64 15 ret double %r } -define double @extractelement_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { +define double @extractelement_v32f64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: extractelement_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -254,7 +254,7 @@ define double @extractelement_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: whilels p0.d, xzr, x8 ; CHECK-NEXT: lastb d0, p0, z0.d ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a + %op1 = load <32 x double>, ptr %a %r = extractelement <32 x double> %op1, i64 31 ret double %r } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll index 1d588c9..8698f4a 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll @@ -29,7 +29,7 @@ define <8 x half> @fadd_v8f16(<8 x half> %op1, <8 x half> %op2) vscale_range(2,0 ret <8 x half> %res } -define void @fadd_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 { +define void @fadd_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fadd_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -38,14 +38,14 @@ define void @fadd_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %res = fadd <16 x half> %op1, %op2 - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @fadd_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { +define void @fadd_v32f16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fadd_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -68,14 +68,14 @@ define void @fadd_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { ; VBITS_GE_512-NEXT: fadd z0.h, p0/m, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a - %op2 = load <32 x half>, <32 x half>* %b + %op1 = load <32 x half>, ptr %a + %op2 = load <32 x half>, ptr %b %res = fadd <32 x half> %op1, %op2 - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @fadd_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) #0 { +define void @fadd_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fadd_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -84,14 +84,14 @@ define void @fadd_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) #0 ; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a - %op2 = load <64 x half>, <64 x half>* %b + %op1 = load <64 x half>, ptr %a + %op2 = load <64 x half>, ptr %b %res = fadd <64 x half> %op1, %op2 - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @fadd_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16,0) #0 { +define void @fadd_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fadd_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -100,10 +100,10 @@ define void @fadd_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16,0 ; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x half>, <128 x half>* %a - %op2 = load <128 x half>, <128 x half>* %b + %op1 = load <128 x half>, ptr %a + %op2 = load <128 x half>, ptr %b %res = fadd <128 x half> %op1, %op2 - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -127,7 +127,7 @@ define <4 x float> @fadd_v4f32(<4 x float> %op1, <4 x float> %op2) vscale_range( ret <4 x float> %res } -define void @fadd_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 { +define void @fadd_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fadd_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -136,14 +136,14 @@ define void @fadd_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a - %op2 = load <8 x float>, <8 x float>* %b + %op1 = load <8 x float>, ptr %a + %op2 = load <8 x float>, ptr %b %res = fadd <8 x float> %op1, %op2 - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @fadd_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { +define void @fadd_v16f32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fadd_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -166,14 +166,14 @@ define void @fadd_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { ; VBITS_GE_512-NEXT: fadd z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a - %op2 = load <16 x float>, <16 x float>* %b + %op1 = load <16 x float>, ptr %a + %op2 = load <16 x float>, ptr %b %res = fadd <16 x float> %op1, %op2 - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @fadd_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) #0 { +define void @fadd_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fadd_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -182,14 +182,14 @@ define void @fadd_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) # ; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a - %op2 = load <32 x float>, <32 x float>* %b + %op1 = load <32 x float>, ptr %a + %op2 = load <32 x float>, ptr %b %res = fadd <32 x float> %op1, %op2 - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @fadd_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0) #0 { +define void @fadd_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fadd_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -198,10 +198,10 @@ define void @fadd_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0) ; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a - %op2 = load <64 x float>, <64 x float>* %b + %op1 = load <64 x float>, ptr %a + %op2 = load <64 x float>, ptr %b %res = fadd <64 x float> %op1, %op2 - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -225,7 +225,7 @@ define <2 x double> @fadd_v2f64(<2 x double> %op1, <2 x double> %op2) vscale_ran ret <2 x double> %res } -define void @fadd_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @fadd_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fadd_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -234,14 +234,14 @@ define void @fadd_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a - %op2 = load <4 x double>, <4 x double>* %b + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b %res = fadd <4 x double> %op1, %op2 - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @fadd_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { +define void @fadd_v8f64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fadd_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -264,14 +264,14 @@ define void @fadd_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: fadd z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a - %op2 = load <8 x double>, <8 x double>* %b + %op1 = load <8 x double>, ptr %a + %op2 = load <8 x double>, ptr %b %res = fadd <8 x double> %op1, %op2 - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @fadd_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @fadd_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fadd_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -280,14 +280,14 @@ define void @fadd_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8,0) ; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a - %op2 = load <16 x double>, <16 x double>* %b + %op1 = load <16 x double>, ptr %a + %op2 = load <16 x double>, ptr %b %res = fadd <16 x double> %op1, %op2 - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @fadd_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @fadd_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fadd_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -296,10 +296,10 @@ define void @fadd_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16,0 ; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a - %op2 = load <32 x double>, <32 x double>* %b + %op1 = load <32 x double>, ptr %a + %op2 = load <32 x double>, ptr %b %res = fadd <32 x double> %op1, %op2 - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } @@ -327,7 +327,7 @@ define <8 x half> @fdiv_v8f16(<8 x half> %op1, <8 x half> %op2) vscale_range(2,0 ret <8 x half> %res } -define void @fdiv_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 { +define void @fdiv_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fdiv_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -336,14 +336,14 @@ define void @fdiv_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: fdiv z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %res = fdiv <16 x half> %op1, %op2 - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @fdiv_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { +define void @fdiv_v32f16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fdiv_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -366,14 +366,14 @@ define void @fdiv_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { ; VBITS_GE_512-NEXT: fdiv z0.h, p0/m, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a - %op2 = load <32 x half>, <32 x half>* %b + %op1 = load <32 x half>, ptr %a + %op2 = load <32 x half>, ptr %b %res = fdiv <32 x half> %op1, %op2 - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @fdiv_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) #0 { +define void @fdiv_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fdiv_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -382,14 +382,14 @@ define void @fdiv_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) #0 ; CHECK-NEXT: fdiv z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a - %op2 = load <64 x half>, <64 x half>* %b + %op1 = load <64 x half>, ptr %a + %op2 = load <64 x half>, ptr %b %res = fdiv <64 x half> %op1, %op2 - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @fdiv_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16,0) #0 { +define void @fdiv_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fdiv_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -398,10 +398,10 @@ define void @fdiv_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16,0) ; CHECK-NEXT: fdiv z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x half>, <128 x half>* %a - %op2 = load <128 x half>, <128 x half>* %b + %op1 = load <128 x half>, ptr %a + %op2 = load <128 x half>, ptr %b %res = fdiv <128 x half> %op1, %op2 - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -425,7 +425,7 @@ define <4 x float> @fdiv_v4f32(<4 x float> %op1, <4 x float> %op2) vscale_range( ret <4 x float> %res } -define void @fdiv_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 { +define void @fdiv_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fdiv_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -434,14 +434,14 @@ define void @fdiv_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: fdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a - %op2 = load <8 x float>, <8 x float>* %b + %op1 = load <8 x float>, ptr %a + %op2 = load <8 x float>, ptr %b %res = fdiv <8 x float> %op1, %op2 - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @fdiv_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { +define void @fdiv_v16f32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fdiv_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -464,14 +464,14 @@ define void @fdiv_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { ; VBITS_GE_512-NEXT: fdiv z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a - %op2 = load <16 x float>, <16 x float>* %b + %op1 = load <16 x float>, ptr %a + %op2 = load <16 x float>, ptr %b %res = fdiv <16 x float> %op1, %op2 - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @fdiv_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) #0 { +define void @fdiv_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fdiv_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -480,14 +480,14 @@ define void @fdiv_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) # ; CHECK-NEXT: fdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a - %op2 = load <32 x float>, <32 x float>* %b + %op1 = load <32 x float>, ptr %a + %op2 = load <32 x float>, ptr %b %res = fdiv <32 x float> %op1, %op2 - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @fdiv_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0) #0 { +define void @fdiv_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fdiv_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -496,10 +496,10 @@ define void @fdiv_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0) ; CHECK-NEXT: fdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a - %op2 = load <64 x float>, <64 x float>* %b + %op1 = load <64 x float>, ptr %a + %op2 = load <64 x float>, ptr %b %res = fdiv <64 x float> %op1, %op2 - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -523,7 +523,7 @@ define <2 x double> @fdiv_v2f64(<2 x double> %op1, <2 x double> %op2) vscale_ran ret <2 x double> %res } -define void @fdiv_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @fdiv_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fdiv_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -532,14 +532,14 @@ define void @fdiv_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: fdiv z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a - %op2 = load <4 x double>, <4 x double>* %b + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b %res = fdiv <4 x double> %op1, %op2 - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @fdiv_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { +define void @fdiv_v8f64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fdiv_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -562,14 +562,14 @@ define void @fdiv_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: fdiv z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a - %op2 = load <8 x double>, <8 x double>* %b + %op1 = load <8 x double>, ptr %a + %op2 = load <8 x double>, ptr %b %res = fdiv <8 x double> %op1, %op2 - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @fdiv_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @fdiv_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fdiv_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -578,14 +578,14 @@ define void @fdiv_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8,0) ; CHECK-NEXT: fdiv z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a - %op2 = load <16 x double>, <16 x double>* %b + %op1 = load <16 x double>, ptr %a + %op2 = load <16 x double>, ptr %b %res = fdiv <16 x double> %op1, %op2 - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @fdiv_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @fdiv_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fdiv_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -594,10 +594,10 @@ define void @fdiv_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16,0 ; CHECK-NEXT: fdiv z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a - %op2 = load <32 x double>, <32 x double>* %b + %op1 = load <32 x double>, ptr %a + %op2 = load <32 x double>, ptr %b %res = fdiv <32 x double> %op1, %op2 - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } @@ -627,7 +627,7 @@ define <8 x half> @fma_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x half> %op3) ret <8 x half> %res } -define void @fma_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x half>* %c) vscale_range(2,0) #0 { +define void @fma_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fma_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -637,15 +637,15 @@ define void @fma_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x half>* %c) vscal ; CHECK-NEXT: fmad z0.h, p0/m, z1.h, z2.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b - %op3 = load <16 x half>, <16 x half>* %c + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %op3 = load <16 x half>, ptr %c %res = call <16 x half> @llvm.fma.v16f16(<16 x half> %op1, <16 x half> %op2, <16 x half> %op3) - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @fma_v32f16(<32 x half>* %a, <32 x half>* %b, <32 x half>* %c) #0 { +define void @fma_v32f16(ptr %a, ptr %b, ptr %c) #0 { ; VBITS_GE_256-LABEL: fma_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -671,15 +671,15 @@ define void @fma_v32f16(<32 x half>* %a, <32 x half>* %b, <32 x half>* %c) #0 { ; VBITS_GE_512-NEXT: fmad z0.h, p0/m, z1.h, z2.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a - %op2 = load <32 x half>, <32 x half>* %b - %op3 = load <32 x half>, <32 x half>* %c + %op1 = load <32 x half>, ptr %a + %op2 = load <32 x half>, ptr %b + %op3 = load <32 x half>, ptr %c %res = call <32 x half> @llvm.fma.v32f16(<32 x half> %op1, <32 x half> %op2, <32 x half> %op3) - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @fma_v64f16(<64 x half>* %a, <64 x half>* %b, <64 x half>* %c) vscale_range(8,0) #0 { +define void @fma_v64f16(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 { ; CHECK-LABEL: fma_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -689,15 +689,15 @@ define void @fma_v64f16(<64 x half>* %a, <64 x half>* %b, <64 x half>* %c) vscal ; CHECK-NEXT: fmad z0.h, p0/m, z1.h, z2.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a - %op2 = load <64 x half>, <64 x half>* %b - %op3 = load <64 x half>, <64 x half>* %c + %op1 = load <64 x half>, ptr %a + %op2 = load <64 x half>, ptr %b + %op3 = load <64 x half>, ptr %c %res = call <64 x half> @llvm.fma.v64f16(<64 x half> %op1, <64 x half> %op2, <64 x half> %op3) - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @fma_v128f16(<128 x half>* %a, <128 x half>* %b, <128 x half>* %c) vscale_range(16,0) #0 { +define void @fma_v128f16(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 { ; CHECK-LABEL: fma_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -707,11 +707,11 @@ define void @fma_v128f16(<128 x half>* %a, <128 x half>* %b, <128 x half>* %c) v ; CHECK-NEXT: fmad z0.h, p0/m, z1.h, z2.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x half>, <128 x half>* %a - %op2 = load <128 x half>, <128 x half>* %b - %op3 = load <128 x half>, <128 x half>* %c + %op1 = load <128 x half>, ptr %a + %op2 = load <128 x half>, ptr %b + %op3 = load <128 x half>, ptr %c %res = call <128 x half> @llvm.fma.v128f16(<128 x half> %op1, <128 x half> %op2, <128 x half> %op3) - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -737,7 +737,7 @@ define <4 x float> @fma_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x float> %o ret <4 x float> %res } -define void @fma_v8f32(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) vscale_range(2,0) #0 { +define void @fma_v8f32(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fma_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -747,15 +747,15 @@ define void @fma_v8f32(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) vscale ; CHECK-NEXT: fmad z0.s, p0/m, z1.s, z2.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a - %op2 = load <8 x float>, <8 x float>* %b - %op3 = load <8 x float>, <8 x float>* %c + %op1 = load <8 x float>, ptr %a + %op2 = load <8 x float>, ptr %b + %op3 = load <8 x float>, ptr %c %res = call <8 x float> @llvm.fma.v8f32(<8 x float> %op1, <8 x float> %op2, <8 x float> %op3) - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @fma_v16f32(<16 x float>* %a, <16 x float>* %b, <16 x float>* %c) #0 { +define void @fma_v16f32(ptr %a, ptr %b, ptr %c) #0 { ; VBITS_GE_256-LABEL: fma_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -781,15 +781,15 @@ define void @fma_v16f32(<16 x float>* %a, <16 x float>* %b, <16 x float>* %c) #0 ; VBITS_GE_512-NEXT: fmad z0.s, p0/m, z1.s, z2.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a - %op2 = load <16 x float>, <16 x float>* %b - %op3 = load <16 x float>, <16 x float>* %c + %op1 = load <16 x float>, ptr %a + %op2 = load <16 x float>, ptr %b + %op3 = load <16 x float>, ptr %c %res = call <16 x float> @llvm.fma.v16f32(<16 x float> %op1, <16 x float> %op2, <16 x float> %op3) - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @fma_v32f32(<32 x float>* %a, <32 x float>* %b, <32 x float>* %c) vscale_range(8,0) #0 { +define void @fma_v32f32(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 { ; CHECK-LABEL: fma_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -799,15 +799,15 @@ define void @fma_v32f32(<32 x float>* %a, <32 x float>* %b, <32 x float>* %c) vs ; CHECK-NEXT: fmad z0.s, p0/m, z1.s, z2.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a - %op2 = load <32 x float>, <32 x float>* %b - %op3 = load <32 x float>, <32 x float>* %c + %op1 = load <32 x float>, ptr %a + %op2 = load <32 x float>, ptr %b + %op3 = load <32 x float>, ptr %c %res = call <32 x float> @llvm.fma.v32f32(<32 x float> %op1, <32 x float> %op2, <32 x float> %op3) - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @fma_v64f32(<64 x float>* %a, <64 x float>* %b, <64 x float>* %c) vscale_range(16,0) #0 { +define void @fma_v64f32(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 { ; CHECK-LABEL: fma_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -817,11 +817,11 @@ define void @fma_v64f32(<64 x float>* %a, <64 x float>* %b, <64 x float>* %c) vs ; CHECK-NEXT: fmad z0.s, p0/m, z1.s, z2.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a - %op2 = load <64 x float>, <64 x float>* %b - %op3 = load <64 x float>, <64 x float>* %c + %op1 = load <64 x float>, ptr %a + %op2 = load <64 x float>, ptr %b + %op3 = load <64 x float>, ptr %c %res = call <64 x float> @llvm.fma.v64f32(<64 x float> %op1, <64 x float> %op2, <64 x float> %op3) - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -846,7 +846,7 @@ define <2 x double> @fma_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x double ret <2 x double> %res } -define void @fma_v4f64(<4 x double>* %a, <4 x double>* %b, <4 x double>* %c) vscale_range(2,0) #0 { +define void @fma_v4f64(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fma_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -856,15 +856,15 @@ define void @fma_v4f64(<4 x double>* %a, <4 x double>* %b, <4 x double>* %c) vsc ; CHECK-NEXT: fmad z0.d, p0/m, z1.d, z2.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a - %op2 = load <4 x double>, <4 x double>* %b - %op3 = load <4 x double>, <4 x double>* %c + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b + %op3 = load <4 x double>, ptr %c %res = call <4 x double> @llvm.fma.v4f64(<4 x double> %op1, <4 x double> %op2, <4 x double> %op3) - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @fma_v8f64(<8 x double>* %a, <8 x double>* %b, <8 x double>* %c) #0 { +define void @fma_v8f64(ptr %a, ptr %b, ptr %c) #0 { ; VBITS_GE_256-LABEL: fma_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -890,15 +890,15 @@ define void @fma_v8f64(<8 x double>* %a, <8 x double>* %b, <8 x double>* %c) #0 ; VBITS_GE_512-NEXT: fmad z0.d, p0/m, z1.d, z2.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a - %op2 = load <8 x double>, <8 x double>* %b - %op3 = load <8 x double>, <8 x double>* %c + %op1 = load <8 x double>, ptr %a + %op2 = load <8 x double>, ptr %b + %op3 = load <8 x double>, ptr %c %res = call <8 x double> @llvm.fma.v8f64(<8 x double> %op1, <8 x double> %op2, <8 x double> %op3) - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @fma_v16f64(<16 x double>* %a, <16 x double>* %b, <16 x double>* %c) vscale_range(8,0) #0 { +define void @fma_v16f64(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 { ; CHECK-LABEL: fma_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -908,15 +908,15 @@ define void @fma_v16f64(<16 x double>* %a, <16 x double>* %b, <16 x double>* %c) ; CHECK-NEXT: fmad z0.d, p0/m, z1.d, z2.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a - %op2 = load <16 x double>, <16 x double>* %b - %op3 = load <16 x double>, <16 x double>* %c + %op1 = load <16 x double>, ptr %a + %op2 = load <16 x double>, ptr %b + %op3 = load <16 x double>, ptr %c %res = call <16 x double> @llvm.fma.v16f64(<16 x double> %op1, <16 x double> %op2, <16 x double> %op3) - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @fma_v32f64(<32 x double>* %a, <32 x double>* %b, <32 x double>* %c) vscale_range(16,0) #0 { +define void @fma_v32f64(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 { ; CHECK-LABEL: fma_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -926,11 +926,11 @@ define void @fma_v32f64(<32 x double>* %a, <32 x double>* %b, <32 x double>* %c) ; CHECK-NEXT: fmad z0.d, p0/m, z1.d, z2.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a - %op2 = load <32 x double>, <32 x double>* %b - %op3 = load <32 x double>, <32 x double>* %c + %op1 = load <32 x double>, ptr %a + %op2 = load <32 x double>, ptr %b + %op3 = load <32 x double>, ptr %c %res = call <32 x double> @llvm.fma.v32f64(<32 x double> %op1, <32 x double> %op2, <32 x double> %op3) - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } @@ -958,7 +958,7 @@ define <8 x half> @fmul_v8f16(<8 x half> %op1, <8 x half> %op2) vscale_range(2,0 ret <8 x half> %res } -define void @fmul_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 { +define void @fmul_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fmul_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -967,14 +967,14 @@ define void @fmul_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: fmul z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %res = fmul <16 x half> %op1, %op2 - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @fmul_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { +define void @fmul_v32f16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fmul_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -997,14 +997,14 @@ define void @fmul_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { ; VBITS_GE_512-NEXT: fmul z0.h, p0/m, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a - %op2 = load <32 x half>, <32 x half>* %b + %op1 = load <32 x half>, ptr %a + %op2 = load <32 x half>, ptr %b %res = fmul <32 x half> %op1, %op2 - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @fmul_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) #0 { +define void @fmul_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fmul_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -1013,14 +1013,14 @@ define void @fmul_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) #0 ; CHECK-NEXT: fmul z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a - %op2 = load <64 x half>, <64 x half>* %b + %op1 = load <64 x half>, ptr %a + %op2 = load <64 x half>, ptr %b %res = fmul <64 x half> %op1, %op2 - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @fmul_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16,0) #0 { +define void @fmul_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fmul_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1029,10 +1029,10 @@ define void @fmul_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16,0) ; CHECK-NEXT: fmul z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x half>, <128 x half>* %a - %op2 = load <128 x half>, <128 x half>* %b + %op1 = load <128 x half>, ptr %a + %op2 = load <128 x half>, ptr %b %res = fmul <128 x half> %op1, %op2 - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -1056,7 +1056,7 @@ define <4 x float> @fmul_v4f32(<4 x float> %op1, <4 x float> %op2) vscale_range( ret <4 x float> %res } -define void @fmul_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 { +define void @fmul_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fmul_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1065,14 +1065,14 @@ define void @fmul_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: fmul z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a - %op2 = load <8 x float>, <8 x float>* %b + %op1 = load <8 x float>, ptr %a + %op2 = load <8 x float>, ptr %b %res = fmul <8 x float> %op1, %op2 - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @fmul_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { +define void @fmul_v16f32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fmul_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1095,14 +1095,14 @@ define void @fmul_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { ; VBITS_GE_512-NEXT: fmul z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a - %op2 = load <16 x float>, <16 x float>* %b + %op1 = load <16 x float>, ptr %a + %op2 = load <16 x float>, ptr %b %res = fmul <16 x float> %op1, %op2 - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @fmul_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) #0 { +define void @fmul_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fmul_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1111,14 +1111,14 @@ define void @fmul_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) # ; CHECK-NEXT: fmul z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a - %op2 = load <32 x float>, <32 x float>* %b + %op1 = load <32 x float>, ptr %a + %op2 = load <32 x float>, ptr %b %res = fmul <32 x float> %op1, %op2 - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @fmul_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0) #0 { +define void @fmul_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fmul_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1127,10 +1127,10 @@ define void @fmul_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0) ; CHECK-NEXT: fmul z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a - %op2 = load <64 x float>, <64 x float>* %b + %op1 = load <64 x float>, ptr %a + %op2 = load <64 x float>, ptr %b %res = fmul <64 x float> %op1, %op2 - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -1154,7 +1154,7 @@ define <2 x double> @fmul_v2f64(<2 x double> %op1, <2 x double> %op2) vscale_ran ret <2 x double> %res } -define void @fmul_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @fmul_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fmul_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1163,14 +1163,14 @@ define void @fmul_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: fmul z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a - %op2 = load <4 x double>, <4 x double>* %b + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b %res = fmul <4 x double> %op1, %op2 - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @fmul_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { +define void @fmul_v8f64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fmul_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1193,14 +1193,14 @@ define void @fmul_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: fmul z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a - %op2 = load <8 x double>, <8 x double>* %b + %op1 = load <8 x double>, ptr %a + %op2 = load <8 x double>, ptr %b %res = fmul <8 x double> %op1, %op2 - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @fmul_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @fmul_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fmul_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1209,14 +1209,14 @@ define void @fmul_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8,0) ; CHECK-NEXT: fmul z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a - %op2 = load <16 x double>, <16 x double>* %b + %op1 = load <16 x double>, ptr %a + %op2 = load <16 x double>, ptr %b %res = fmul <16 x double> %op1, %op2 - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @fmul_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @fmul_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fmul_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1225,10 +1225,10 @@ define void @fmul_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16,0 ; CHECK-NEXT: fmul z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a - %op2 = load <32 x double>, <32 x double>* %b + %op1 = load <32 x double>, ptr %a + %op2 = load <32 x double>, ptr %b %res = fmul <32 x double> %op1, %op2 - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } @@ -1256,7 +1256,7 @@ define <8 x half> @fneg_v8f16(<8 x half> %op) vscale_range(2,0) #0 { ret <8 x half> %res } -define void @fneg_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 { +define void @fneg_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fneg_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -1264,13 +1264,13 @@ define void @fneg_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: fneg z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x half>, <16 x half>* %a + %op = load <16 x half>, ptr %a %res = fneg <16 x half> %op - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @fneg_v32f16(<32 x half>* %a) #0 { +define void @fneg_v32f16(ptr %a) #0 { ; VBITS_GE_256-LABEL: fneg_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -1290,13 +1290,13 @@ define void @fneg_v32f16(<32 x half>* %a) #0 { ; VBITS_GE_512-NEXT: fneg z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <32 x half>, <32 x half>* %a + %op = load <32 x half>, ptr %a %res = fneg <32 x half> %op - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @fneg_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { +define void @fneg_v64f16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: fneg_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -1304,13 +1304,13 @@ define void @fneg_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fneg z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x half>, <64 x half>* %a + %op = load <64 x half>, ptr %a %res = fneg <64 x half> %op - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @fneg_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { +define void @fneg_v128f16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: fneg_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1318,9 +1318,9 @@ define void @fneg_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: fneg z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x half>, <128 x half>* %a + %op = load <128 x half>, ptr %a %res = fneg <128 x half> %op - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -1344,7 +1344,7 @@ define <4 x float> @fneg_v4f32(<4 x float> %op) vscale_range(2,0) #0 { ret <4 x float> %res } -define void @fneg_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { +define void @fneg_v8f32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fneg_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1352,13 +1352,13 @@ define void @fneg_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: fneg z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <8 x float>, <8 x float>* %a + %op = load <8 x float>, ptr %a %res = fneg <8 x float> %op - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @fneg_v16f32(<16 x float>* %a) #0 { +define void @fneg_v16f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: fneg_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1378,13 +1378,13 @@ define void @fneg_v16f32(<16 x float>* %a) #0 { ; VBITS_GE_512-NEXT: fneg z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <16 x float>, <16 x float>* %a + %op = load <16 x float>, ptr %a %res = fneg <16 x float> %op - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @fneg_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { +define void @fneg_v32f32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: fneg_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1392,13 +1392,13 @@ define void @fneg_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fneg z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x float>, <32 x float>* %a + %op = load <32 x float>, ptr %a %res = fneg <32 x float> %op - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @fneg_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { +define void @fneg_v64f32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: fneg_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1406,9 +1406,9 @@ define void @fneg_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: fneg z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x float>, <64 x float>* %a + %op = load <64 x float>, ptr %a %res = fneg <64 x float> %op - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -1432,7 +1432,7 @@ define <2 x double> @fneg_v2f64(<2 x double> %op) vscale_range(2,0) #0 { ret <2 x double> %res } -define void @fneg_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { +define void @fneg_v4f64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fneg_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1440,13 +1440,13 @@ define void @fneg_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: fneg z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <4 x double>, <4 x double>* %a + %op = load <4 x double>, ptr %a %res = fneg <4 x double> %op - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @fneg_v8f64(<8 x double>* %a) #0 { +define void @fneg_v8f64(ptr %a) #0 { ; VBITS_GE_256-LABEL: fneg_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1466,13 +1466,13 @@ define void @fneg_v8f64(<8 x double>* %a) #0 { ; VBITS_GE_512-NEXT: fneg z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <8 x double>, <8 x double>* %a + %op = load <8 x double>, ptr %a %res = fneg <8 x double> %op - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @fneg_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { +define void @fneg_v16f64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: fneg_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1480,13 +1480,13 @@ define void @fneg_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fneg z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x double>, <16 x double>* %a + %op = load <16 x double>, ptr %a %res = fneg <16 x double> %op - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @fneg_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { +define void @fneg_v32f64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: fneg_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1494,9 +1494,9 @@ define void @fneg_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: fneg z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x double>, <32 x double>* %a + %op = load <32 x double>, ptr %a %res = fneg <32 x double> %op - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } @@ -1524,7 +1524,7 @@ define <8 x half> @fsqrt_v8f16(<8 x half> %op) vscale_range(2,0) #0 { ret <8 x half> %res } -define void @fsqrt_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 { +define void @fsqrt_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fsqrt_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -1532,13 +1532,13 @@ define void @fsqrt_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: fsqrt z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x half>, <16 x half>* %a + %op = load <16 x half>, ptr %a %res = call <16 x half> @llvm.sqrt.v16f16(<16 x half> %op) - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @fsqrt_v32f16(<32 x half>* %a) #0 { +define void @fsqrt_v32f16(ptr %a) #0 { ; VBITS_GE_256-LABEL: fsqrt_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -1558,13 +1558,13 @@ define void @fsqrt_v32f16(<32 x half>* %a) #0 { ; VBITS_GE_512-NEXT: fsqrt z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <32 x half>, <32 x half>* %a + %op = load <32 x half>, ptr %a %res = call <32 x half> @llvm.sqrt.v32f16(<32 x half> %op) - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @fsqrt_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { +define void @fsqrt_v64f16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: fsqrt_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -1572,13 +1572,13 @@ define void @fsqrt_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fsqrt z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x half>, <64 x half>* %a + %op = load <64 x half>, ptr %a %res = call <64 x half> @llvm.sqrt.v64f16(<64 x half> %op) - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @fsqrt_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { +define void @fsqrt_v128f16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: fsqrt_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1586,9 +1586,9 @@ define void @fsqrt_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: fsqrt z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x half>, <128 x half>* %a + %op = load <128 x half>, ptr %a %res = call <128 x half> @llvm.sqrt.v128f16(<128 x half> %op) - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -1612,7 +1612,7 @@ define <4 x float> @fsqrt_v4f32(<4 x float> %op) vscale_range(2,0) #0 { ret <4 x float> %res } -define void @fsqrt_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { +define void @fsqrt_v8f32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fsqrt_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1620,13 +1620,13 @@ define void @fsqrt_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: fsqrt z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <8 x float>, <8 x float>* %a + %op = load <8 x float>, ptr %a %res = call <8 x float> @llvm.sqrt.v8f32(<8 x float> %op) - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @fsqrt_v16f32(<16 x float>* %a) #0 { +define void @fsqrt_v16f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: fsqrt_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1646,13 +1646,13 @@ define void @fsqrt_v16f32(<16 x float>* %a) #0 { ; VBITS_GE_512-NEXT: fsqrt z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <16 x float>, <16 x float>* %a + %op = load <16 x float>, ptr %a %res = call <16 x float> @llvm.sqrt.v16f32(<16 x float> %op) - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @fsqrt_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { +define void @fsqrt_v32f32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: fsqrt_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1660,13 +1660,13 @@ define void @fsqrt_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fsqrt z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x float>, <32 x float>* %a + %op = load <32 x float>, ptr %a %res = call <32 x float> @llvm.sqrt.v32f32(<32 x float> %op) - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @fsqrt_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { +define void @fsqrt_v64f32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: fsqrt_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1674,9 +1674,9 @@ define void @fsqrt_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: fsqrt z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x float>, <64 x float>* %a + %op = load <64 x float>, ptr %a %res = call <64 x float> @llvm.sqrt.v64f32(<64 x float> %op) - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -1700,7 +1700,7 @@ define <2 x double> @fsqrt_v2f64(<2 x double> %op) vscale_range(2,0) #0 { ret <2 x double> %res } -define void @fsqrt_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { +define void @fsqrt_v4f64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fsqrt_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1708,13 +1708,13 @@ define void @fsqrt_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: fsqrt z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <4 x double>, <4 x double>* %a + %op = load <4 x double>, ptr %a %res = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %op) - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @fsqrt_v8f64(<8 x double>* %a) #0 { +define void @fsqrt_v8f64(ptr %a) #0 { ; VBITS_GE_256-LABEL: fsqrt_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1734,13 +1734,13 @@ define void @fsqrt_v8f64(<8 x double>* %a) #0 { ; VBITS_GE_512-NEXT: fsqrt z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <8 x double>, <8 x double>* %a + %op = load <8 x double>, ptr %a %res = call <8 x double> @llvm.sqrt.v8f64(<8 x double> %op) - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @fsqrt_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { +define void @fsqrt_v16f64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: fsqrt_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1748,13 +1748,13 @@ define void @fsqrt_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fsqrt z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x double>, <16 x double>* %a + %op = load <16 x double>, ptr %a %res = call <16 x double> @llvm.sqrt.v16f64(<16 x double> %op) - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @fsqrt_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { +define void @fsqrt_v32f64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: fsqrt_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1762,9 +1762,9 @@ define void @fsqrt_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: fsqrt z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x double>, <32 x double>* %a + %op = load <32 x double>, ptr %a %res = call <32 x double> @llvm.sqrt.v32f64(<32 x double> %op) - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } @@ -1792,7 +1792,7 @@ define <8 x half> @fsub_v8f16(<8 x half> %op1, <8 x half> %op2) vscale_range(2,0 ret <8 x half> %res } -define void @fsub_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 { +define void @fsub_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fsub_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -1801,14 +1801,14 @@ define void @fsub_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: fsub z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %res = fsub <16 x half> %op1, %op2 - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @fsub_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { +define void @fsub_v32f16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fsub_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -1831,14 +1831,14 @@ define void @fsub_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { ; VBITS_GE_512-NEXT: fsub z0.h, p0/m, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a - %op2 = load <32 x half>, <32 x half>* %b + %op1 = load <32 x half>, ptr %a + %op2 = load <32 x half>, ptr %b %res = fsub <32 x half> %op1, %op2 - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @fsub_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) #0 { +define void @fsub_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fsub_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -1847,14 +1847,14 @@ define void @fsub_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) #0 ; CHECK-NEXT: fsub z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a - %op2 = load <64 x half>, <64 x half>* %b + %op1 = load <64 x half>, ptr %a + %op2 = load <64 x half>, ptr %b %res = fsub <64 x half> %op1, %op2 - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @fsub_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16,0) #0 { +define void @fsub_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fsub_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1863,10 +1863,10 @@ define void @fsub_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16,0) ; CHECK-NEXT: fsub z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x half>, <128 x half>* %a - %op2 = load <128 x half>, <128 x half>* %b + %op1 = load <128 x half>, ptr %a + %op2 = load <128 x half>, ptr %b %res = fsub <128 x half> %op1, %op2 - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -1890,7 +1890,7 @@ define <4 x float> @fsub_v4f32(<4 x float> %op1, <4 x float> %op2) vscale_range( ret <4 x float> %res } -define void @fsub_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 { +define void @fsub_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fsub_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1899,14 +1899,14 @@ define void @fsub_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: fsub z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a - %op2 = load <8 x float>, <8 x float>* %b + %op1 = load <8 x float>, ptr %a + %op2 = load <8 x float>, ptr %b %res = fsub <8 x float> %op1, %op2 - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @fsub_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { +define void @fsub_v16f32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fsub_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1929,14 +1929,14 @@ define void @fsub_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { ; VBITS_GE_512-NEXT: fsub z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a - %op2 = load <16 x float>, <16 x float>* %b + %op1 = load <16 x float>, ptr %a + %op2 = load <16 x float>, ptr %b %res = fsub <16 x float> %op1, %op2 - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @fsub_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) #0 { +define void @fsub_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fsub_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1945,14 +1945,14 @@ define void @fsub_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) # ; CHECK-NEXT: fsub z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a - %op2 = load <32 x float>, <32 x float>* %b + %op1 = load <32 x float>, ptr %a + %op2 = load <32 x float>, ptr %b %res = fsub <32 x float> %op1, %op2 - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @fsub_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0) #0 { +define void @fsub_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fsub_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1961,10 +1961,10 @@ define void @fsub_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0) ; CHECK-NEXT: fsub z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a - %op2 = load <64 x float>, <64 x float>* %b + %op1 = load <64 x float>, ptr %a + %op2 = load <64 x float>, ptr %b %res = fsub <64 x float> %op1, %op2 - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -1988,7 +1988,7 @@ define <2 x double> @fsub_v2f64(<2 x double> %op1, <2 x double> %op2) vscale_ran ret <2 x double> %res } -define void @fsub_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @fsub_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fsub_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1997,14 +1997,14 @@ define void @fsub_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: fsub z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a - %op2 = load <4 x double>, <4 x double>* %b + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b %res = fsub <4 x double> %op1, %op2 - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @fsub_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { +define void @fsub_v8f64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fsub_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -2027,14 +2027,14 @@ define void @fsub_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: fsub z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a - %op2 = load <8 x double>, <8 x double>* %b + %op1 = load <8 x double>, ptr %a + %op2 = load <8 x double>, ptr %b %res = fsub <8 x double> %op1, %op2 - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @fsub_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @fsub_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fsub_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -2043,14 +2043,14 @@ define void @fsub_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8,0) ; CHECK-NEXT: fsub z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a - %op2 = load <16 x double>, <16 x double>* %b + %op1 = load <16 x double>, ptr %a + %op2 = load <16 x double>, ptr %b %res = fsub <16 x double> %op1, %op2 - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @fsub_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @fsub_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fsub_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -2059,10 +2059,10 @@ define void @fsub_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16,0 ; CHECK-NEXT: fsub z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a - %op2 = load <32 x double>, <32 x double>* %b + %op1 = load <32 x double>, ptr %a + %op2 = load <32 x double>, ptr %b %res = fsub <32 x double> %op1, %op2 - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } @@ -2090,7 +2090,7 @@ define <8 x half> @fabs_v8f16(<8 x half> %op) vscale_range(2,0) #0 { ret <8 x half> %res } -define void @fabs_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { +define void @fabs_v16f16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fabs_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -2098,13 +2098,13 @@ define void @fabs_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: fabs z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x half>, <16 x half>* %a + %op = load <16 x half>, ptr %a %res = call <16 x half> @llvm.fabs.v16f16(<16 x half> %op) - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @fabs_v32f16(<32 x half>* %a) #0 { +define void @fabs_v32f16(ptr %a) #0 { ; VBITS_GE_256-LABEL: fabs_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -2124,13 +2124,13 @@ define void @fabs_v32f16(<32 x half>* %a) #0 { ; VBITS_GE_512-NEXT: fabs z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <32 x half>, <32 x half>* %a + %op = load <32 x half>, ptr %a %res = call <32 x half> @llvm.fabs.v32f16(<32 x half> %op) - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @fabs_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { +define void @fabs_v64f16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: fabs_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -2138,13 +2138,13 @@ define void @fabs_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fabs z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x half>, <64 x half>* %a + %op = load <64 x half>, ptr %a %res = call <64 x half> @llvm.fabs.v64f16(<64 x half> %op) - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @fabs_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { +define void @fabs_v128f16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: fabs_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -2152,9 +2152,9 @@ define void @fabs_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: fabs z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x half>, <128 x half>* %a + %op = load <128 x half>, ptr %a %res = call <128 x half> @llvm.fabs.v128f16(<128 x half> %op) - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -2178,7 +2178,7 @@ define <4 x float> @fabs_v4f32(<4 x float> %op) vscale_range(2,0) #0 { ret <4 x float> %res } -define void @fabs_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { +define void @fabs_v8f32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fabs_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -2186,13 +2186,13 @@ define void @fabs_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: fabs z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <8 x float>, <8 x float>* %a + %op = load <8 x float>, ptr %a %res = call <8 x float> @llvm.fabs.v8f32(<8 x float> %op) - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @fabs_v16f32(<16 x float>* %a) #0 { +define void @fabs_v16f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: fabs_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -2212,13 +2212,13 @@ define void @fabs_v16f32(<16 x float>* %a) #0 { ; VBITS_GE_512-NEXT: fabs z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <16 x float>, <16 x float>* %a + %op = load <16 x float>, ptr %a %res = call <16 x float> @llvm.fabs.v16f32(<16 x float> %op) - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @fabs_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { +define void @fabs_v32f32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: fabs_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -2226,13 +2226,13 @@ define void @fabs_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fabs z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x float>, <32 x float>* %a + %op = load <32 x float>, ptr %a %res = call <32 x float> @llvm.fabs.v32f32(<32 x float> %op) - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @fabs_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { +define void @fabs_v64f32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: fabs_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -2240,9 +2240,9 @@ define void @fabs_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: fabs z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x float>, <64 x float>* %a + %op = load <64 x float>, ptr %a %res = call <64 x float> @llvm.fabs.v64f32(<64 x float> %op) - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -2266,7 +2266,7 @@ define <2 x double> @fabs_v2f64(<2 x double> %op) vscale_range(2,0) #0 { ret <2 x double> %res } -define void @fabs_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { +define void @fabs_v4f64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fabs_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -2274,13 +2274,13 @@ define void @fabs_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: fabs z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <4 x double>, <4 x double>* %a + %op = load <4 x double>, ptr %a %res = call <4 x double> @llvm.fabs.v4f64(<4 x double> %op) - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @fabs_v8f64(<8 x double>* %a) #0 { +define void @fabs_v8f64(ptr %a) #0 { ; VBITS_GE_256-LABEL: fabs_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -2300,13 +2300,13 @@ define void @fabs_v8f64(<8 x double>* %a) #0 { ; VBITS_GE_512-NEXT: fabs z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <8 x double>, <8 x double>* %a + %op = load <8 x double>, ptr %a %res = call <8 x double> @llvm.fabs.v8f64(<8 x double> %op) - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @fabs_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { +define void @fabs_v16f64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: fabs_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -2314,13 +2314,13 @@ define void @fabs_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fabs z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x double>, <16 x double>* %a + %op = load <16 x double>, ptr %a %res = call <16 x double> @llvm.fabs.v16f64(<16 x double> %op) - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @fabs_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { +define void @fabs_v32f64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: fabs_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -2328,9 +2328,9 @@ define void @fabs_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: fabs z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x double>, <32 x double>* %a + %op = load <32 x double>, ptr %a %res = call <32 x double> @llvm.fabs.v32f64(<32 x double> %op) - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-compares.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-compares.ll index db7bef03..582ff6a 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-compares.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-compares.ll @@ -31,7 +31,7 @@ define <8 x i16> @fcmp_oeq_v8f16(<8 x half> %op1, <8 x half> %op2) vscale_range( ret <8 x i16> %sext } -define void @fcmp_oeq_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_oeq_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_oeq_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -41,15 +41,15 @@ define void @fcmp_oeq_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp oeq <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } -define void @fcmp_oeq_v32f16(<32 x half>* %a, <32 x half>* %b, <32 x i16>* %c) #0 { +define void @fcmp_oeq_v32f16(ptr %a, ptr %b, ptr %c) #0 { ; VBITS_GE_256-LABEL: fcmp_oeq_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -75,15 +75,15 @@ define void @fcmp_oeq_v32f16(<32 x half>* %a, <32 x half>* %b, <32 x i16>* %c) # ; VBITS_GE_512-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x2] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a - %op2 = load <32 x half>, <32 x half>* %b + %op1 = load <32 x half>, ptr %a + %op2 = load <32 x half>, ptr %b %cmp = fcmp oeq <32 x half> %op1, %op2 %sext = sext <32 x i1> %cmp to <32 x i16> - store <32 x i16> %sext, <32 x i16>* %c + store <32 x i16> %sext, ptr %c ret void } -define void @fcmp_oeq_v64f16(<64 x half>* %a, <64 x half>* %b, <64 x i16>* %c) vscale_range(8,0) #0 { +define void @fcmp_oeq_v64f16(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 { ; CHECK-LABEL: fcmp_oeq_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -93,15 +93,15 @@ define void @fcmp_oeq_v64f16(<64 x half>* %a, <64 x half>* %b, <64 x i16>* %c) v ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a - %op2 = load <64 x half>, <64 x half>* %b + %op1 = load <64 x half>, ptr %a + %op2 = load <64 x half>, ptr %b %cmp = fcmp oeq <64 x half> %op1, %op2 %sext = sext <64 x i1> %cmp to <64 x i16> - store <64 x i16> %sext, <64 x i16>* %c + store <64 x i16> %sext, ptr %c ret void } -define void @fcmp_oeq_v128f16(<128 x half>* %a, <128 x half>* %b, <128 x i16>* %c) vscale_range(16,0) #0 { +define void @fcmp_oeq_v128f16(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 { ; CHECK-LABEL: fcmp_oeq_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -111,11 +111,11 @@ define void @fcmp_oeq_v128f16(<128 x half>* %a, <128 x half>* %b, <128 x i16>* % ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <128 x half>, <128 x half>* %a - %op2 = load <128 x half>, <128 x half>* %b + %op1 = load <128 x half>, ptr %a + %op2 = load <128 x half>, ptr %b %cmp = fcmp oeq <128 x half> %op1, %op2 %sext = sext <128 x i1> %cmp to <128 x i16> - store <128 x i16> %sext, <128 x i16>* %c + store <128 x i16> %sext, ptr %c ret void } @@ -141,7 +141,7 @@ define <4 x i32> @fcmp_oeq_v4f32(<4 x float> %op1, <4 x float> %op2) vscale_rang ret <4 x i32> %sext } -define void @fcmp_oeq_v8f32(<8 x float>* %a, <8 x float>* %b, <8 x i32>* %c) vscale_range(2,0) #0 { +define void @fcmp_oeq_v8f32(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_oeq_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -151,15 +151,15 @@ define void @fcmp_oeq_v8f32(<8 x float>* %a, <8 x float>* %b, <8 x i32>* %c) vsc ; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1w { z0.s }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a - %op2 = load <8 x float>, <8 x float>* %b + %op1 = load <8 x float>, ptr %a + %op2 = load <8 x float>, ptr %b %cmp = fcmp oeq <8 x float> %op1, %op2 %sext = sext <8 x i1> %cmp to <8 x i32> - store <8 x i32> %sext, <8 x i32>* %c + store <8 x i32> %sext, ptr %c ret void } -define void @fcmp_oeq_v16f32(<16 x float>* %a, <16 x float>* %b, <16 x i32>* %c) #0 { +define void @fcmp_oeq_v16f32(ptr %a, ptr %b, ptr %c) #0 { ; VBITS_GE_256-LABEL: fcmp_oeq_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -185,15 +185,15 @@ define void @fcmp_oeq_v16f32(<16 x float>* %a, <16 x float>* %b, <16 x i32>* %c) ; VBITS_GE_512-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x2] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a - %op2 = load <16 x float>, <16 x float>* %b + %op1 = load <16 x float>, ptr %a + %op2 = load <16 x float>, ptr %b %cmp = fcmp oeq <16 x float> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i32> - store <16 x i32> %sext, <16 x i32>* %c + store <16 x i32> %sext, ptr %c ret void } -define void @fcmp_oeq_v32f32(<32 x float>* %a, <32 x float>* %b, <32 x i32>* %c) vscale_range(8,0) #0 { +define void @fcmp_oeq_v32f32(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 { ; CHECK-LABEL: fcmp_oeq_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -203,15 +203,15 @@ define void @fcmp_oeq_v32f32(<32 x float>* %a, <32 x float>* %b, <32 x i32>* %c) ; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1w { z0.s }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a - %op2 = load <32 x float>, <32 x float>* %b + %op1 = load <32 x float>, ptr %a + %op2 = load <32 x float>, ptr %b %cmp = fcmp oeq <32 x float> %op1, %op2 %sext = sext <32 x i1> %cmp to <32 x i32> - store <32 x i32> %sext, <32 x i32>* %c + store <32 x i32> %sext, ptr %c ret void } -define void @fcmp_oeq_v64f32(<64 x float>* %a, <64 x float>* %b, <64 x i32>* %c) vscale_range(16,0) #0 { +define void @fcmp_oeq_v64f32(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 { ; CHECK-LABEL: fcmp_oeq_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -221,11 +221,11 @@ define void @fcmp_oeq_v64f32(<64 x float>* %a, <64 x float>* %b, <64 x i32>* %c) ; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1w { z0.s }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a - %op2 = load <64 x float>, <64 x float>* %b + %op1 = load <64 x float>, ptr %a + %op2 = load <64 x float>, ptr %b %cmp = fcmp oeq <64 x float> %op1, %op2 %sext = sext <64 x i1> %cmp to <64 x i32> - store <64 x i32> %sext, <64 x i32>* %c + store <64 x i32> %sext, ptr %c ret void } @@ -251,7 +251,7 @@ define <2 x i64> @fcmp_oeq_v2f64(<2 x double> %op1, <2 x double> %op2) vscale_ra ret <2 x i64> %sext } -define void @fcmp_oeq_v4f64(<4 x double>* %a, <4 x double>* %b, <4 x i64>* %c) vscale_range(2,0) #0 { +define void @fcmp_oeq_v4f64(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_oeq_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -261,15 +261,15 @@ define void @fcmp_oeq_v4f64(<4 x double>* %a, <4 x double>* %b, <4 x i64>* %c) v ; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1d { z0.d }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a - %op2 = load <4 x double>, <4 x double>* %b + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b %cmp = fcmp oeq <4 x double> %op1, %op2 %sext = sext <4 x i1> %cmp to <4 x i64> - store <4 x i64> %sext, <4 x i64>* %c + store <4 x i64> %sext, ptr %c ret void } -define void @fcmp_oeq_v8f64(<8 x double>* %a, <8 x double>* %b, <8 x i64>* %c) #0 { +define void @fcmp_oeq_v8f64(ptr %a, ptr %b, ptr %c) #0 { ; VBITS_GE_256-LABEL: fcmp_oeq_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -295,15 +295,15 @@ define void @fcmp_oeq_v8f64(<8 x double>* %a, <8 x double>* %b, <8 x i64>* %c) # ; VBITS_GE_512-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x2] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a - %op2 = load <8 x double>, <8 x double>* %b + %op1 = load <8 x double>, ptr %a + %op2 = load <8 x double>, ptr %b %cmp = fcmp oeq <8 x double> %op1, %op2 %sext = sext <8 x i1> %cmp to <8 x i64> - store <8 x i64> %sext, <8 x i64>* %c + store <8 x i64> %sext, ptr %c ret void } -define void @fcmp_oeq_v16f64(<16 x double>* %a, <16 x double>* %b, <16 x i64>* %c) vscale_range(8,0) #0 { +define void @fcmp_oeq_v16f64(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 { ; CHECK-LABEL: fcmp_oeq_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -313,15 +313,15 @@ define void @fcmp_oeq_v16f64(<16 x double>* %a, <16 x double>* %b, <16 x i64>* % ; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1d { z0.d }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a - %op2 = load <16 x double>, <16 x double>* %b + %op1 = load <16 x double>, ptr %a + %op2 = load <16 x double>, ptr %b %cmp = fcmp oeq <16 x double> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i64> - store <16 x i64> %sext, <16 x i64>* %c + store <16 x i64> %sext, ptr %c ret void } -define void @fcmp_oeq_v32f64(<32 x double>* %a, <32 x double>* %b, <32 x i64>* %c) vscale_range(16,0) #0 { +define void @fcmp_oeq_v32f64(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 { ; CHECK-LABEL: fcmp_oeq_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -331,11 +331,11 @@ define void @fcmp_oeq_v32f64(<32 x double>* %a, <32 x double>* %b, <32 x i64>* % ; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1d { z0.d }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a - %op2 = load <32 x double>, <32 x double>* %b + %op1 = load <32 x double>, ptr %a + %op2 = load <32 x double>, ptr %b %cmp = fcmp oeq <32 x double> %op1, %op2 %sext = sext <32 x i1> %cmp to <32 x i64> - store <32 x i64> %sext, <32 x i64>* %c + store <32 x i64> %sext, ptr %c ret void } @@ -343,7 +343,7 @@ define void @fcmp_oeq_v32f64(<32 x double>* %a, <32 x double>* %b, <32 x i64>* % ; FCMP UEQ ; -define void @fcmp_ueq_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_ueq_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_ueq_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -355,11 +355,11 @@ define void @fcmp_ueq_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp ueq <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } @@ -367,7 +367,7 @@ define void @fcmp_ueq_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; FCMP ONE ; -define void @fcmp_one_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_one_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_one_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -379,11 +379,11 @@ define void @fcmp_one_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp one <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } @@ -391,7 +391,7 @@ define void @fcmp_one_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; FCMP UNE ; -define void @fcmp_une_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_une_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_une_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -401,11 +401,11 @@ define void @fcmp_une_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp une <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } @@ -413,7 +413,7 @@ define void @fcmp_une_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; FCMP OGT ; -define void @fcmp_ogt_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_ogt_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_ogt_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -423,11 +423,11 @@ define void @fcmp_ogt_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp ogt <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } @@ -435,7 +435,7 @@ define void @fcmp_ogt_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; FCMP UGT ; -define void @fcmp_ugt_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_ugt_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_ugt_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -447,11 +447,11 @@ define void @fcmp_ugt_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp ugt <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } @@ -459,7 +459,7 @@ define void @fcmp_ugt_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; FCMP OLT ; -define void @fcmp_olt_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_olt_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_olt_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -469,11 +469,11 @@ define void @fcmp_olt_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp olt <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } @@ -481,7 +481,7 @@ define void @fcmp_olt_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; FCMP ULT ; -define void @fcmp_ult_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_ult_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_ult_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -493,11 +493,11 @@ define void @fcmp_ult_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp ult <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } @@ -505,7 +505,7 @@ define void @fcmp_ult_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; FCMP OGE ; -define void @fcmp_oge_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_oge_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_oge_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -515,11 +515,11 @@ define void @fcmp_oge_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp oge <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } @@ -527,7 +527,7 @@ define void @fcmp_oge_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; FCMP UGE ; -define void @fcmp_uge_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_uge_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_uge_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -539,11 +539,11 @@ define void @fcmp_uge_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp uge <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } @@ -551,7 +551,7 @@ define void @fcmp_uge_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; FCMP OLE ; -define void @fcmp_ole_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_ole_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_ole_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -561,11 +561,11 @@ define void @fcmp_ole_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp ole <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } @@ -573,7 +573,7 @@ define void @fcmp_ole_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; FCMP ULE ; -define void @fcmp_ule_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_ule_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_ule_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -585,11 +585,11 @@ define void @fcmp_ule_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp ule <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } @@ -597,7 +597,7 @@ define void @fcmp_ule_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; FCMP UNO ; -define void @fcmp_uno_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_uno_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_uno_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -607,11 +607,11 @@ define void @fcmp_uno_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp uno <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } @@ -619,7 +619,7 @@ define void @fcmp_uno_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; FCMP ORD ; -define void @fcmp_ord_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_ord_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_ord_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -631,11 +631,11 @@ define void @fcmp_ord_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp ord <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } @@ -643,7 +643,7 @@ define void @fcmp_ord_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) v ; FCMP EQ ; -define void @fcmp_eq_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_eq_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_eq_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -653,11 +653,11 @@ define void @fcmp_eq_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vs ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp fast oeq <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } @@ -665,7 +665,7 @@ define void @fcmp_eq_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vs ; FCMP NE ; -define void @fcmp_ne_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_ne_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_ne_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -675,11 +675,11 @@ define void @fcmp_ne_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vs ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp fast one <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } @@ -687,7 +687,7 @@ define void @fcmp_ne_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vs ; FCMP GT ; -define void @fcmp_gt_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_gt_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_gt_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -697,11 +697,11 @@ define void @fcmp_gt_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vs ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp fast ogt <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } @@ -709,7 +709,7 @@ define void @fcmp_gt_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vs ; FCMP LT ; -define void @fcmp_lt_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_lt_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_lt_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -719,11 +719,11 @@ define void @fcmp_lt_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vs ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp fast olt <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } @@ -731,7 +731,7 @@ define void @fcmp_lt_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vs ; FCMP GE ; -define void @fcmp_ge_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_ge_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_ge_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -741,11 +741,11 @@ define void @fcmp_ge_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vs ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp fast oge <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } @@ -753,7 +753,7 @@ define void @fcmp_ge_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vs ; FCMP LE ; -define void @fcmp_le_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vscale_range(2,0) #0 { +define void @fcmp_le_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fcmp_le_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -763,11 +763,11 @@ define void @fcmp_le_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) vs ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x2] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %cmp = fcmp fast ole <16 x half> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %c + store <16 x i16> %sext, ptr %c ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-convert.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-convert.ll index 72d0a56..25876f0 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-convert.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-convert.ll @@ -4,7 +4,7 @@ target triple = "aarch64-unknown-linux-gnu" ; Ensure we don't crash when trying to combine fp<->int conversions -define void @fp_convert_combine_crash(<8 x float> *%a, <8 x i32> *%b) #0 { +define void @fp_convert_combine_crash(ptr %a, ptr %b) #0 { ; CHECK-LABEL: fp_convert_combine_crash: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s @@ -14,11 +14,11 @@ define void @fp_convert_combine_crash(<8 x float> *%a, <8 x i32> *%b) #0 { ; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %f = load <8 x float>, <8 x float>* %a + %f = load <8 x float>, ptr %a %mul.i = fmul <8 x float> %f, %vcvt.i = fptosi <8 x float> %mul.i to <8 x i32> - store <8 x i32> %vcvt.i, <8 x i32>* %b + store <8 x i32> %vcvt.i, ptr %b ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll index 6799151..0bf8b93 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll @@ -10,34 +10,34 @@ target triple = "aarch64-unknown-linux-gnu" ; ; Don't use SVE for 64-bit vectors. -define void @fcvt_v2f16_v2f32(<2 x half>* %a, <2 x float>* %b) vscale_range(2,0) #0 { +define void @fcvt_v2f16_v2f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvt_v2f16_v2f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr s0, [x0] ; CHECK-NEXT: fcvtl v0.4s, v0.4h ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret - %op1 = load <2 x half>, <2 x half>* %a + %op1 = load <2 x half>, ptr %a %res = fpext <2 x half> %op1 to <2 x float> - store <2 x float> %res, <2 x float>* %b + store <2 x float> %res, ptr %b ret void } ; Don't use SVE for 128-bit vectors. -define void @fcvt_v4f16_v4f32(<4 x half>* %a, <4 x float>* %b) vscale_range(2,0) #0 { +define void @fcvt_v4f16_v4f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvt_v4f16_v4f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: fcvtl v0.4s, v0.4h ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x half>, <4 x half>* %a + %op1 = load <4 x half>, ptr %a %res = fpext <4 x half> %op1 to <4 x float> - store <4 x float> %res, <4 x float>* %b + store <4 x float> %res, ptr %b ret void } -define void @fcvt_v8f16_v8f32(<8 x half>* %a, <8 x float>* %b) vscale_range(2,0) #0 { +define void @fcvt_v8f16_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvt_v8f16_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -45,13 +45,13 @@ define void @fcvt_v8f16_v8f32(<8 x half>* %a, <8 x float>* %b) vscale_range(2,0) ; CHECK-NEXT: fcvt z0.s, p0/m, z0.h ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <8 x half>, <8 x half>* %a + %op1 = load <8 x half>, ptr %a %res = fpext <8 x half> %op1 to <8 x float> - store <8 x float> %res, <8 x float>* %b + store <8 x float> %res, ptr %b ret void } -define void @fcvt_v16f16_v16f32(<16 x half>* %a, <16 x float>* %b) #0 { +define void @fcvt_v16f16_v16f32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvt_v16f16_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -71,13 +71,13 @@ define void @fcvt_v16f16_v16f32(<16 x half>* %a, <16 x float>* %b) #0 { ; VBITS_GE_512-NEXT: fcvt z0.s, p0/m, z0.h ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a + %op1 = load <16 x half>, ptr %a %res = fpext <16 x half> %op1 to <16 x float> - store <16 x float> %res, <16 x float>* %b + store <16 x float> %res, ptr %b ret void } -define void @fcvt_v32f16_v32f32(<32 x half>* %a, <32 x float>* %b) vscale_range(8,0) #0 { +define void @fcvt_v32f16_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvt_v32f16_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -85,13 +85,13 @@ define void @fcvt_v32f16_v32f32(<32 x half>* %a, <32 x float>* %b) vscale_range( ; CHECK-NEXT: fcvt z0.s, p0/m, z0.h ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a + %op1 = load <32 x half>, ptr %a %res = fpext <32 x half> %op1 to <32 x float> - store <32 x float> %res, <32 x float>* %b + store <32 x float> %res, ptr %b ret void } -define void @fcvt_v64f16_v64f32(<64 x half>* %a, <64 x float>* %b) vscale_range(16,0) #0 { +define void @fcvt_v64f16_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvt_v64f16_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -99,9 +99,9 @@ define void @fcvt_v64f16_v64f32(<64 x half>* %a, <64 x float>* %b) vscale_range( ; CHECK-NEXT: fcvt z0.s, p0/m, z0.h ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a + %op1 = load <64 x half>, ptr %a %res = fpext <64 x half> %op1 to <64 x float> - store <64 x float> %res, <64 x float>* %b + store <64 x float> %res, ptr %b ret void } @@ -110,21 +110,21 @@ define void @fcvt_v64f16_v64f32(<64 x half>* %a, <64 x float>* %b) vscale_range( ; ; Don't use SVE for 64-bit vectors. -define void @fcvt_v1f16_v1f64(<1 x half>* %a, <1 x double>* %b) vscale_range(2,0) #0 { +define void @fcvt_v1f16_v1f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvt_v1f16_v1f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr h0, [x0] ; CHECK-NEXT: fcvt d0, h0 ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret - %op1 = load <1 x half>, <1 x half>* %a + %op1 = load <1 x half>, ptr %a %res = fpext <1 x half> %op1 to <1 x double> - store <1 x double> %res, <1 x double>* %b + store <1 x double> %res, ptr %b ret void } ; v2f16 is not legal for NEON, so use SVE -define void @fcvt_v2f16_v2f64(<2 x half>* %a, <2 x double>* %b) vscale_range(2,0) #0 { +define void @fcvt_v2f16_v2f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvt_v2f16_v2f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr s0, [x0] @@ -134,13 +134,13 @@ define void @fcvt_v2f16_v2f64(<2 x half>* %a, <2 x double>* %b) vscale_range(2,0 ; CHECK-NEXT: fcvt z0.d, p0/m, z0.h ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %op1 = load <2 x half>, <2 x half>* %a + %op1 = load <2 x half>, ptr %a %res = fpext <2 x half> %op1 to <2 x double> - store <2 x double> %res, <2 x double>* %b + store <2 x double> %res, ptr %b ret void } -define void @fcvt_v4f16_v4f64(<4 x half>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @fcvt_v4f16_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvt_v4f16_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -148,13 +148,13 @@ define void @fcvt_v4f16_v4f64(<4 x half>* %a, <4 x double>* %b) vscale_range(2,0 ; CHECK-NEXT: fcvt z0.d, p0/m, z0.h ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x half>, <4 x half>* %a + %op1 = load <4 x half>, ptr %a %res = fpext <4 x half> %op1 to <4 x double> - store <4 x double> %res, <4 x double>* %b + store <4 x double> %res, ptr %b ret void } -define void @fcvt_v8f16_v8f64(<8 x half>* %a, <8 x double>* %b) #0 { +define void @fcvt_v8f16_v8f64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvt_v8f16_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -174,13 +174,13 @@ define void @fcvt_v8f16_v8f64(<8 x half>* %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: fcvt z0.d, p0/m, z0.h ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x half>, <8 x half>* %a + %op1 = load <8 x half>, ptr %a %res = fpext <8 x half> %op1 to <8 x double> - store <8 x double> %res, <8 x double>* %b + store <8 x double> %res, ptr %b ret void } -define void @fcvt_v16f16_v16f64(<16 x half>* %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @fcvt_v16f16_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvt_v16f16_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -188,13 +188,13 @@ define void @fcvt_v16f16_v16f64(<16 x half>* %a, <16 x double>* %b) vscale_range ; CHECK-NEXT: fcvt z0.d, p0/m, z0.h ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a + %op1 = load <16 x half>, ptr %a %res = fpext <16 x half> %op1 to <16 x double> - store <16 x double> %res, <16 x double>* %b + store <16 x double> %res, ptr %b ret void } -define void @fcvt_v32f16_v32f64(<32 x half>* %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @fcvt_v32f16_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvt_v32f16_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -202,9 +202,9 @@ define void @fcvt_v32f16_v32f64(<32 x half>* %a, <32 x double>* %b) vscale_range ; CHECK-NEXT: fcvt z0.d, p0/m, z0.h ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a + %op1 = load <32 x half>, ptr %a %res = fpext <32 x half> %op1 to <32 x double> - store <32 x double> %res, <32 x double>* %b + store <32 x double> %res, ptr %b ret void } @@ -213,34 +213,34 @@ define void @fcvt_v32f16_v32f64(<32 x half>* %a, <32 x double>* %b) vscale_range ; ; Don't use SVE for 64-bit vectors. -define void @fcvt_v1f32_v1f64(<1 x float>* %a, <1 x double>* %b) vscale_range(2,0) #0 { +define void @fcvt_v1f32_v1f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvt_v1f32_v1f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr s0, [x0] ; CHECK-NEXT: fcvtl v0.2d, v0.2s ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret - %op1 = load <1 x float>, <1 x float>* %a + %op1 = load <1 x float>, ptr %a %res = fpext <1 x float> %op1 to <1 x double> - store <1 x double> %res, <1 x double>* %b + store <1 x double> %res, ptr %b ret void } ; Don't use SVE for 128-bit vectors. -define void @fcvt_v2f32_v2f64(<2 x float>* %a, <2 x double>* %b) vscale_range(2,0) #0 { +define void @fcvt_v2f32_v2f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvt_v2f32_v2f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: fcvtl v0.2d, v0.2s ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %op1 = load <2 x float>, <2 x float>* %a + %op1 = load <2 x float>, ptr %a %res = fpext <2 x float> %op1 to <2 x double> - store <2 x double> %res, <2 x double>* %b + store <2 x double> %res, ptr %b ret void } -define void @fcvt_v4f32_v4f64(<4 x float>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @fcvt_v4f32_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvt_v4f32_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -248,13 +248,13 @@ define void @fcvt_v4f32_v4f64(<4 x float>* %a, <4 x double>* %b) vscale_range(2, ; CHECK-NEXT: fcvt z0.d, p0/m, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x float>, <4 x float>* %a + %op1 = load <4 x float>, ptr %a %res = fpext <4 x float> %op1 to <4 x double> - store <4 x double> %res, <4 x double>* %b + store <4 x double> %res, ptr %b ret void } -define void @fcvt_v8f32_v8f64(<8 x float>* %a, <8 x double>* %b) #0 { +define void @fcvt_v8f32_v8f64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvt_v8f32_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -274,13 +274,13 @@ define void @fcvt_v8f32_v8f64(<8 x float>* %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: fcvt z0.d, p0/m, z0.s ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a + %op1 = load <8 x float>, ptr %a %res = fpext <8 x float> %op1 to <8 x double> - store <8 x double> %res, <8 x double>* %b + store <8 x double> %res, ptr %b ret void } -define void @fcvt_v16f32_v16f64(<16 x float>* %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @fcvt_v16f32_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvt_v16f32_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -288,13 +288,13 @@ define void @fcvt_v16f32_v16f64(<16 x float>* %a, <16 x double>* %b) vscale_rang ; CHECK-NEXT: fcvt z0.d, p0/m, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a + %op1 = load <16 x float>, ptr %a %res = fpext <16 x float> %op1 to <16 x double> - store <16 x double> %res, <16 x double>* %b + store <16 x double> %res, ptr %b ret void } -define void @fcvt_v32f32_v32f64(<32 x float>* %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @fcvt_v32f32_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvt_v32f32_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -302,9 +302,9 @@ define void @fcvt_v32f32_v32f64(<32 x float>* %a, <32 x double>* %b) vscale_rang ; CHECK-NEXT: fcvt z0.d, p0/m, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a + %op1 = load <32 x float>, ptr %a %res = fpext <32 x float> %op1 to <32 x double> - store <32 x double> %res, <32 x double>* %b + store <32 x double> %res, ptr %b ret void } @@ -313,34 +313,34 @@ define void @fcvt_v32f32_v32f64(<32 x float>* %a, <32 x double>* %b) vscale_rang ; ; Don't use SVE for 64-bit vectors. -define void @fcvt_v2f32_v2f16(<2 x float>* %a, <2 x half>* %b) vscale_range(2,0) #0 { +define void @fcvt_v2f32_v2f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvt_v2f32_v2f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: fcvtn v0.4h, v0.4s ; CHECK-NEXT: str s0, [x1] ; CHECK-NEXT: ret - %op1 = load <2 x float>, <2 x float>* %a + %op1 = load <2 x float>, ptr %a %res = fptrunc <2 x float> %op1 to <2 x half> - store <2 x half> %res, <2 x half>* %b + store <2 x half> %res, ptr %b ret void } ; Don't use SVE for 128-bit vectors. -define void @fcvt_v4f32_v4f16(<4 x float>* %a, <4 x half>* %b) vscale_range(2,0) #0 { +define void @fcvt_v4f32_v4f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvt_v4f32_v4f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: fcvtn v0.4h, v0.4s ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x float>, <4 x float>* %a + %op1 = load <4 x float>, ptr %a %res = fptrunc <4 x float> %op1 to <4 x half> - store <4 x half> %res, <4 x half>* %b + store <4 x half> %res, ptr %b ret void } -define void @fcvt_v8f32_v8f16(<8 x float>* %a, <8 x half>* %b) vscale_range(2,0) #0 { +define void @fcvt_v8f32_v8f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvt_v8f32_v8f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -348,13 +348,13 @@ define void @fcvt_v8f32_v8f16(<8 x float>* %a, <8 x half>* %b) vscale_range(2,0) ; CHECK-NEXT: fcvt z0.h, p0/m, z0.s ; CHECK-NEXT: st1h { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a + %op1 = load <8 x float>, ptr %a %res = fptrunc <8 x float> %op1 to <8 x half> - store <8 x half> %res, <8 x half>* %b + store <8 x half> %res, ptr %b ret void } -define void @fcvt_v16f32_v16f16(<16 x float>* %a, <16 x half>* %b) #0 { +define void @fcvt_v16f32_v16f16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvt_v16f32_v16f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -374,13 +374,13 @@ define void @fcvt_v16f32_v16f16(<16 x float>* %a, <16 x half>* %b) #0 { ; VBITS_GE_512-NEXT: fcvt z0.h, p0/m, z0.s ; VBITS_GE_512-NEXT: st1h { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a + %op1 = load <16 x float>, ptr %a %res = fptrunc <16 x float> %op1 to <16 x half> - store <16 x half> %res, <16 x half>* %b + store <16 x half> %res, ptr %b ret void } -define void @fcvt_v32f32_v32f16(<32 x float>* %a, <32 x half>* %b) vscale_range(8,0) #0 { +define void @fcvt_v32f32_v32f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvt_v32f32_v32f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -388,13 +388,13 @@ define void @fcvt_v32f32_v32f16(<32 x float>* %a, <32 x half>* %b) vscale_range( ; CHECK-NEXT: fcvt z0.h, p0/m, z0.s ; CHECK-NEXT: st1h { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a + %op1 = load <32 x float>, ptr %a %res = fptrunc <32 x float> %op1 to <32 x half> - store <32 x half> %res, <32 x half>* %b + store <32 x half> %res, ptr %b ret void } -define void @fcvt_v64f32_v64f16(<64 x float>* %a, <64 x half>* %b) vscale_range(16,0) #0 { +define void @fcvt_v64f32_v64f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvt_v64f32_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -402,9 +402,9 @@ define void @fcvt_v64f32_v64f16(<64 x float>* %a, <64 x half>* %b) vscale_range( ; CHECK-NEXT: fcvt z0.h, p0/m, z0.s ; CHECK-NEXT: st1h { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a + %op1 = load <64 x float>, ptr %a %res = fptrunc <64 x float> %op1 to <64 x half> - store <64 x half> %res, <64 x half>* %b + store <64 x half> %res, ptr %b ret void } @@ -413,21 +413,21 @@ define void @fcvt_v64f32_v64f16(<64 x float>* %a, <64 x half>* %b) vscale_range( ; ; Don't use SVE for 64-bit vectors. -define void @fcvt_v1f64_v1f16(<1 x double>* %a, <1 x half>* %b) vscale_range(2,0) #0 { +define void @fcvt_v1f64_v1f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvt_v1f64_v1f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: fcvt h0, d0 ; CHECK-NEXT: str h0, [x1] ; CHECK-NEXT: ret - %op1 = load <1 x double>, <1 x double>* %a + %op1 = load <1 x double>, ptr %a %res = fptrunc <1 x double> %op1 to <1 x half> - store <1 x half> %res, <1 x half>* %b + store <1 x half> %res, ptr %b ret void } ; v2f16 is not legal for NEON, so use SVE -define void @fcvt_v2f64_v2f16(<2 x double>* %a, <2 x half>* %b) vscale_range(2,0) #0 { +define void @fcvt_v2f64_v2f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvt_v2f64_v2f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -437,13 +437,13 @@ define void @fcvt_v2f64_v2f16(<2 x double>* %a, <2 x half>* %b) vscale_range(2,0 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: str s0, [x1] ; CHECK-NEXT: ret - %op1 = load <2 x double>, <2 x double>* %a + %op1 = load <2 x double>, ptr %a %res = fptrunc <2 x double> %op1 to <2 x half> - store <2 x half> %res, <2 x half>* %b + store <2 x half> %res, ptr %b ret void } -define void @fcvt_v4f64_v4f16(<4 x double>* %a, <4 x half>* %b) vscale_range(2,0) #0 { +define void @fcvt_v4f64_v4f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvt_v4f64_v4f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -451,13 +451,13 @@ define void @fcvt_v4f64_v4f16(<4 x double>* %a, <4 x half>* %b) vscale_range(2,0 ; CHECK-NEXT: fcvt z0.h, p0/m, z0.d ; CHECK-NEXT: st1h { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a + %op1 = load <4 x double>, ptr %a %res = fptrunc <4 x double> %op1 to <4 x half> - store <4 x half> %res, <4 x half>* %b + store <4 x half> %res, ptr %b ret void } -define void @fcvt_v8f64_v8f16(<8 x double>* %a, <8 x half>* %b) #0 { +define void @fcvt_v8f64_v8f16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvt_v8f64_v8f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -482,13 +482,13 @@ define void @fcvt_v8f64_v8f16(<8 x double>* %a, <8 x half>* %b) #0 { ; VBITS_GE_512-NEXT: fcvt z0.h, p0/m, z0.d ; VBITS_GE_512-NEXT: st1h { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a + %op1 = load <8 x double>, ptr %a %res = fptrunc <8 x double> %op1 to <8 x half> - store <8 x half> %res, <8 x half>* %b + store <8 x half> %res, ptr %b ret void } -define void @fcvt_v16f64_v16f16(<16 x double>* %a, <16 x half>* %b) vscale_range(8,0) #0 { +define void @fcvt_v16f64_v16f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvt_v16f64_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -496,13 +496,13 @@ define void @fcvt_v16f64_v16f16(<16 x double>* %a, <16 x half>* %b) vscale_range ; CHECK-NEXT: fcvt z0.h, p0/m, z0.d ; CHECK-NEXT: st1h { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a + %op1 = load <16 x double>, ptr %a %res = fptrunc <16 x double> %op1 to <16 x half> - store <16 x half> %res, <16 x half>* %b + store <16 x half> %res, ptr %b ret void } -define void @fcvt_v32f64_v32f16(<32 x double>* %a, <32 x half>* %b) vscale_range(16,0) #0 { +define void @fcvt_v32f64_v32f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvt_v32f64_v32f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -510,9 +510,9 @@ define void @fcvt_v32f64_v32f16(<32 x double>* %a, <32 x half>* %b) vscale_range ; CHECK-NEXT: fcvt z0.h, p0/m, z0.d ; CHECK-NEXT: st1h { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a + %op1 = load <32 x double>, ptr %a %res = fptrunc <32 x double> %op1 to <32 x half> - store <32 x half> %res, <32 x half>* %b + store <32 x half> %res, ptr %b ret void } @@ -521,7 +521,7 @@ define void @fcvt_v32f64_v32f16(<32 x double>* %a, <32 x half>* %b) vscale_range ; ; Don't use SVE for 64-bit vectors. -define void @fcvt_v1f64_v1f32(<1 x double> %op1, <1 x float>* %b) vscale_range(2,0) #0 { +define void @fcvt_v1f64_v1f32(<1 x double> %op1, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvt_v1f64_v1f32: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 @@ -529,23 +529,23 @@ define void @fcvt_v1f64_v1f32(<1 x double> %op1, <1 x float>* %b) vscale_range(2 ; CHECK-NEXT: str s0, [x0] ; CHECK-NEXT: ret %res = fptrunc <1 x double> %op1 to <1 x float> - store <1 x float> %res, <1 x float>* %b + store <1 x float> %res, ptr %b ret void } ; Don't use SVE for 128-bit vectors. -define void @fcvt_v2f64_v2f32(<2 x double> %op1, <2 x float>* %b) vscale_range(2,0) #0 { +define void @fcvt_v2f64_v2f32(<2 x double> %op1, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvt_v2f64_v2f32: ; CHECK: // %bb.0: ; CHECK-NEXT: fcvtn v0.2s, v0.2d ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret %res = fptrunc <2 x double> %op1 to <2 x float> - store <2 x float> %res, <2 x float>* %b + store <2 x float> %res, ptr %b ret void } -define void @fcvt_v4f64_v4f32(<4 x double>* %a, <4 x float>* %b) vscale_range(2,0) #0 { +define void @fcvt_v4f64_v4f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvt_v4f64_v4f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -553,13 +553,13 @@ define void @fcvt_v4f64_v4f32(<4 x double>* %a, <4 x float>* %b) vscale_range(2, ; CHECK-NEXT: fcvt z0.s, p0/m, z0.d ; CHECK-NEXT: st1w { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a + %op1 = load <4 x double>, ptr %a %res = fptrunc <4 x double> %op1 to <4 x float> - store <4 x float> %res, <4 x float>* %b + store <4 x float> %res, ptr %b ret void } -define void @fcvt_v8f64_v8f32(<8 x double>* %a, <8 x float>* %b) #0 { +define void @fcvt_v8f64_v8f32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvt_v8f64_v8f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -579,13 +579,13 @@ define void @fcvt_v8f64_v8f32(<8 x double>* %a, <8 x float>* %b) #0 { ; VBITS_GE_512-NEXT: fcvt z0.s, p0/m, z0.d ; VBITS_GE_512-NEXT: st1w { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a + %op1 = load <8 x double>, ptr %a %res = fptrunc <8 x double> %op1 to <8 x float> - store <8 x float> %res, <8 x float>* %b + store <8 x float> %res, ptr %b ret void } -define void @fcvt_v16f64_v16f32(<16 x double>* %a, <16 x float>* %b) vscale_range(8,0) #0 { +define void @fcvt_v16f64_v16f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvt_v16f64_v16f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -593,13 +593,13 @@ define void @fcvt_v16f64_v16f32(<16 x double>* %a, <16 x float>* %b) vscale_rang ; CHECK-NEXT: fcvt z0.s, p0/m, z0.d ; CHECK-NEXT: st1w { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a + %op1 = load <16 x double>, ptr %a %res = fptrunc <16 x double> %op1 to <16 x float> - store <16 x float> %res, <16 x float>* %b + store <16 x float> %res, ptr %b ret void } -define void @fcvt_v32f64_v32f32(<32 x double>* %a, <32 x float>* %b) vscale_range(16,0) #0 { +define void @fcvt_v32f64_v32f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvt_v32f64_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -607,9 +607,9 @@ define void @fcvt_v32f64_v32f32(<32 x double>* %a, <32 x float>* %b) vscale_rang ; CHECK-NEXT: fcvt z0.s, p0/m, z0.d ; CHECK-NEXT: st1w { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a + %op1 = load <32 x double>, ptr %a %res = fptrunc <32 x double> %op1 to <32 x float> - store <32 x float> %res, <32 x float>* %b + store <32 x float> %res, ptr %b ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-fma.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-fma.ll index 2d0f8da..a329320 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-fma.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-fma.ll @@ -33,7 +33,7 @@ define <8 x half> @fma_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x half> %op3) ret <8 x half> %res } -define void @fma_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x half>* %c) vscale_range(2,0) #0 { +define void @fma_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fma_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -43,16 +43,16 @@ define void @fma_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x half>* %c) vscal ; CHECK-NEXT: fmad z0.h, p0/m, z1.h, z2.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b - %op3 = load <16 x half>, <16 x half>* %c + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %op3 = load <16 x half>, ptr %c %mul = fmul contract <16 x half> %op1, %op2 %res = fadd contract <16 x half> %mul, %op3 - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @fma_v32f16(<32 x half>* %a, <32 x half>* %b, <32 x half>* %c) #0 { +define void @fma_v32f16(ptr %a, ptr %b, ptr %c) #0 { ; VBITS_GE_256-LABEL: fma_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -78,16 +78,16 @@ define void @fma_v32f16(<32 x half>* %a, <32 x half>* %b, <32 x half>* %c) #0 { ; VBITS_GE_512-NEXT: fmad z0.h, p0/m, z1.h, z2.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a - %op2 = load <32 x half>, <32 x half>* %b - %op3 = load <32 x half>, <32 x half>* %c + %op1 = load <32 x half>, ptr %a + %op2 = load <32 x half>, ptr %b + %op3 = load <32 x half>, ptr %c %mul = fmul contract <32 x half> %op1, %op2 %res = fadd contract <32 x half> %mul, %op3 - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @fma_v64f16(<64 x half>* %a, <64 x half>* %b, <64 x half>* %c) vscale_range(8,0) #0 { +define void @fma_v64f16(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 { ; CHECK-LABEL: fma_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -97,16 +97,16 @@ define void @fma_v64f16(<64 x half>* %a, <64 x half>* %b, <64 x half>* %c) vscal ; CHECK-NEXT: fmad z0.h, p0/m, z1.h, z2.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a - %op2 = load <64 x half>, <64 x half>* %b - %op3 = load <64 x half>, <64 x half>* %c + %op1 = load <64 x half>, ptr %a + %op2 = load <64 x half>, ptr %b + %op3 = load <64 x half>, ptr %c %mul = fmul contract <64 x half> %op1, %op2 %res = fadd contract <64 x half> %mul, %op3 - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @fma_v128f16(<128 x half>* %a, <128 x half>* %b, <128 x half>* %c) vscale_range(16,0) #0 { +define void @fma_v128f16(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 { ; CHECK-LABEL: fma_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -116,12 +116,12 @@ define void @fma_v128f16(<128 x half>* %a, <128 x half>* %b, <128 x half>* %c) v ; CHECK-NEXT: fmad z0.h, p0/m, z1.h, z2.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x half>, <128 x half>* %a - %op2 = load <128 x half>, <128 x half>* %b - %op3 = load <128 x half>, <128 x half>* %c + %op1 = load <128 x half>, ptr %a + %op2 = load <128 x half>, ptr %b + %op3 = load <128 x half>, ptr %c %mul = fmul contract <128 x half> %op1, %op2 %res = fadd contract <128 x half> %mul, %op3 - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -149,7 +149,7 @@ define <4 x float> @fma_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x float> %o ret <4 x float> %res } -define void @fma_v8f32(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) vscale_range(2,0) #0 { +define void @fma_v8f32(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fma_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -159,16 +159,16 @@ define void @fma_v8f32(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) vscale ; CHECK-NEXT: fmad z0.s, p0/m, z1.s, z2.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a - %op2 = load <8 x float>, <8 x float>* %b - %op3 = load <8 x float>, <8 x float>* %c + %op1 = load <8 x float>, ptr %a + %op2 = load <8 x float>, ptr %b + %op3 = load <8 x float>, ptr %c %mul = fmul contract <8 x float> %op1, %op2 %res = fadd contract <8 x float> %mul, %op3 - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @fma_v16f32(<16 x float>* %a, <16 x float>* %b, <16 x float>* %c) #0 { +define void @fma_v16f32(ptr %a, ptr %b, ptr %c) #0 { ; VBITS_GE_256-LABEL: fma_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -194,16 +194,16 @@ define void @fma_v16f32(<16 x float>* %a, <16 x float>* %b, <16 x float>* %c) #0 ; VBITS_GE_512-NEXT: fmad z0.s, p0/m, z1.s, z2.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a - %op2 = load <16 x float>, <16 x float>* %b - %op3 = load <16 x float>, <16 x float>* %c + %op1 = load <16 x float>, ptr %a + %op2 = load <16 x float>, ptr %b + %op3 = load <16 x float>, ptr %c %mul = fmul contract <16 x float> %op1, %op2 %res = fadd contract <16 x float> %mul, %op3 - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @fma_v32f32(<32 x float>* %a, <32 x float>* %b, <32 x float>* %c) vscale_range(8,0) #0 { +define void @fma_v32f32(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 { ; CHECK-LABEL: fma_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -213,16 +213,16 @@ define void @fma_v32f32(<32 x float>* %a, <32 x float>* %b, <32 x float>* %c) vs ; CHECK-NEXT: fmad z0.s, p0/m, z1.s, z2.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a - %op2 = load <32 x float>, <32 x float>* %b - %op3 = load <32 x float>, <32 x float>* %c + %op1 = load <32 x float>, ptr %a + %op2 = load <32 x float>, ptr %b + %op3 = load <32 x float>, ptr %c %mul = fmul contract <32 x float> %op1, %op2 %res = fadd contract <32 x float> %mul, %op3 - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @fma_v64f32(<64 x float>* %a, <64 x float>* %b, <64 x float>* %c) vscale_range(16,0) #0 { +define void @fma_v64f32(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 { ; CHECK-LABEL: fma_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -232,12 +232,12 @@ define void @fma_v64f32(<64 x float>* %a, <64 x float>* %b, <64 x float>* %c) vs ; CHECK-NEXT: fmad z0.s, p0/m, z1.s, z2.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a - %op2 = load <64 x float>, <64 x float>* %b - %op3 = load <64 x float>, <64 x float>* %c + %op1 = load <64 x float>, ptr %a + %op2 = load <64 x float>, ptr %b + %op3 = load <64 x float>, ptr %c %mul = fmul contract <64 x float> %op1, %op2 %res = fadd contract <64 x float> %mul, %op3 - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -264,7 +264,7 @@ define <2 x double> @fma_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x double ret <2 x double> %res } -define void @fma_v4f64(<4 x double>* %a, <4 x double>* %b, <4 x double>* %c) vscale_range(2,0) #0 { +define void @fma_v4f64(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 { ; CHECK-LABEL: fma_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -274,16 +274,16 @@ define void @fma_v4f64(<4 x double>* %a, <4 x double>* %b, <4 x double>* %c) vsc ; CHECK-NEXT: fmad z0.d, p0/m, z1.d, z2.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a - %op2 = load <4 x double>, <4 x double>* %b - %op3 = load <4 x double>, <4 x double>* %c + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b + %op3 = load <4 x double>, ptr %c %mul = fmul contract <4 x double> %op1, %op2 %res = fadd contract <4 x double> %mul, %op3 - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @fma_v8f64(<8 x double>* %a, <8 x double>* %b, <8 x double>* %c) #0 { +define void @fma_v8f64(ptr %a, ptr %b, ptr %c) #0 { ; VBITS_GE_256-LABEL: fma_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -309,16 +309,16 @@ define void @fma_v8f64(<8 x double>* %a, <8 x double>* %b, <8 x double>* %c) #0 ; VBITS_GE_512-NEXT: fmad z0.d, p0/m, z1.d, z2.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a - %op2 = load <8 x double>, <8 x double>* %b - %op3 = load <8 x double>, <8 x double>* %c + %op1 = load <8 x double>, ptr %a + %op2 = load <8 x double>, ptr %b + %op3 = load <8 x double>, ptr %c %mul = fmul contract <8 x double> %op1, %op2 %res = fadd contract <8 x double> %mul, %op3 - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @fma_v16f64(<16 x double>* %a, <16 x double>* %b, <16 x double>* %c) vscale_range(8,0) #0 { +define void @fma_v16f64(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 { ; CHECK-LABEL: fma_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -328,16 +328,16 @@ define void @fma_v16f64(<16 x double>* %a, <16 x double>* %b, <16 x double>* %c) ; CHECK-NEXT: fmad z0.d, p0/m, z1.d, z2.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a - %op2 = load <16 x double>, <16 x double>* %b - %op3 = load <16 x double>, <16 x double>* %c + %op1 = load <16 x double>, ptr %a + %op2 = load <16 x double>, ptr %b + %op3 = load <16 x double>, ptr %c %mul = fmul contract <16 x double> %op1, %op2 %res = fadd contract <16 x double> %mul, %op3 - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @fma_v32f64(<32 x double>* %a, <32 x double>* %b, <32 x double>* %c) vscale_range(16,0) #0 { +define void @fma_v32f64(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 { ; CHECK-LABEL: fma_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -347,12 +347,12 @@ define void @fma_v32f64(<32 x double>* %a, <32 x double>* %b, <32 x double>* %c) ; CHECK-NEXT: fmad z0.d, p0/m, z1.d, z2.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a - %op2 = load <32 x double>, <32 x double>* %b - %op3 = load <32 x double>, <32 x double>* %c + %op1 = load <32 x double>, ptr %a + %op2 = load <32 x double>, ptr %b + %op3 = load <32 x double>, ptr %c %mul = fmul contract <32 x double> %op1, %op2 %res = fadd contract <32 x double> %mul, %op3 - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll index 955169c..1714be3 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll @@ -29,7 +29,7 @@ define <8 x half> @fmaxnm_v8f16(<8 x half> %op1, <8 x half> %op2) vscale_range(2 ret <8 x half> %res } -define void @fmaxnm_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 { +define void @fmaxnm_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fmaxnm_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -38,14 +38,14 @@ define void @fmaxnm_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) # ; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %res = call <16 x half> @llvm.maxnum.v16f16(<16 x half> %op1, <16 x half> %op2) - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @fmaxnm_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { +define void @fmaxnm_v32f16(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: fmaxnm_v32f16: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: mov x8, #16 @@ -68,14 +68,14 @@ define void @fmaxnm_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { ; VBITS_GE_512-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a - %op2 = load <32 x half>, <32 x half>* %b + %op1 = load <32 x half>, ptr %a + %op2 = load <32 x half>, ptr %b %res = call <32 x half> @llvm.maxnum.v32f16(<32 x half> %op1, <32 x half> %op2) - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @fmaxnm_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) #0 { +define void @fmaxnm_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fmaxnm_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -84,14 +84,14 @@ define void @fmaxnm_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) # ; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a - %op2 = load <64 x half>, <64 x half>* %b + %op1 = load <64 x half>, ptr %a + %op2 = load <64 x half>, ptr %b %res = call <64 x half> @llvm.maxnum.v64f16(<64 x half> %op1, <64 x half> %op2) - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @fmaxnm_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16,0) #0 { +define void @fmaxnm_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fmaxnm_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -100,10 +100,10 @@ define void @fmaxnm_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16, ; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x half>, <128 x half>* %a - %op2 = load <128 x half>, <128 x half>* %b + %op1 = load <128 x half>, ptr %a + %op2 = load <128 x half>, ptr %b %res = call <128 x half> @llvm.maxnum.v128f16(<128 x half> %op1, <128 x half> %op2) - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -127,7 +127,7 @@ define <4 x float> @fmaxnm_v4f32(<4 x float> %op1, <4 x float> %op2) vscale_rang ret <4 x float> %res } -define void @fmaxnm_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 { +define void @fmaxnm_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fmaxnm_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -136,14 +136,14 @@ define void @fmaxnm_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a - %op2 = load <8 x float>, <8 x float>* %b + %op1 = load <8 x float>, ptr %a + %op2 = load <8 x float>, ptr %b %res = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %op1, <8 x float> %op2) - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @fmaxnm_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { +define void @fmaxnm_v16f32(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: fmaxnm_v16f32: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: mov x8, #8 @@ -166,14 +166,14 @@ define void @fmaxnm_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { ; VBITS_GE_512-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a - %op2 = load <16 x float>, <16 x float>* %b + %op1 = load <16 x float>, ptr %a + %op2 = load <16 x float>, ptr %b %res = call <16 x float> @llvm.maxnum.v16f32(<16 x float> %op1, <16 x float> %op2) - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @fmaxnm_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) #0 { +define void @fmaxnm_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fmaxnm_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -182,14 +182,14 @@ define void @fmaxnm_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) ; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a - %op2 = load <32 x float>, <32 x float>* %b + %op1 = load <32 x float>, ptr %a + %op2 = load <32 x float>, ptr %b %res = call <32 x float> @llvm.maxnum.v32f32(<32 x float> %op1, <32 x float> %op2) - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @fmaxnm_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0) #0 { +define void @fmaxnm_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fmaxnm_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -198,10 +198,10 @@ define void @fmaxnm_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0 ; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a - %op2 = load <64 x float>, <64 x float>* %b + %op1 = load <64 x float>, ptr %a + %op2 = load <64 x float>, ptr %b %res = call <64 x float> @llvm.maxnum.v64f32(<64 x float> %op1, <64 x float> %op2) - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -225,7 +225,7 @@ define <2 x double> @fmaxnm_v2f64(<2 x double> %op1, <2 x double> %op2) vscale_r ret <2 x double> %res } -define void @fmaxnm_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @fmaxnm_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fmaxnm_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -234,14 +234,14 @@ define void @fmaxnm_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) ; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a - %op2 = load <4 x double>, <4 x double>* %b + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b %res = call <4 x double> @llvm.maxnum.v4f64(<4 x double> %op1, <4 x double> %op2) - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @fmaxnm_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { +define void @fmaxnm_v8f64(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: fmaxnm_v8f64: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: mov x8, #4 @@ -264,14 +264,14 @@ define void @fmaxnm_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a - %op2 = load <8 x double>, <8 x double>* %b + %op1 = load <8 x double>, ptr %a + %op2 = load <8 x double>, ptr %b %res = call <8 x double> @llvm.maxnum.v8f64(<8 x double> %op1, <8 x double> %op2) - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @fmaxnm_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @fmaxnm_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fmaxnm_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -280,14 +280,14 @@ define void @fmaxnm_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8, ; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a - %op2 = load <16 x double>, <16 x double>* %b + %op1 = load <16 x double>, ptr %a + %op2 = load <16 x double>, ptr %b %res = call <16 x double> @llvm.maxnum.v16f64(<16 x double> %op1, <16 x double> %op2) - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @fmaxnm_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @fmaxnm_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fmaxnm_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -296,10 +296,10 @@ define void @fmaxnm_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16 ; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a - %op2 = load <32 x double>, <32 x double>* %b + %op1 = load <32 x double>, ptr %a + %op2 = load <32 x double>, ptr %b %res = call <32 x double> @llvm.maxnum.v32f64(<32 x double> %op1, <32 x double> %op2) - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } @@ -327,7 +327,7 @@ define <8 x half> @fminnm_v8f16(<8 x half> %op1, <8 x half> %op2) vscale_range(2 ret <8 x half> %res } -define void @fminnm_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 { +define void @fminnm_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fminnm_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -336,14 +336,14 @@ define void @fminnm_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) # ; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %res = call <16 x half> @llvm.minnum.v16f16(<16 x half> %op1, <16 x half> %op2) - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @fminnm_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { +define void @fminnm_v32f16(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: fminnm_v32f16: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: mov x8, #16 @@ -366,14 +366,14 @@ define void @fminnm_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { ; VBITS_GE_512-NEXT: fminnm z0.h, p0/m, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a - %op2 = load <32 x half>, <32 x half>* %b + %op1 = load <32 x half>, ptr %a + %op2 = load <32 x half>, ptr %b %res = call <32 x half> @llvm.minnum.v32f16(<32 x half> %op1, <32 x half> %op2) - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @fminnm_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) #0 { +define void @fminnm_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fminnm_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -382,14 +382,14 @@ define void @fminnm_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) # ; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a - %op2 = load <64 x half>, <64 x half>* %b + %op1 = load <64 x half>, ptr %a + %op2 = load <64 x half>, ptr %b %res = call <64 x half> @llvm.minnum.v64f16(<64 x half> %op1, <64 x half> %op2) - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @fminnm_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16,0) #0 { +define void @fminnm_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fminnm_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -398,10 +398,10 @@ define void @fminnm_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16, ; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x half>, <128 x half>* %a - %op2 = load <128 x half>, <128 x half>* %b + %op1 = load <128 x half>, ptr %a + %op2 = load <128 x half>, ptr %b %res = call <128 x half> @llvm.minnum.v128f16(<128 x half> %op1, <128 x half> %op2) - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -425,7 +425,7 @@ define <4 x float> @fminnm_v4f32(<4 x float> %op1, <4 x float> %op2) vscale_rang ret <4 x float> %res } -define void @fminnm_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 { +define void @fminnm_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fminnm_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -434,14 +434,14 @@ define void @fminnm_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a - %op2 = load <8 x float>, <8 x float>* %b + %op1 = load <8 x float>, ptr %a + %op2 = load <8 x float>, ptr %b %res = call <8 x float> @llvm.minnum.v8f32(<8 x float> %op1, <8 x float> %op2) - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @fminnm_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { +define void @fminnm_v16f32(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: fminnm_v16f32: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: mov x8, #8 @@ -464,14 +464,14 @@ define void @fminnm_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { ; VBITS_GE_512-NEXT: fminnm z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a - %op2 = load <16 x float>, <16 x float>* %b + %op1 = load <16 x float>, ptr %a + %op2 = load <16 x float>, ptr %b %res = call <16 x float> @llvm.minnum.v16f32(<16 x float> %op1, <16 x float> %op2) - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @fminnm_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) #0 { +define void @fminnm_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fminnm_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -480,14 +480,14 @@ define void @fminnm_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) ; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a - %op2 = load <32 x float>, <32 x float>* %b + %op1 = load <32 x float>, ptr %a + %op2 = load <32 x float>, ptr %b %res = call <32 x float> @llvm.minnum.v32f32(<32 x float> %op1, <32 x float> %op2) - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @fminnm_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0) #0 { +define void @fminnm_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fminnm_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -496,10 +496,10 @@ define void @fminnm_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0 ; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a - %op2 = load <64 x float>, <64 x float>* %b + %op1 = load <64 x float>, ptr %a + %op2 = load <64 x float>, ptr %b %res = call <64 x float> @llvm.minnum.v64f32(<64 x float> %op1, <64 x float> %op2) - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -523,7 +523,7 @@ define <2 x double> @fminnm_v2f64(<2 x double> %op1, <2 x double> %op2) vscale_r ret <2 x double> %res } -define void @fminnm_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @fminnm_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fminnm_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -532,14 +532,14 @@ define void @fminnm_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) ; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a - %op2 = load <4 x double>, <4 x double>* %b + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b %res = call <4 x double> @llvm.minnum.v4f64(<4 x double> %op1, <4 x double> %op2) - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @fminnm_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { +define void @fminnm_v8f64(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: fminnm_v8f64: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: mov x8, #4 @@ -562,14 +562,14 @@ define void @fminnm_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: fminnm z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a - %op2 = load <8 x double>, <8 x double>* %b + %op1 = load <8 x double>, ptr %a + %op2 = load <8 x double>, ptr %b %res = call <8 x double> @llvm.minnum.v8f64(<8 x double> %op1, <8 x double> %op2) - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @fminnm_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @fminnm_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fminnm_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -578,14 +578,14 @@ define void @fminnm_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8, ; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a - %op2 = load <16 x double>, <16 x double>* %b + %op1 = load <16 x double>, ptr %a + %op2 = load <16 x double>, ptr %b %res = call <16 x double> @llvm.minnum.v16f64(<16 x double> %op1, <16 x double> %op2) - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @fminnm_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @fminnm_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fminnm_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -594,10 +594,10 @@ define void @fminnm_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16 ; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a - %op2 = load <32 x double>, <32 x double>* %b + %op1 = load <32 x double>, ptr %a + %op2 = load <32 x double>, ptr %b %res = call <32 x double> @llvm.minnum.v32f64(<32 x double> %op1, <32 x double> %op2) - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } @@ -625,7 +625,7 @@ define <8 x half> @fmax_v8f16(<8 x half> %op1, <8 x half> %op2) vscale_range(2,0 ret <8 x half> %res } -define void @fmax_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 { +define void @fmax_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fmax_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -634,14 +634,14 @@ define void @fmax_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: fmax z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %res = call <16 x half> @llvm.maximum.v16f16(<16 x half> %op1, <16 x half> %op2) - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @fmax_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { +define void @fmax_v32f16(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: fmax_v32f16: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: mov x8, #16 @@ -664,14 +664,14 @@ define void @fmax_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { ; VBITS_GE_512-NEXT: fmax z0.h, p0/m, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a - %op2 = load <32 x half>, <32 x half>* %b + %op1 = load <32 x half>, ptr %a + %op2 = load <32 x half>, ptr %b %res = call <32 x half> @llvm.maximum.v32f16(<32 x half> %op1, <32 x half> %op2) - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @fmax_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) #0 { +define void @fmax_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fmax_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -680,14 +680,14 @@ define void @fmax_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) #0 ; CHECK-NEXT: fmax z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a - %op2 = load <64 x half>, <64 x half>* %b + %op1 = load <64 x half>, ptr %a + %op2 = load <64 x half>, ptr %b %res = call <64 x half> @llvm.maximum.v64f16(<64 x half> %op1, <64 x half> %op2) - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @fmax_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16,0) #0 { +define void @fmax_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fmax_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -696,10 +696,10 @@ define void @fmax_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16,0) ; CHECK-NEXT: fmax z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x half>, <128 x half>* %a - %op2 = load <128 x half>, <128 x half>* %b + %op1 = load <128 x half>, ptr %a + %op2 = load <128 x half>, ptr %b %res = call <128 x half> @llvm.maximum.v128f16(<128 x half> %op1, <128 x half> %op2) - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -723,7 +723,7 @@ define <4 x float> @fmax_v4f32(<4 x float> %op1, <4 x float> %op2) vscale_range( ret <4 x float> %res } -define void @fmax_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 { +define void @fmax_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fmax_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -732,14 +732,14 @@ define void @fmax_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: fmax z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a - %op2 = load <8 x float>, <8 x float>* %b + %op1 = load <8 x float>, ptr %a + %op2 = load <8 x float>, ptr %b %res = call <8 x float> @llvm.maximum.v8f32(<8 x float> %op1, <8 x float> %op2) - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @fmax_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { +define void @fmax_v16f32(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: fmax_v16f32: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: mov x8, #8 @@ -762,14 +762,14 @@ define void @fmax_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { ; VBITS_GE_512-NEXT: fmax z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a - %op2 = load <16 x float>, <16 x float>* %b + %op1 = load <16 x float>, ptr %a + %op2 = load <16 x float>, ptr %b %res = call <16 x float> @llvm.maximum.v16f32(<16 x float> %op1, <16 x float> %op2) - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @fmax_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) #0 { +define void @fmax_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fmax_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -778,14 +778,14 @@ define void @fmax_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) # ; CHECK-NEXT: fmax z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a - %op2 = load <32 x float>, <32 x float>* %b + %op1 = load <32 x float>, ptr %a + %op2 = load <32 x float>, ptr %b %res = call <32 x float> @llvm.maximum.v32f32(<32 x float> %op1, <32 x float> %op2) - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @fmax_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0) #0 { +define void @fmax_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fmax_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -794,10 +794,10 @@ define void @fmax_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0) ; CHECK-NEXT: fmax z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a - %op2 = load <64 x float>, <64 x float>* %b + %op1 = load <64 x float>, ptr %a + %op2 = load <64 x float>, ptr %b %res = call <64 x float> @llvm.maximum.v64f32(<64 x float> %op1, <64 x float> %op2) - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -821,7 +821,7 @@ define <2 x double> @fmax_v2f64(<2 x double> %op1, <2 x double> %op2) vscale_ran ret <2 x double> %res } -define void @fmax_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @fmax_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fmax_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -830,14 +830,14 @@ define void @fmax_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: fmax z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a - %op2 = load <4 x double>, <4 x double>* %b + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b %res = call <4 x double> @llvm.maximum.v4f64(<4 x double> %op1, <4 x double> %op2) - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @fmax_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { +define void @fmax_v8f64(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: fmax_v8f64: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: mov x8, #4 @@ -860,14 +860,14 @@ define void @fmax_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: fmax z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a - %op2 = load <8 x double>, <8 x double>* %b + %op1 = load <8 x double>, ptr %a + %op2 = load <8 x double>, ptr %b %res = call <8 x double> @llvm.maximum.v8f64(<8 x double> %op1, <8 x double> %op2) - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @fmax_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @fmax_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fmax_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -876,14 +876,14 @@ define void @fmax_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8,0) ; CHECK-NEXT: fmax z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a - %op2 = load <16 x double>, <16 x double>* %b + %op1 = load <16 x double>, ptr %a + %op2 = load <16 x double>, ptr %b %res = call <16 x double> @llvm.maximum.v16f64(<16 x double> %op1, <16 x double> %op2) - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @fmax_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @fmax_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fmax_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -892,10 +892,10 @@ define void @fmax_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16,0 ; CHECK-NEXT: fmax z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a - %op2 = load <32 x double>, <32 x double>* %b + %op1 = load <32 x double>, ptr %a + %op2 = load <32 x double>, ptr %b %res = call <32 x double> @llvm.maximum.v32f64(<32 x double> %op1, <32 x double> %op2) - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } @@ -923,7 +923,7 @@ define <8 x half> @fmin_v8f16(<8 x half> %op1, <8 x half> %op2) vscale_range(2,0 ret <8 x half> %res } -define void @fmin_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 { +define void @fmin_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fmin_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -932,14 +932,14 @@ define void @fmin_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: fmin z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %res = call <16 x half> @llvm.minimum.v16f16(<16 x half> %op1, <16 x half> %op2) - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @fmin_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { +define void @fmin_v32f16(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: fmin_v32f16: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: mov x8, #16 @@ -962,14 +962,14 @@ define void @fmin_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { ; VBITS_GE_512-NEXT: fmin z0.h, p0/m, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a - %op2 = load <32 x half>, <32 x half>* %b + %op1 = load <32 x half>, ptr %a + %op2 = load <32 x half>, ptr %b %res = call <32 x half> @llvm.minimum.v32f16(<32 x half> %op1, <32 x half> %op2) - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @fmin_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) #0 { +define void @fmin_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fmin_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -978,14 +978,14 @@ define void @fmin_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) #0 ; CHECK-NEXT: fmin z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a - %op2 = load <64 x half>, <64 x half>* %b + %op1 = load <64 x half>, ptr %a + %op2 = load <64 x half>, ptr %b %res = call <64 x half> @llvm.minimum.v64f16(<64 x half> %op1, <64 x half> %op2) - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @fmin_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16,0) #0 { +define void @fmin_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fmin_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -994,10 +994,10 @@ define void @fmin_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16,0) ; CHECK-NEXT: fmin z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x half>, <128 x half>* %a - %op2 = load <128 x half>, <128 x half>* %b + %op1 = load <128 x half>, ptr %a + %op2 = load <128 x half>, ptr %b %res = call <128 x half> @llvm.minimum.v128f16(<128 x half> %op1, <128 x half> %op2) - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -1021,7 +1021,7 @@ define <4 x float> @fmin_v4f32(<4 x float> %op1, <4 x float> %op2) vscale_range( ret <4 x float> %res } -define void @fmin_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 { +define void @fmin_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fmin_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1030,14 +1030,14 @@ define void @fmin_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: fmin z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a - %op2 = load <8 x float>, <8 x float>* %b + %op1 = load <8 x float>, ptr %a + %op2 = load <8 x float>, ptr %b %res = call <8 x float> @llvm.minimum.v8f32(<8 x float> %op1, <8 x float> %op2) - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @fmin_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { +define void @fmin_v16f32(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: fmin_v16f32: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: mov x8, #8 @@ -1060,14 +1060,14 @@ define void @fmin_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { ; VBITS_GE_512-NEXT: fmin z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a - %op2 = load <16 x float>, <16 x float>* %b + %op1 = load <16 x float>, ptr %a + %op2 = load <16 x float>, ptr %b %res = call <16 x float> @llvm.minimum.v16f32(<16 x float> %op1, <16 x float> %op2) - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @fmin_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) #0 { +define void @fmin_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fmin_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1076,14 +1076,14 @@ define void @fmin_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) # ; CHECK-NEXT: fmin z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a - %op2 = load <32 x float>, <32 x float>* %b + %op1 = load <32 x float>, ptr %a + %op2 = load <32 x float>, ptr %b %res = call <32 x float> @llvm.minimum.v32f32(<32 x float> %op1, <32 x float> %op2) - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @fmin_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0) #0 { +define void @fmin_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fmin_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1092,10 +1092,10 @@ define void @fmin_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0) ; CHECK-NEXT: fmin z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a - %op2 = load <64 x float>, <64 x float>* %b + %op1 = load <64 x float>, ptr %a + %op2 = load <64 x float>, ptr %b %res = call <64 x float> @llvm.minimum.v64f32(<64 x float> %op1, <64 x float> %op2) - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -1119,7 +1119,7 @@ define <2 x double> @fmin_v2f64(<2 x double> %op1, <2 x double> %op2) vscale_ran ret <2 x double> %res } -define void @fmin_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @fmin_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fmin_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1128,14 +1128,14 @@ define void @fmin_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: fmin z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a - %op2 = load <4 x double>, <4 x double>* %b + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b %res = call <4 x double> @llvm.minimum.v4f64(<4 x double> %op1, <4 x double> %op2) - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @fmin_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { +define void @fmin_v8f64(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: fmin_v8f64: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: mov x8, #4 @@ -1158,14 +1158,14 @@ define void @fmin_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: fmin z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a - %op2 = load <8 x double>, <8 x double>* %b + %op1 = load <8 x double>, ptr %a + %op2 = load <8 x double>, ptr %b %res = call <8 x double> @llvm.minimum.v8f64(<8 x double> %op1, <8 x double> %op2) - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @fmin_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @fmin_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fmin_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1174,14 +1174,14 @@ define void @fmin_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8,0) ; CHECK-NEXT: fmin z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a - %op2 = load <16 x double>, <16 x double>* %b + %op1 = load <16 x double>, ptr %a + %op2 = load <16 x double>, ptr %b %res = call <16 x double> @llvm.minimum.v16f64(<16 x double> %op1, <16 x double> %op2) - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @fmin_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @fmin_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fmin_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1190,10 +1190,10 @@ define void @fmin_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16,0 ; CHECK-NEXT: fmin z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a - %op2 = load <32 x double>, <32 x double>* %b + %op1 = load <32 x double>, ptr %a + %op2 = load <32 x double>, ptr %b %res = call <32 x double> @llvm.minimum.v32f64(<32 x double> %op1, <32 x double> %op2) - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll index 455639e..39784af 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll @@ -37,7 +37,7 @@ define half @fadda_v8f16(half %start, <8 x half> %a) vscale_range(1,0) #0 { ret half %res } -define half @fadda_v16f16(half %start, <16 x half>* %a) vscale_range(2,0) #0 { +define half @fadda_v16f16(half %start, ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fadda_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -46,12 +46,12 @@ define half @fadda_v16f16(half %start, <16 x half>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: fadda h0, p0, h0, z1.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret - %op = load <16 x half>, <16 x half>* %a + %op = load <16 x half>, ptr %a %res = call half @llvm.vector.reduce.fadd.v16f16(half %start, <16 x half> %op) ret half %res } -define half @fadda_v32f16(half %start, <32 x half>* %a) #0 { +define half @fadda_v32f16(half %start, ptr %a) #0 { ; VBITS_GE_256-LABEL: fadda_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -72,12 +72,12 @@ define half @fadda_v32f16(half %start, <32 x half>* %a) #0 { ; VBITS_GE_512-NEXT: fadda h0, p0, h0, z1.h ; VBITS_GE_512-NEXT: // kill: def $h0 killed $h0 killed $z0 ; VBITS_GE_512-NEXT: ret - %op = load <32 x half>, <32 x half>* %a + %op = load <32 x half>, ptr %a %res = call half @llvm.vector.reduce.fadd.v32f16(half %start, <32 x half> %op) ret half %res } -define half @fadda_v64f16(half %start, <64 x half>* %a) vscale_range(8,0) #0 { +define half @fadda_v64f16(half %start, ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: fadda_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -86,12 +86,12 @@ define half @fadda_v64f16(half %start, <64 x half>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fadda h0, p0, h0, z1.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret - %op = load <64 x half>, <64 x half>* %a + %op = load <64 x half>, ptr %a %res = call half @llvm.vector.reduce.fadd.v64f16(half %start, <64 x half> %op) ret half %res } -define half @fadda_v128f16(half %start, <128 x half>* %a) vscale_range(16,0) #0 { +define half @fadda_v128f16(half %start, ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: fadda_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -100,7 +100,7 @@ define half @fadda_v128f16(half %start, <128 x half>* %a) vscale_range(16,0) #0 ; CHECK-NEXT: fadda h0, p0, h0, z1.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret - %op = load <128 x half>, <128 x half>* %a + %op = load <128 x half>, ptr %a %res = call half @llvm.vector.reduce.fadd.v128f16(half %start, <128 x half> %op) ret half %res } @@ -133,7 +133,7 @@ define float @fadda_v4f32(float %start, <4 x float> %a) vscale_range(1,0) #0 { ret float %res } -define float @fadda_v8f32(float %start, <8 x float>* %a) vscale_range(2,0) #0 { +define float @fadda_v8f32(float %start, ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fadda_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -142,12 +142,12 @@ define float @fadda_v8f32(float %start, <8 x float>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: fadda s0, p0, s0, z1.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret - %op = load <8 x float>, <8 x float>* %a + %op = load <8 x float>, ptr %a %res = call float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %op) ret float %res } -define float @fadda_v16f32(float %start, <16 x float>* %a) #0 { +define float @fadda_v16f32(float %start, ptr %a) #0 { ; VBITS_GE_256-LABEL: fadda_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -168,12 +168,12 @@ define float @fadda_v16f32(float %start, <16 x float>* %a) #0 { ; VBITS_GE_512-NEXT: fadda s0, p0, s0, z1.s ; VBITS_GE_512-NEXT: // kill: def $s0 killed $s0 killed $z0 ; VBITS_GE_512-NEXT: ret - %op = load <16 x float>, <16 x float>* %a + %op = load <16 x float>, ptr %a %res = call float @llvm.vector.reduce.fadd.v16f32(float %start, <16 x float> %op) ret float %res } -define float @fadda_v32f32(float %start, <32 x float>* %a) vscale_range(8,0) #0 { +define float @fadda_v32f32(float %start, ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: fadda_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -182,12 +182,12 @@ define float @fadda_v32f32(float %start, <32 x float>* %a) vscale_range(8,0) #0 ; CHECK-NEXT: fadda s0, p0, s0, z1.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret - %op = load <32 x float>, <32 x float>* %a + %op = load <32 x float>, ptr %a %res = call float @llvm.vector.reduce.fadd.v32f32(float %start, <32 x float> %op) ret float %res } -define float @fadda_v64f32(float %start, <64 x float>* %a) vscale_range(16,0) #0 { +define float @fadda_v64f32(float %start, ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: fadda_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -196,7 +196,7 @@ define float @fadda_v64f32(float %start, <64 x float>* %a) vscale_range(16,0) #0 ; CHECK-NEXT: fadda s0, p0, s0, z1.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret - %op = load <64 x float>, <64 x float>* %a + %op = load <64 x float>, ptr %a %res = call float @llvm.vector.reduce.fadd.v64f32(float %start, <64 x float> %op) ret float %res } @@ -225,7 +225,7 @@ define double @fadda_v2f64(double %start, <2 x double> %a) vscale_range(1,0) #0 ret double %res } -define double @fadda_v4f64(double %start, <4 x double>* %a) vscale_range(2,0) #0 { +define double @fadda_v4f64(double %start, ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fadda_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -234,12 +234,12 @@ define double @fadda_v4f64(double %start, <4 x double>* %a) vscale_range(2,0) #0 ; CHECK-NEXT: fadda d0, p0, d0, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %op = load <4 x double>, <4 x double>* %a + %op = load <4 x double>, ptr %a %res = call double @llvm.vector.reduce.fadd.v4f64(double %start, <4 x double> %op) ret double %res } -define double @fadda_v8f64(double %start, <8 x double>* %a) #0 { +define double @fadda_v8f64(double %start, ptr %a) #0 { ; VBITS_GE_256-LABEL: fadda_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -260,12 +260,12 @@ define double @fadda_v8f64(double %start, <8 x double>* %a) #0 { ; VBITS_GE_512-NEXT: fadda d0, p0, d0, z1.d ; VBITS_GE_512-NEXT: // kill: def $d0 killed $d0 killed $z0 ; VBITS_GE_512-NEXT: ret - %op = load <8 x double>, <8 x double>* %a + %op = load <8 x double>, ptr %a %res = call double @llvm.vector.reduce.fadd.v8f64(double %start, <8 x double> %op) ret double %res } -define double @fadda_v16f64(double %start, <16 x double>* %a) vscale_range(8,0) #0 { +define double @fadda_v16f64(double %start, ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: fadda_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -274,12 +274,12 @@ define double @fadda_v16f64(double %start, <16 x double>* %a) vscale_range(8,0) ; CHECK-NEXT: fadda d0, p0, d0, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %op = load <16 x double>, <16 x double>* %a + %op = load <16 x double>, ptr %a %res = call double @llvm.vector.reduce.fadd.v16f64(double %start, <16 x double> %op) ret double %res } -define double @fadda_v32f64(double %start, <32 x double>* %a) vscale_range(16,0) #0 { +define double @fadda_v32f64(double %start, ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: fadda_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -288,7 +288,7 @@ define double @fadda_v32f64(double %start, <32 x double>* %a) vscale_range(16,0) ; CHECK-NEXT: fadda d0, p0, d0, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %op = load <32 x double>, <32 x double>* %a + %op = load <32 x double>, ptr %a %res = call double @llvm.vector.reduce.fadd.v32f64(double %start, <32 x double> %op) ret double %res } @@ -323,7 +323,7 @@ define half @faddv_v8f16(half %start, <8 x half> %a) vscale_range(2,0) #0 { ret half %res } -define half @faddv_v16f16(half %start, <16 x half>* %a) vscale_range(2,0) #0 { +define half @faddv_v16f16(half %start, ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: faddv_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -331,12 +331,12 @@ define half @faddv_v16f16(half %start, <16 x half>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: faddv h1, p0, z1.h ; CHECK-NEXT: fadd h0, h0, h1 ; CHECK-NEXT: ret - %op = load <16 x half>, <16 x half>* %a + %op = load <16 x half>, ptr %a %res = call fast half @llvm.vector.reduce.fadd.v16f16(half %start, <16 x half> %op) ret half %res } -define half @faddv_v32f16(half %start, <32 x half>* %a) #0 { +define half @faddv_v32f16(half %start, ptr %a) #0 { ; VBITS_GE_256-LABEL: faddv_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -355,12 +355,12 @@ define half @faddv_v32f16(half %start, <32 x half>* %a) #0 { ; VBITS_GE_512-NEXT: faddv h1, p0, z1.h ; VBITS_GE_512-NEXT: fadd h0, h0, h1 ; VBITS_GE_512-NEXT: ret - %op = load <32 x half>, <32 x half>* %a + %op = load <32 x half>, ptr %a %res = call fast half @llvm.vector.reduce.fadd.v32f16(half %start, <32 x half> %op) ret half %res } -define half @faddv_v64f16(half %start, <64 x half>* %a) vscale_range(8,0) #0 { +define half @faddv_v64f16(half %start, ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: faddv_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -368,12 +368,12 @@ define half @faddv_v64f16(half %start, <64 x half>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: faddv h1, p0, z1.h ; CHECK-NEXT: fadd h0, h0, h1 ; CHECK-NEXT: ret - %op = load <64 x half>, <64 x half>* %a + %op = load <64 x half>, ptr %a %res = call fast half @llvm.vector.reduce.fadd.v64f16(half %start, <64 x half> %op) ret half %res } -define half @faddv_v128f16(half %start, <128 x half>* %a) vscale_range(16,0) #0 { +define half @faddv_v128f16(half %start, ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: faddv_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -381,7 +381,7 @@ define half @faddv_v128f16(half %start, <128 x half>* %a) vscale_range(16,0) #0 ; CHECK-NEXT: faddv h1, p0, z1.h ; CHECK-NEXT: fadd h0, h0, h1 ; CHECK-NEXT: ret - %op = load <128 x half>, <128 x half>* %a + %op = load <128 x half>, ptr %a %res = call fast half @llvm.vector.reduce.fadd.v128f16(half %start, <128 x half> %op) ret half %res } @@ -410,7 +410,7 @@ define float @faddv_v4f32(float %start, <4 x float> %a) vscale_range(2,0) #0 { ret float %res } -define float @faddv_v8f32(float %start, <8 x float>* %a) vscale_range(2,0) #0 { +define float @faddv_v8f32(float %start, ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: faddv_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -418,12 +418,12 @@ define float @faddv_v8f32(float %start, <8 x float>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: faddv s1, p0, z1.s ; CHECK-NEXT: fadd s0, s0, s1 ; CHECK-NEXT: ret - %op = load <8 x float>, <8 x float>* %a + %op = load <8 x float>, ptr %a %res = call fast float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %op) ret float %res } -define float @faddv_v16f32(float %start, <16 x float>* %a) #0 { +define float @faddv_v16f32(float %start, ptr %a) #0 { ; VBITS_GE_256-LABEL: faddv_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -442,12 +442,12 @@ define float @faddv_v16f32(float %start, <16 x float>* %a) #0 { ; VBITS_GE_512-NEXT: faddv s1, p0, z1.s ; VBITS_GE_512-NEXT: fadd s0, s0, s1 ; VBITS_GE_512-NEXT: ret - %op = load <16 x float>, <16 x float>* %a + %op = load <16 x float>, ptr %a %res = call fast float @llvm.vector.reduce.fadd.v16f32(float %start, <16 x float> %op) ret float %res } -define float @faddv_v32f32(float %start, <32 x float>* %a) vscale_range(8,0) #0 { +define float @faddv_v32f32(float %start, ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: faddv_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -455,12 +455,12 @@ define float @faddv_v32f32(float %start, <32 x float>* %a) vscale_range(8,0) #0 ; CHECK-NEXT: faddv s1, p0, z1.s ; CHECK-NEXT: fadd s0, s0, s1 ; CHECK-NEXT: ret - %op = load <32 x float>, <32 x float>* %a + %op = load <32 x float>, ptr %a %res = call fast float @llvm.vector.reduce.fadd.v32f32(float %start, <32 x float> %op) ret float %res } -define float @faddv_v64f32(float %start, <64 x float>* %a) vscale_range(16,0) #0 { +define float @faddv_v64f32(float %start, ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: faddv_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -468,7 +468,7 @@ define float @faddv_v64f32(float %start, <64 x float>* %a) vscale_range(16,0) #0 ; CHECK-NEXT: faddv s1, p0, z1.s ; CHECK-NEXT: fadd s0, s0, s1 ; CHECK-NEXT: ret - %op = load <64 x float>, <64 x float>* %a + %op = load <64 x float>, ptr %a %res = call fast float @llvm.vector.reduce.fadd.v64f32(float %start, <64 x float> %op) ret float %res } @@ -494,7 +494,7 @@ define double @faddv_v2f64(double %start, <2 x double> %a) vscale_range(2,0) #0 ret double %res } -define double @faddv_v4f64(double %start, <4 x double>* %a) vscale_range(2,0) #0 { +define double @faddv_v4f64(double %start, ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: faddv_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -502,12 +502,12 @@ define double @faddv_v4f64(double %start, <4 x double>* %a) vscale_range(2,0) #0 ; CHECK-NEXT: faddv d1, p0, z1.d ; CHECK-NEXT: fadd d0, d0, d1 ; CHECK-NEXT: ret - %op = load <4 x double>, <4 x double>* %a + %op = load <4 x double>, ptr %a %res = call fast double @llvm.vector.reduce.fadd.v4f64(double %start, <4 x double> %op) ret double %res } -define double @faddv_v8f64(double %start, <8 x double>* %a) #0 { +define double @faddv_v8f64(double %start, ptr %a) #0 { ; VBITS_GE_256-LABEL: faddv_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -526,12 +526,12 @@ define double @faddv_v8f64(double %start, <8 x double>* %a) #0 { ; VBITS_GE_512-NEXT: faddv d1, p0, z1.d ; VBITS_GE_512-NEXT: fadd d0, d0, d1 ; VBITS_GE_512-NEXT: ret - %op = load <8 x double>, <8 x double>* %a + %op = load <8 x double>, ptr %a %res = call fast double @llvm.vector.reduce.fadd.v8f64(double %start, <8 x double> %op) ret double %res } -define double @faddv_v16f64(double %start, <16 x double>* %a) vscale_range(8,0) #0 { +define double @faddv_v16f64(double %start, ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: faddv_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -539,12 +539,12 @@ define double @faddv_v16f64(double %start, <16 x double>* %a) vscale_range(8,0) ; CHECK-NEXT: faddv d1, p0, z1.d ; CHECK-NEXT: fadd d0, d0, d1 ; CHECK-NEXT: ret - %op = load <16 x double>, <16 x double>* %a + %op = load <16 x double>, ptr %a %res = call fast double @llvm.vector.reduce.fadd.v16f64(double %start, <16 x double> %op) ret double %res } -define double @faddv_v32f64(double %start, <32 x double>* %a) vscale_range(16,0) #0 { +define double @faddv_v32f64(double %start, ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: faddv_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -552,7 +552,7 @@ define double @faddv_v32f64(double %start, <32 x double>* %a) vscale_range(16,0) ; CHECK-NEXT: faddv d1, p0, z1.d ; CHECK-NEXT: fadd d0, d0, d1 ; CHECK-NEXT: ret - %op = load <32 x double>, <32 x double>* %a + %op = load <32 x double>, ptr %a %res = call fast double @llvm.vector.reduce.fadd.v32f64(double %start, <32 x double> %op) ret double %res } @@ -581,7 +581,7 @@ define half @fmaxv_v8f16(<8 x half> %a) vscale_range(2,0) #0 { ret half %res } -define half @fmaxv_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { +define half @fmaxv_v16f16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fmaxv_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -589,12 +589,12 @@ define half @fmaxv_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: fmaxnmv h0, p0, z0.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret - %op = load <16 x half>, <16 x half>* %a + %op = load <16 x half>, ptr %a %res = call half @llvm.vector.reduce.fmax.v16f16(<16 x half> %op) ret half %res } -define half @fmaxv_v32f16(<32 x half>* %a) #0 { +define half @fmaxv_v32f16(ptr %a) #0 { ; VBITS_GE_256-LABEL: fmaxv_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -613,12 +613,12 @@ define half @fmaxv_v32f16(<32 x half>* %a) #0 { ; VBITS_GE_512-NEXT: fmaxnmv h0, p0, z0.h ; VBITS_GE_512-NEXT: // kill: def $h0 killed $h0 killed $z0 ; VBITS_GE_512-NEXT: ret - %op = load <32 x half>, <32 x half>* %a + %op = load <32 x half>, ptr %a %res = call half @llvm.vector.reduce.fmax.v32f16(<32 x half> %op) ret half %res } -define half @fmaxv_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { +define half @fmaxv_v64f16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: fmaxv_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -626,12 +626,12 @@ define half @fmaxv_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fmaxnmv h0, p0, z0.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret - %op = load <64 x half>, <64 x half>* %a + %op = load <64 x half>, ptr %a %res = call half @llvm.vector.reduce.fmax.v64f16(<64 x half> %op) ret half %res } -define half @fmaxv_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { +define half @fmaxv_v128f16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: fmaxv_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -639,7 +639,7 @@ define half @fmaxv_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: fmaxnmv h0, p0, z0.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret - %op = load <128 x half>, <128 x half>* %a + %op = load <128 x half>, ptr %a %res = call half @llvm.vector.reduce.fmax.v128f16(<128 x half> %op) ret half %res } @@ -664,7 +664,7 @@ define float @fmaxv_v4f32(<4 x float> %a) vscale_range(2,0) #0 { ret float %res } -define float @fmaxv_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { +define float @fmaxv_v8f32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fmaxv_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -672,12 +672,12 @@ define float @fmaxv_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: fmaxnmv s0, p0, z0.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret - %op = load <8 x float>, <8 x float>* %a + %op = load <8 x float>, ptr %a %res = call float @llvm.vector.reduce.fmax.v8f32(<8 x float> %op) ret float %res } -define float @fmaxv_v16f32(<16 x float>* %a) #0 { +define float @fmaxv_v16f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: fmaxv_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -696,12 +696,12 @@ define float @fmaxv_v16f32(<16 x float>* %a) #0 { ; VBITS_GE_512-NEXT: fmaxnmv s0, p0, z0.s ; VBITS_GE_512-NEXT: // kill: def $s0 killed $s0 killed $z0 ; VBITS_GE_512-NEXT: ret - %op = load <16 x float>, <16 x float>* %a + %op = load <16 x float>, ptr %a %res = call float @llvm.vector.reduce.fmax.v16f32(<16 x float> %op) ret float %res } -define float @fmaxv_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { +define float @fmaxv_v32f32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: fmaxv_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -709,12 +709,12 @@ define float @fmaxv_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fmaxnmv s0, p0, z0.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret - %op = load <32 x float>, <32 x float>* %a + %op = load <32 x float>, ptr %a %res = call float @llvm.vector.reduce.fmax.v32f32(<32 x float> %op) ret float %res } -define float @fmaxv_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { +define float @fmaxv_v64f32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: fmaxv_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -722,7 +722,7 @@ define float @fmaxv_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: fmaxnmv s0, p0, z0.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret - %op = load <64 x float>, <64 x float>* %a + %op = load <64 x float>, ptr %a %res = call float @llvm.vector.reduce.fmax.v64f32(<64 x float> %op) ret float %res } @@ -746,7 +746,7 @@ define double @fmaxv_v2f64(<2 x double> %a) vscale_range(2,0) #0 { ret double %res } -define double @fmaxv_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { +define double @fmaxv_v4f64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fmaxv_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -754,12 +754,12 @@ define double @fmaxv_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: fmaxnmv d0, p0, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %op = load <4 x double>, <4 x double>* %a + %op = load <4 x double>, ptr %a %res = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %op) ret double %res } -define double @fmaxv_v8f64(<8 x double>* %a) #0 { +define double @fmaxv_v8f64(ptr %a) #0 { ; VBITS_GE_256-LABEL: fmaxv_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -778,12 +778,12 @@ define double @fmaxv_v8f64(<8 x double>* %a) #0 { ; VBITS_GE_512-NEXT: fmaxnmv d0, p0, z0.d ; VBITS_GE_512-NEXT: // kill: def $d0 killed $d0 killed $z0 ; VBITS_GE_512-NEXT: ret - %op = load <8 x double>, <8 x double>* %a + %op = load <8 x double>, ptr %a %res = call double @llvm.vector.reduce.fmax.v8f64(<8 x double> %op) ret double %res } -define double @fmaxv_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { +define double @fmaxv_v16f64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: fmaxv_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -791,12 +791,12 @@ define double @fmaxv_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fmaxnmv d0, p0, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %op = load <16 x double>, <16 x double>* %a + %op = load <16 x double>, ptr %a %res = call double @llvm.vector.reduce.fmax.v16f64(<16 x double> %op) ret double %res } -define double @fmaxv_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { +define double @fmaxv_v32f64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: fmaxv_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -804,7 +804,7 @@ define double @fmaxv_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: fmaxnmv d0, p0, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %op = load <32 x double>, <32 x double>* %a + %op = load <32 x double>, ptr %a %res = call double @llvm.vector.reduce.fmax.v32f64(<32 x double> %op) ret double %res } @@ -833,7 +833,7 @@ define half @fminv_v8f16(<8 x half> %a) vscale_range(2,0) #0 { ret half %res } -define half @fminv_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { +define half @fminv_v16f16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fminv_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -841,12 +841,12 @@ define half @fminv_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: fminnmv h0, p0, z0.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret - %op = load <16 x half>, <16 x half>* %a + %op = load <16 x half>, ptr %a %res = call half @llvm.vector.reduce.fmin.v16f16(<16 x half> %op) ret half %res } -define half @fminv_v32f16(<32 x half>* %a) #0 { +define half @fminv_v32f16(ptr %a) #0 { ; VBITS_GE_256-LABEL: fminv_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -865,12 +865,12 @@ define half @fminv_v32f16(<32 x half>* %a) #0 { ; VBITS_GE_512-NEXT: fminnmv h0, p0, z0.h ; VBITS_GE_512-NEXT: // kill: def $h0 killed $h0 killed $z0 ; VBITS_GE_512-NEXT: ret - %op = load <32 x half>, <32 x half>* %a + %op = load <32 x half>, ptr %a %res = call half @llvm.vector.reduce.fmin.v32f16(<32 x half> %op) ret half %res } -define half @fminv_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { +define half @fminv_v64f16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: fminv_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -878,12 +878,12 @@ define half @fminv_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fminnmv h0, p0, z0.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret - %op = load <64 x half>, <64 x half>* %a + %op = load <64 x half>, ptr %a %res = call half @llvm.vector.reduce.fmin.v64f16(<64 x half> %op) ret half %res } -define half @fminv_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { +define half @fminv_v128f16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: fminv_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -891,7 +891,7 @@ define half @fminv_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: fminnmv h0, p0, z0.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret - %op = load <128 x half>, <128 x half>* %a + %op = load <128 x half>, ptr %a %res = call half @llvm.vector.reduce.fmin.v128f16(<128 x half> %op) ret half %res } @@ -916,7 +916,7 @@ define float @fminv_v4f32(<4 x float> %a) vscale_range(2,0) #0 { ret float %res } -define float @fminv_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { +define float @fminv_v8f32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fminv_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -924,12 +924,12 @@ define float @fminv_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: fminnmv s0, p0, z0.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret - %op = load <8 x float>, <8 x float>* %a + %op = load <8 x float>, ptr %a %res = call float @llvm.vector.reduce.fmin.v8f32(<8 x float> %op) ret float %res } -define float @fminv_v16f32(<16 x float>* %a) #0 { +define float @fminv_v16f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: fminv_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -948,12 +948,12 @@ define float @fminv_v16f32(<16 x float>* %a) #0 { ; VBITS_GE_512-NEXT: fminnmv s0, p0, z0.s ; VBITS_GE_512-NEXT: // kill: def $s0 killed $s0 killed $z0 ; VBITS_GE_512-NEXT: ret - %op = load <16 x float>, <16 x float>* %a + %op = load <16 x float>, ptr %a %res = call float @llvm.vector.reduce.fmin.v16f32(<16 x float> %op) ret float %res } -define float @fminv_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { +define float @fminv_v32f32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: fminv_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -961,12 +961,12 @@ define float @fminv_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fminnmv s0, p0, z0.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret - %op = load <32 x float>, <32 x float>* %a + %op = load <32 x float>, ptr %a %res = call float @llvm.vector.reduce.fmin.v32f32(<32 x float> %op) ret float %res } -define float @fminv_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { +define float @fminv_v64f32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: fminv_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -974,7 +974,7 @@ define float @fminv_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: fminnmv s0, p0, z0.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret - %op = load <64 x float>, <64 x float>* %a + %op = load <64 x float>, ptr %a %res = call float @llvm.vector.reduce.fmin.v64f32(<64 x float> %op) ret float %res } @@ -998,7 +998,7 @@ define double @fminv_v2f64(<2 x double> %a) vscale_range(2,0) #0 { ret double %res } -define double @fminv_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { +define double @fminv_v4f64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fminv_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1006,12 +1006,12 @@ define double @fminv_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: fminnmv d0, p0, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %op = load <4 x double>, <4 x double>* %a + %op = load <4 x double>, ptr %a %res = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %op) ret double %res } -define double @fminv_v8f64(<8 x double>* %a) #0 { +define double @fminv_v8f64(ptr %a) #0 { ; VBITS_GE_256-LABEL: fminv_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1030,12 +1030,12 @@ define double @fminv_v8f64(<8 x double>* %a) #0 { ; VBITS_GE_512-NEXT: fminnmv d0, p0, z0.d ; VBITS_GE_512-NEXT: // kill: def $d0 killed $d0 killed $z0 ; VBITS_GE_512-NEXT: ret - %op = load <8 x double>, <8 x double>* %a + %op = load <8 x double>, ptr %a %res = call double @llvm.vector.reduce.fmin.v8f64(<8 x double> %op) ret double %res } -define double @fminv_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { +define double @fminv_v16f64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: fminv_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1043,12 +1043,12 @@ define double @fminv_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fminnmv d0, p0, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %op = load <16 x double>, <16 x double>* %a + %op = load <16 x double>, ptr %a %res = call double @llvm.vector.reduce.fmin.v16f64(<16 x double> %op) ret double %res } -define double @fminv_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { +define double @fminv_v32f64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: fminv_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1056,7 +1056,7 @@ define double @fminv_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: fminnmv d0, p0, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %op = load <32 x double>, <32 x double>* %a + %op = load <32 x double>, ptr %a %res = call double @llvm.vector.reduce.fmin.v32f64(<32 x double> %op) ret double %res } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-rounding.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-rounding.ll index 0f5afa5..ac46e1d 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-rounding.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-rounding.ll @@ -29,7 +29,7 @@ define <8 x half> @frintp_v8f16(<8 x half> %op) vscale_range(2,0) #0 { ret <8 x half> %res } -define void @frintp_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { +define void @frintp_v16f16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frintp_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -37,13 +37,13 @@ define void @frintp_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frintp z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x half>, <16 x half>* %a + %op = load <16 x half>, ptr %a %res = call <16 x half> @llvm.ceil.v16f16(<16 x half> %op) - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @frintp_v32f16(<32 x half>* %a) #0 { +define void @frintp_v32f16(ptr %a) #0 { ; VBITS_GE_256-LABEL: frintp_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -63,13 +63,13 @@ define void @frintp_v32f16(<32 x half>* %a) #0 { ; VBITS_GE_512-NEXT: frintp z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <32 x half>, <32 x half>* %a + %op = load <32 x half>, ptr %a %res = call <32 x half> @llvm.ceil.v32f16(<32 x half> %op) - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @frintp_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { +define void @frintp_v64f16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frintp_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -77,13 +77,13 @@ define void @frintp_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frintp z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x half>, <64 x half>* %a + %op = load <64 x half>, ptr %a %res = call <64 x half> @llvm.ceil.v64f16(<64 x half> %op) - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @frintp_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { +define void @frintp_v128f16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frintp_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -91,9 +91,9 @@ define void @frintp_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frintp z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x half>, <128 x half>* %a + %op = load <128 x half>, ptr %a %res = call <128 x half> @llvm.ceil.v128f16(<128 x half> %op) - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -117,7 +117,7 @@ define <4 x float> @frintp_v4f32(<4 x float> %op) vscale_range(2,0) #0 { ret <4 x float> %res } -define void @frintp_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { +define void @frintp_v8f32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frintp_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -125,13 +125,13 @@ define void @frintp_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frintp z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <8 x float>, <8 x float>* %a + %op = load <8 x float>, ptr %a %res = call <8 x float> @llvm.ceil.v8f32(<8 x float> %op) - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @frintp_v16f32(<16 x float>* %a) #0 { +define void @frintp_v16f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: frintp_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -151,13 +151,13 @@ define void @frintp_v16f32(<16 x float>* %a) #0 { ; VBITS_GE_512-NEXT: frintp z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <16 x float>, <16 x float>* %a + %op = load <16 x float>, ptr %a %res = call <16 x float> @llvm.ceil.v16f32(<16 x float> %op) - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @frintp_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { +define void @frintp_v32f32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frintp_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -165,13 +165,13 @@ define void @frintp_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frintp z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x float>, <32 x float>* %a + %op = load <32 x float>, ptr %a %res = call <32 x float> @llvm.ceil.v32f32(<32 x float> %op) - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @frintp_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { +define void @frintp_v64f32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frintp_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -179,9 +179,9 @@ define void @frintp_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frintp z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x float>, <64 x float>* %a + %op = load <64 x float>, ptr %a %res = call <64 x float> @llvm.ceil.v64f32(<64 x float> %op) - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -205,7 +205,7 @@ define <2 x double> @frintp_v2f64(<2 x double> %op) vscale_range(2,0) #0 { ret <2 x double> %res } -define void @frintp_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { +define void @frintp_v4f64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frintp_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -213,13 +213,13 @@ define void @frintp_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frintp z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <4 x double>, <4 x double>* %a + %op = load <4 x double>, ptr %a %res = call <4 x double> @llvm.ceil.v4f64(<4 x double> %op) - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @frintp_v8f64(<8 x double>* %a) #0 { +define void @frintp_v8f64(ptr %a) #0 { ; VBITS_GE_256-LABEL: frintp_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -239,13 +239,13 @@ define void @frintp_v8f64(<8 x double>* %a) #0 { ; VBITS_GE_512-NEXT: frintp z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <8 x double>, <8 x double>* %a + %op = load <8 x double>, ptr %a %res = call <8 x double> @llvm.ceil.v8f64(<8 x double> %op) - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @frintp_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { +define void @frintp_v16f64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frintp_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -253,13 +253,13 @@ define void @frintp_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frintp z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x double>, <16 x double>* %a + %op = load <16 x double>, ptr %a %res = call <16 x double> @llvm.ceil.v16f64(<16 x double> %op) - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @frintp_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { +define void @frintp_v32f64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frintp_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -267,9 +267,9 @@ define void @frintp_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frintp z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x double>, <32 x double>* %a + %op = load <32 x double>, ptr %a %res = call <32 x double> @llvm.ceil.v32f64(<32 x double> %op) - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } @@ -297,7 +297,7 @@ define <8 x half> @frintm_v8f16(<8 x half> %op) vscale_range(2,0) #0 { ret <8 x half> %res } -define void @frintm_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { +define void @frintm_v16f16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frintm_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -305,13 +305,13 @@ define void @frintm_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frintm z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x half>, <16 x half>* %a + %op = load <16 x half>, ptr %a %res = call <16 x half> @llvm.floor.v16f16(<16 x half> %op) - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @frintm_v32f16(<32 x half>* %a) #0 { +define void @frintm_v32f16(ptr %a) #0 { ; VBITS_GE_256-LABEL: frintm_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -331,13 +331,13 @@ define void @frintm_v32f16(<32 x half>* %a) #0 { ; VBITS_GE_512-NEXT: frintm z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <32 x half>, <32 x half>* %a + %op = load <32 x half>, ptr %a %res = call <32 x half> @llvm.floor.v32f16(<32 x half> %op) - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @frintm_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { +define void @frintm_v64f16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frintm_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -345,13 +345,13 @@ define void @frintm_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frintm z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x half>, <64 x half>* %a + %op = load <64 x half>, ptr %a %res = call <64 x half> @llvm.floor.v64f16(<64 x half> %op) - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @frintm_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { +define void @frintm_v128f16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frintm_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -359,9 +359,9 @@ define void @frintm_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frintm z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x half>, <128 x half>* %a + %op = load <128 x half>, ptr %a %res = call <128 x half> @llvm.floor.v128f16(<128 x half> %op) - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -385,7 +385,7 @@ define <4 x float> @frintm_v4f32(<4 x float> %op) vscale_range(2,0) #0 { ret <4 x float> %res } -define void @frintm_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { +define void @frintm_v8f32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frintm_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -393,13 +393,13 @@ define void @frintm_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frintm z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <8 x float>, <8 x float>* %a + %op = load <8 x float>, ptr %a %res = call <8 x float> @llvm.floor.v8f32(<8 x float> %op) - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @frintm_v16f32(<16 x float>* %a) #0 { +define void @frintm_v16f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: frintm_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -419,13 +419,13 @@ define void @frintm_v16f32(<16 x float>* %a) #0 { ; VBITS_GE_512-NEXT: frintm z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <16 x float>, <16 x float>* %a + %op = load <16 x float>, ptr %a %res = call <16 x float> @llvm.floor.v16f32(<16 x float> %op) - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @frintm_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { +define void @frintm_v32f32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frintm_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -433,13 +433,13 @@ define void @frintm_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frintm z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x float>, <32 x float>* %a + %op = load <32 x float>, ptr %a %res = call <32 x float> @llvm.floor.v32f32(<32 x float> %op) - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @frintm_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { +define void @frintm_v64f32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frintm_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -447,9 +447,9 @@ define void @frintm_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frintm z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x float>, <64 x float>* %a + %op = load <64 x float>, ptr %a %res = call <64 x float> @llvm.floor.v64f32(<64 x float> %op) - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -473,7 +473,7 @@ define <2 x double> @frintm_v2f64(<2 x double> %op) vscale_range(2,0) #0 { ret <2 x double> %res } -define void @frintm_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { +define void @frintm_v4f64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frintm_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -481,13 +481,13 @@ define void @frintm_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frintm z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <4 x double>, <4 x double>* %a + %op = load <4 x double>, ptr %a %res = call <4 x double> @llvm.floor.v4f64(<4 x double> %op) - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @frintm_v8f64(<8 x double>* %a) #0 { +define void @frintm_v8f64(ptr %a) #0 { ; VBITS_GE_256-LABEL: frintm_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -507,13 +507,13 @@ define void @frintm_v8f64(<8 x double>* %a) #0 { ; VBITS_GE_512-NEXT: frintm z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <8 x double>, <8 x double>* %a + %op = load <8 x double>, ptr %a %res = call <8 x double> @llvm.floor.v8f64(<8 x double> %op) - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @frintm_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { +define void @frintm_v16f64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frintm_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -521,13 +521,13 @@ define void @frintm_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frintm z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x double>, <16 x double>* %a + %op = load <16 x double>, ptr %a %res = call <16 x double> @llvm.floor.v16f64(<16 x double> %op) - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @frintm_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { +define void @frintm_v32f64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frintm_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -535,9 +535,9 @@ define void @frintm_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frintm z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x double>, <32 x double>* %a + %op = load <32 x double>, ptr %a %res = call <32 x double> @llvm.floor.v32f64(<32 x double> %op) - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } @@ -565,7 +565,7 @@ define <8 x half> @frinti_v8f16(<8 x half> %op) vscale_range(2,0) #0 { ret <8 x half> %res } -define void @frinti_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { +define void @frinti_v16f16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frinti_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -573,13 +573,13 @@ define void @frinti_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frinti z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x half>, <16 x half>* %a + %op = load <16 x half>, ptr %a %res = call <16 x half> @llvm.nearbyint.v16f16(<16 x half> %op) - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @frinti_v32f16(<32 x half>* %a) #0 { +define void @frinti_v32f16(ptr %a) #0 { ; VBITS_GE_256-LABEL: frinti_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -599,13 +599,13 @@ define void @frinti_v32f16(<32 x half>* %a) #0 { ; VBITS_GE_512-NEXT: frinti z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <32 x half>, <32 x half>* %a + %op = load <32 x half>, ptr %a %res = call <32 x half> @llvm.nearbyint.v32f16(<32 x half> %op) - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @frinti_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { +define void @frinti_v64f16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frinti_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -613,13 +613,13 @@ define void @frinti_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frinti z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x half>, <64 x half>* %a + %op = load <64 x half>, ptr %a %res = call <64 x half> @llvm.nearbyint.v64f16(<64 x half> %op) - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @frinti_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { +define void @frinti_v128f16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frinti_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -627,9 +627,9 @@ define void @frinti_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frinti z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x half>, <128 x half>* %a + %op = load <128 x half>, ptr %a %res = call <128 x half> @llvm.nearbyint.v128f16(<128 x half> %op) - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -653,7 +653,7 @@ define <4 x float> @frinti_v4f32(<4 x float> %op) vscale_range(2,0) #0 { ret <4 x float> %res } -define void @frinti_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { +define void @frinti_v8f32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frinti_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -661,13 +661,13 @@ define void @frinti_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frinti z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <8 x float>, <8 x float>* %a + %op = load <8 x float>, ptr %a %res = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %op) - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @frinti_v16f32(<16 x float>* %a) #0 { +define void @frinti_v16f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: frinti_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -687,13 +687,13 @@ define void @frinti_v16f32(<16 x float>* %a) #0 { ; VBITS_GE_512-NEXT: frinti z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <16 x float>, <16 x float>* %a + %op = load <16 x float>, ptr %a %res = call <16 x float> @llvm.nearbyint.v16f32(<16 x float> %op) - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @frinti_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { +define void @frinti_v32f32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frinti_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -701,13 +701,13 @@ define void @frinti_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frinti z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x float>, <32 x float>* %a + %op = load <32 x float>, ptr %a %res = call <32 x float> @llvm.nearbyint.v32f32(<32 x float> %op) - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @frinti_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { +define void @frinti_v64f32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frinti_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -715,9 +715,9 @@ define void @frinti_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frinti z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x float>, <64 x float>* %a + %op = load <64 x float>, ptr %a %res = call <64 x float> @llvm.nearbyint.v64f32(<64 x float> %op) - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -741,7 +741,7 @@ define <2 x double> @frinti_v2f64(<2 x double> %op) vscale_range(2,0) #0 { ret <2 x double> %res } -define void @frinti_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { +define void @frinti_v4f64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frinti_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -749,13 +749,13 @@ define void @frinti_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frinti z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <4 x double>, <4 x double>* %a + %op = load <4 x double>, ptr %a %res = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %op) - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @frinti_v8f64(<8 x double>* %a) #0 { +define void @frinti_v8f64(ptr %a) #0 { ; VBITS_GE_256-LABEL: frinti_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -775,13 +775,13 @@ define void @frinti_v8f64(<8 x double>* %a) #0 { ; VBITS_GE_512-NEXT: frinti z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <8 x double>, <8 x double>* %a + %op = load <8 x double>, ptr %a %res = call <8 x double> @llvm.nearbyint.v8f64(<8 x double> %op) - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @frinti_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { +define void @frinti_v16f64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frinti_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -789,13 +789,13 @@ define void @frinti_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frinti z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x double>, <16 x double>* %a + %op = load <16 x double>, ptr %a %res = call <16 x double> @llvm.nearbyint.v16f64(<16 x double> %op) - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @frinti_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { +define void @frinti_v32f64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frinti_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -803,9 +803,9 @@ define void @frinti_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frinti z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x double>, <32 x double>* %a + %op = load <32 x double>, ptr %a %res = call <32 x double> @llvm.nearbyint.v32f64(<32 x double> %op) - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } @@ -833,7 +833,7 @@ define <8 x half> @frintx_v8f16(<8 x half> %op) vscale_range(2,0) #0 { ret <8 x half> %res } -define void @frintx_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { +define void @frintx_v16f16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frintx_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -841,13 +841,13 @@ define void @frintx_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frintx z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x half>, <16 x half>* %a + %op = load <16 x half>, ptr %a %res = call <16 x half> @llvm.rint.v16f16(<16 x half> %op) - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @frintx_v32f16(<32 x half>* %a) #0 { +define void @frintx_v32f16(ptr %a) #0 { ; VBITS_GE_256-LABEL: frintx_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -867,13 +867,13 @@ define void @frintx_v32f16(<32 x half>* %a) #0 { ; VBITS_GE_512-NEXT: frintx z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <32 x half>, <32 x half>* %a + %op = load <32 x half>, ptr %a %res = call <32 x half> @llvm.rint.v32f16(<32 x half> %op) - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @frintx_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { +define void @frintx_v64f16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frintx_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -881,13 +881,13 @@ define void @frintx_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frintx z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x half>, <64 x half>* %a + %op = load <64 x half>, ptr %a %res = call <64 x half> @llvm.rint.v64f16(<64 x half> %op) - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @frintx_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { +define void @frintx_v128f16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frintx_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -895,9 +895,9 @@ define void @frintx_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frintx z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x half>, <128 x half>* %a + %op = load <128 x half>, ptr %a %res = call <128 x half> @llvm.rint.v128f16(<128 x half> %op) - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -921,7 +921,7 @@ define <4 x float> @frintx_v4f32(<4 x float> %op) vscale_range(2,0) #0 { ret <4 x float> %res } -define void @frintx_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { +define void @frintx_v8f32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frintx_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -929,13 +929,13 @@ define void @frintx_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frintx z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <8 x float>, <8 x float>* %a + %op = load <8 x float>, ptr %a %res = call <8 x float> @llvm.rint.v8f32(<8 x float> %op) - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @frintx_v16f32(<16 x float>* %a) #0 { +define void @frintx_v16f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: frintx_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -955,13 +955,13 @@ define void @frintx_v16f32(<16 x float>* %a) #0 { ; VBITS_GE_512-NEXT: frintx z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <16 x float>, <16 x float>* %a + %op = load <16 x float>, ptr %a %res = call <16 x float> @llvm.rint.v16f32(<16 x float> %op) - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @frintx_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { +define void @frintx_v32f32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frintx_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -969,13 +969,13 @@ define void @frintx_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frintx z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x float>, <32 x float>* %a + %op = load <32 x float>, ptr %a %res = call <32 x float> @llvm.rint.v32f32(<32 x float> %op) - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @frintx_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { +define void @frintx_v64f32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frintx_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -983,9 +983,9 @@ define void @frintx_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frintx z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x float>, <64 x float>* %a + %op = load <64 x float>, ptr %a %res = call <64 x float> @llvm.rint.v64f32(<64 x float> %op) - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -1009,7 +1009,7 @@ define <2 x double> @frintx_v2f64(<2 x double> %op) vscale_range(2,0) #0 { ret <2 x double> %res } -define void @frintx_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { +define void @frintx_v4f64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frintx_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1017,13 +1017,13 @@ define void @frintx_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frintx z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <4 x double>, <4 x double>* %a + %op = load <4 x double>, ptr %a %res = call <4 x double> @llvm.rint.v4f64(<4 x double> %op) - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @frintx_v8f64(<8 x double>* %a) #0 { +define void @frintx_v8f64(ptr %a) #0 { ; VBITS_GE_256-LABEL: frintx_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1043,13 +1043,13 @@ define void @frintx_v8f64(<8 x double>* %a) #0 { ; VBITS_GE_512-NEXT: frintx z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <8 x double>, <8 x double>* %a + %op = load <8 x double>, ptr %a %res = call <8 x double> @llvm.rint.v8f64(<8 x double> %op) - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @frintx_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { +define void @frintx_v16f64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frintx_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1057,13 +1057,13 @@ define void @frintx_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frintx z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x double>, <16 x double>* %a + %op = load <16 x double>, ptr %a %res = call <16 x double> @llvm.rint.v16f64(<16 x double> %op) - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @frintx_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { +define void @frintx_v32f64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frintx_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1071,9 +1071,9 @@ define void @frintx_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frintx z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x double>, <32 x double>* %a + %op = load <32 x double>, ptr %a %res = call <32 x double> @llvm.rint.v32f64(<32 x double> %op) - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } @@ -1101,7 +1101,7 @@ define <8 x half> @frinta_v8f16(<8 x half> %op) vscale_range(2,0) #0 { ret <8 x half> %res } -define void @frinta_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { +define void @frinta_v16f16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frinta_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -1109,13 +1109,13 @@ define void @frinta_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frinta z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x half>, <16 x half>* %a + %op = load <16 x half>, ptr %a %res = call <16 x half> @llvm.round.v16f16(<16 x half> %op) - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @frinta_v32f16(<32 x half>* %a) #0 { +define void @frinta_v32f16(ptr %a) #0 { ; VBITS_GE_256-LABEL: frinta_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -1135,13 +1135,13 @@ define void @frinta_v32f16(<32 x half>* %a) #0 { ; VBITS_GE_512-NEXT: frinta z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <32 x half>, <32 x half>* %a + %op = load <32 x half>, ptr %a %res = call <32 x half> @llvm.round.v32f16(<32 x half> %op) - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @frinta_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { +define void @frinta_v64f16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frinta_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -1149,13 +1149,13 @@ define void @frinta_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frinta z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x half>, <64 x half>* %a + %op = load <64 x half>, ptr %a %res = call <64 x half> @llvm.round.v64f16(<64 x half> %op) - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @frinta_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { +define void @frinta_v128f16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frinta_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1163,9 +1163,9 @@ define void @frinta_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frinta z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x half>, <128 x half>* %a + %op = load <128 x half>, ptr %a %res = call <128 x half> @llvm.round.v128f16(<128 x half> %op) - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -1189,7 +1189,7 @@ define <4 x float> @frinta_v4f32(<4 x float> %op) vscale_range(2,0) #0 { ret <4 x float> %res } -define void @frinta_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { +define void @frinta_v8f32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frinta_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1197,13 +1197,13 @@ define void @frinta_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frinta z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <8 x float>, <8 x float>* %a + %op = load <8 x float>, ptr %a %res = call <8 x float> @llvm.round.v8f32(<8 x float> %op) - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @frinta_v16f32(<16 x float>* %a) #0 { +define void @frinta_v16f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: frinta_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1223,13 +1223,13 @@ define void @frinta_v16f32(<16 x float>* %a) #0 { ; VBITS_GE_512-NEXT: frinta z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <16 x float>, <16 x float>* %a + %op = load <16 x float>, ptr %a %res = call <16 x float> @llvm.round.v16f32(<16 x float> %op) - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @frinta_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { +define void @frinta_v32f32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frinta_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1237,13 +1237,13 @@ define void @frinta_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frinta z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x float>, <32 x float>* %a + %op = load <32 x float>, ptr %a %res = call <32 x float> @llvm.round.v32f32(<32 x float> %op) - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @frinta_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { +define void @frinta_v64f32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frinta_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1251,9 +1251,9 @@ define void @frinta_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frinta z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x float>, <64 x float>* %a + %op = load <64 x float>, ptr %a %res = call <64 x float> @llvm.round.v64f32(<64 x float> %op) - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -1277,7 +1277,7 @@ define <2 x double> @frinta_v2f64(<2 x double> %op) vscale_range(2,0) #0 { ret <2 x double> %res } -define void @frinta_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { +define void @frinta_v4f64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frinta_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1285,13 +1285,13 @@ define void @frinta_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frinta z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <4 x double>, <4 x double>* %a + %op = load <4 x double>, ptr %a %res = call <4 x double> @llvm.round.v4f64(<4 x double> %op) - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @frinta_v8f64(<8 x double>* %a) #0 { +define void @frinta_v8f64(ptr %a) #0 { ; VBITS_GE_256-LABEL: frinta_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1311,13 +1311,13 @@ define void @frinta_v8f64(<8 x double>* %a) #0 { ; VBITS_GE_512-NEXT: frinta z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <8 x double>, <8 x double>* %a + %op = load <8 x double>, ptr %a %res = call <8 x double> @llvm.round.v8f64(<8 x double> %op) - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @frinta_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { +define void @frinta_v16f64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frinta_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1325,13 +1325,13 @@ define void @frinta_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frinta z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x double>, <16 x double>* %a + %op = load <16 x double>, ptr %a %res = call <16 x double> @llvm.round.v16f64(<16 x double> %op) - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @frinta_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { +define void @frinta_v32f64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frinta_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1339,9 +1339,9 @@ define void @frinta_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frinta z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x double>, <32 x double>* %a + %op = load <32 x double>, ptr %a %res = call <32 x double> @llvm.round.v32f64(<32 x double> %op) - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } @@ -1369,7 +1369,7 @@ define <8 x half> @frintn_v8f16(<8 x half> %op) vscale_range(2,0) #0 { ret <8 x half> %res } -define void @frintn_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { +define void @frintn_v16f16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frintn_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -1377,13 +1377,13 @@ define void @frintn_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frintn z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x half>, <16 x half>* %a + %op = load <16 x half>, ptr %a %res = call <16 x half> @llvm.roundeven.v16f16(<16 x half> %op) - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @frintn_v32f16(<32 x half>* %a) #0 { +define void @frintn_v32f16(ptr %a) #0 { ; VBITS_GE_256-LABEL: frintn_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -1403,13 +1403,13 @@ define void @frintn_v32f16(<32 x half>* %a) #0 { ; VBITS_GE_512-NEXT: frintn z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <32 x half>, <32 x half>* %a + %op = load <32 x half>, ptr %a %res = call <32 x half> @llvm.roundeven.v32f16(<32 x half> %op) - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @frintn_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { +define void @frintn_v64f16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frintn_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -1417,13 +1417,13 @@ define void @frintn_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frintn z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x half>, <64 x half>* %a + %op = load <64 x half>, ptr %a %res = call <64 x half> @llvm.roundeven.v64f16(<64 x half> %op) - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @frintn_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { +define void @frintn_v128f16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frintn_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1431,9 +1431,9 @@ define void @frintn_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frintn z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x half>, <128 x half>* %a + %op = load <128 x half>, ptr %a %res = call <128 x half> @llvm.roundeven.v128f16(<128 x half> %op) - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -1457,7 +1457,7 @@ define <4 x float> @frintn_v4f32(<4 x float> %op) vscale_range(2,0) #0 { ret <4 x float> %res } -define void @frintn_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { +define void @frintn_v8f32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frintn_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1465,13 +1465,13 @@ define void @frintn_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frintn z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <8 x float>, <8 x float>* %a + %op = load <8 x float>, ptr %a %res = call <8 x float> @llvm.roundeven.v8f32(<8 x float> %op) - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @frintn_v16f32(<16 x float>* %a) #0 { +define void @frintn_v16f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: frintn_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1491,13 +1491,13 @@ define void @frintn_v16f32(<16 x float>* %a) #0 { ; VBITS_GE_512-NEXT: frintn z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <16 x float>, <16 x float>* %a + %op = load <16 x float>, ptr %a %res = call <16 x float> @llvm.roundeven.v16f32(<16 x float> %op) - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @frintn_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { +define void @frintn_v32f32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frintn_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1505,13 +1505,13 @@ define void @frintn_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frintn z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x float>, <32 x float>* %a + %op = load <32 x float>, ptr %a %res = call <32 x float> @llvm.roundeven.v32f32(<32 x float> %op) - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @frintn_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { +define void @frintn_v64f32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frintn_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1519,9 +1519,9 @@ define void @frintn_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frintn z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x float>, <64 x float>* %a + %op = load <64 x float>, ptr %a %res = call <64 x float> @llvm.roundeven.v64f32(<64 x float> %op) - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -1545,7 +1545,7 @@ define <2 x double> @frintn_v2f64(<2 x double> %op) vscale_range(2,0) #0 { ret <2 x double> %res } -define void @frintn_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { +define void @frintn_v4f64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frintn_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1553,13 +1553,13 @@ define void @frintn_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frintn z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <4 x double>, <4 x double>* %a + %op = load <4 x double>, ptr %a %res = call <4 x double> @llvm.roundeven.v4f64(<4 x double> %op) - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @frintn_v8f64(<8 x double>* %a) #0 { +define void @frintn_v8f64(ptr %a) #0 { ; VBITS_GE_256-LABEL: frintn_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1579,13 +1579,13 @@ define void @frintn_v8f64(<8 x double>* %a) #0 { ; VBITS_GE_512-NEXT: frintn z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <8 x double>, <8 x double>* %a + %op = load <8 x double>, ptr %a %res = call <8 x double> @llvm.roundeven.v8f64(<8 x double> %op) - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @frintn_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { +define void @frintn_v16f64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frintn_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1593,13 +1593,13 @@ define void @frintn_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frintn z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x double>, <16 x double>* %a + %op = load <16 x double>, ptr %a %res = call <16 x double> @llvm.roundeven.v16f64(<16 x double> %op) - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @frintn_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { +define void @frintn_v32f64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frintn_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1607,9 +1607,9 @@ define void @frintn_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frintn z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x double>, <32 x double>* %a + %op = load <32 x double>, ptr %a %res = call <32 x double> @llvm.roundeven.v32f64(<32 x double> %op) - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } @@ -1637,7 +1637,7 @@ define <8 x half> @frintz_v8f16(<8 x half> %op) vscale_range(2,0) #0 { ret <8 x half> %res } -define void @frintz_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { +define void @frintz_v16f16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frintz_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -1645,13 +1645,13 @@ define void @frintz_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frintz z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x half>, <16 x half>* %a + %op = load <16 x half>, ptr %a %res = call <16 x half> @llvm.trunc.v16f16(<16 x half> %op) - store <16 x half> %res, <16 x half>* %a + store <16 x half> %res, ptr %a ret void } -define void @frintz_v32f16(<32 x half>* %a) #0 { +define void @frintz_v32f16(ptr %a) #0 { ; VBITS_GE_256-LABEL: frintz_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -1671,13 +1671,13 @@ define void @frintz_v32f16(<32 x half>* %a) #0 { ; VBITS_GE_512-NEXT: frintz z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <32 x half>, <32 x half>* %a + %op = load <32 x half>, ptr %a %res = call <32 x half> @llvm.trunc.v32f16(<32 x half> %op) - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @frintz_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { +define void @frintz_v64f16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frintz_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -1685,13 +1685,13 @@ define void @frintz_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frintz z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x half>, <64 x half>* %a + %op = load <64 x half>, ptr %a %res = call <64 x half> @llvm.trunc.v64f16(<64 x half> %op) - store <64 x half> %res, <64 x half>* %a + store <64 x half> %res, ptr %a ret void } -define void @frintz_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { +define void @frintz_v128f16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frintz_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1699,9 +1699,9 @@ define void @frintz_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frintz z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x half>, <128 x half>* %a + %op = load <128 x half>, ptr %a %res = call <128 x half> @llvm.trunc.v128f16(<128 x half> %op) - store <128 x half> %res, <128 x half>* %a + store <128 x half> %res, ptr %a ret void } @@ -1725,7 +1725,7 @@ define <4 x float> @frintz_v4f32(<4 x float> %op) vscale_range(2,0) #0 { ret <4 x float> %res } -define void @frintz_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { +define void @frintz_v8f32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frintz_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1733,13 +1733,13 @@ define void @frintz_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frintz z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <8 x float>, <8 x float>* %a + %op = load <8 x float>, ptr %a %res = call <8 x float> @llvm.trunc.v8f32(<8 x float> %op) - store <8 x float> %res, <8 x float>* %a + store <8 x float> %res, ptr %a ret void } -define void @frintz_v16f32(<16 x float>* %a) #0 { +define void @frintz_v16f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: frintz_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1759,13 +1759,13 @@ define void @frintz_v16f32(<16 x float>* %a) #0 { ; VBITS_GE_512-NEXT: frintz z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <16 x float>, <16 x float>* %a + %op = load <16 x float>, ptr %a %res = call <16 x float> @llvm.trunc.v16f32(<16 x float> %op) - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @frintz_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { +define void @frintz_v32f32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frintz_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1773,13 +1773,13 @@ define void @frintz_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frintz z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x float>, <32 x float>* %a + %op = load <32 x float>, ptr %a %res = call <32 x float> @llvm.trunc.v32f32(<32 x float> %op) - store <32 x float> %res, <32 x float>* %a + store <32 x float> %res, ptr %a ret void } -define void @frintz_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { +define void @frintz_v64f32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frintz_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1787,9 +1787,9 @@ define void @frintz_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frintz z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x float>, <64 x float>* %a + %op = load <64 x float>, ptr %a %res = call <64 x float> @llvm.trunc.v64f32(<64 x float> %op) - store <64 x float> %res, <64 x float>* %a + store <64 x float> %res, ptr %a ret void } @@ -1813,7 +1813,7 @@ define <2 x double> @frintz_v2f64(<2 x double> %op) vscale_range(2,0) #0 { ret <2 x double> %res } -define void @frintz_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { +define void @frintz_v4f64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: frintz_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1821,13 +1821,13 @@ define void @frintz_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: frintz z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <4 x double>, <4 x double>* %a + %op = load <4 x double>, ptr %a %res = call <4 x double> @llvm.trunc.v4f64(<4 x double> %op) - store <4 x double> %res, <4 x double>* %a + store <4 x double> %res, ptr %a ret void } -define void @frintz_v8f64(<8 x double>* %a) #0 { +define void @frintz_v8f64(ptr %a) #0 { ; VBITS_GE_256-LABEL: frintz_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1847,13 +1847,13 @@ define void @frintz_v8f64(<8 x double>* %a) #0 { ; VBITS_GE_512-NEXT: frintz z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <8 x double>, <8 x double>* %a + %op = load <8 x double>, ptr %a %res = call <8 x double> @llvm.trunc.v8f64(<8 x double> %op) - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } -define void @frintz_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { +define void @frintz_v16f64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: frintz_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1861,13 +1861,13 @@ define void @frintz_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: frintz z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x double>, <16 x double>* %a + %op = load <16 x double>, ptr %a %res = call <16 x double> @llvm.trunc.v16f64(<16 x double> %op) - store <16 x double> %res, <16 x double>* %a + store <16 x double> %res, ptr %a ret void } -define void @frintz_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { +define void @frintz_v32f64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: frintz_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1875,9 +1875,9 @@ define void @frintz_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: frintz z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x double>, <32 x double>* %a + %op = load <32 x double>, ptr %a %res = call <32 x double> @llvm.trunc.v32f64(<32 x double> %op) - store <32 x double> %res, <32 x double>* %a + store <32 x double> %res, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll index 14cc314..95c312d 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll @@ -31,7 +31,7 @@ define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, i1 %mask) vsca ret <8 x half> %sel } -define void @select_v16f16(<16 x half>* %a, <16 x half>* %b, i1 %mask) vscale_range(2,0) #0 { +define void @select_v16f16(ptr %a, ptr %b, i1 %mask) vscale_range(2,0) #0 { ; CHECK-LABEL: select_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -45,14 +45,14 @@ define void @select_v16f16(<16 x half>* %a, <16 x half>* %b, i1 %mask) vscale_ra ; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <16 x half>, <16 x half>* %a - %op2 = load volatile <16 x half>, <16 x half>* %b + %op1 = load volatile <16 x half>, ptr %a + %op2 = load volatile <16 x half>, ptr %b %sel = select i1 %mask, <16 x half> %op1, <16 x half> %op2 - store <16 x half> %sel, <16 x half>* %a + store <16 x half> %sel, ptr %a ret void } -define void @select_v32f16(<32 x half>* %a, <32 x half>* %b, i1 %mask) #0 { +define void @select_v32f16(ptr %a, ptr %b, i1 %mask) #0 { ; VBITS_GE_256-LABEL: select_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -85,14 +85,14 @@ define void @select_v32f16(<32 x half>* %a, <32 x half>* %b, i1 %mask) #0 { ; VBITS_GE_512-NEXT: sel z0.h, p1, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load volatile <32 x half>, <32 x half>* %a - %op2 = load volatile <32 x half>, <32 x half>* %b + %op1 = load volatile <32 x half>, ptr %a + %op2 = load volatile <32 x half>, ptr %b %sel = select i1 %mask, <32 x half> %op1, <32 x half> %op2 - store <32 x half> %sel, <32 x half>* %a + store <32 x half> %sel, ptr %a ret void } -define void @select_v64f16(<64 x half>* %a, <64 x half>* %b, i1 %mask) vscale_range(8,0) #0 { +define void @select_v64f16(ptr %a, ptr %b, i1 %mask) vscale_range(8,0) #0 { ; CHECK-LABEL: select_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -106,14 +106,14 @@ define void @select_v64f16(<64 x half>* %a, <64 x half>* %b, i1 %mask) vscale_ra ; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <64 x half>, <64 x half>* %a - %op2 = load volatile <64 x half>, <64 x half>* %b + %op1 = load volatile <64 x half>, ptr %a + %op2 = load volatile <64 x half>, ptr %b %sel = select i1 %mask, <64 x half> %op1, <64 x half> %op2 - store <64 x half> %sel, <64 x half>* %a + store <64 x half> %sel, ptr %a ret void } -define void @select_v128f16(<128 x half>* %a, <128 x half>* %b, i1 %mask) vscale_range(16,0) #0 { +define void @select_v128f16(ptr %a, ptr %b, i1 %mask) vscale_range(16,0) #0 { ; CHECK-LABEL: select_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -127,10 +127,10 @@ define void @select_v128f16(<128 x half>* %a, <128 x half>* %b, i1 %mask) vscale ; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <128 x half>, <128 x half>* %a - %op2 = load volatile <128 x half>, <128 x half>* %b + %op1 = load volatile <128 x half>, ptr %a + %op2 = load volatile <128 x half>, ptr %b %sel = select i1 %mask, <128 x half> %op1, <128 x half> %op2 - store <128 x half> %sel, <128 x half>* %a + store <128 x half> %sel, ptr %a ret void } @@ -160,7 +160,7 @@ define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, i1 %mask) v ret <4 x float> %sel } -define void @select_v8f32(<8 x float>* %a, <8 x float>* %b, i1 %mask) vscale_range(2,0) #0 { +define void @select_v8f32(ptr %a, ptr %b, i1 %mask) vscale_range(2,0) #0 { ; CHECK-LABEL: select_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -173,14 +173,14 @@ define void @select_v8f32(<8 x float>* %a, <8 x float>* %b, i1 %mask) vscale_ran ; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <8 x float>, <8 x float>* %a - %op2 = load volatile <8 x float>, <8 x float>* %b + %op1 = load volatile <8 x float>, ptr %a + %op2 = load volatile <8 x float>, ptr %b %sel = select i1 %mask, <8 x float> %op1, <8 x float> %op2 - store <8 x float> %sel, <8 x float>* %a + store <8 x float> %sel, ptr %a ret void } -define void @select_v16f32(<16 x float>* %a, <16 x float>* %b, i1 %mask) #0 { +define void @select_v16f32(ptr %a, ptr %b, i1 %mask) #0 { ; VBITS_GE_256-LABEL: select_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -211,14 +211,14 @@ define void @select_v16f32(<16 x float>* %a, <16 x float>* %b, i1 %mask) #0 { ; VBITS_GE_512-NEXT: sel z0.s, p1, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load volatile <16 x float>, <16 x float>* %a - %op2 = load volatile <16 x float>, <16 x float>* %b + %op1 = load volatile <16 x float>, ptr %a + %op2 = load volatile <16 x float>, ptr %b %sel = select i1 %mask, <16 x float> %op1, <16 x float> %op2 - store <16 x float> %sel, <16 x float>* %a + store <16 x float> %sel, ptr %a ret void } -define void @select_v32f32(<32 x float>* %a, <32 x float>* %b, i1 %mask) vscale_range(8,0) #0 { +define void @select_v32f32(ptr %a, ptr %b, i1 %mask) vscale_range(8,0) #0 { ; CHECK-LABEL: select_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -231,14 +231,14 @@ define void @select_v32f32(<32 x float>* %a, <32 x float>* %b, i1 %mask) vscale_ ; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <32 x float>, <32 x float>* %a - %op2 = load volatile <32 x float>, <32 x float>* %b + %op1 = load volatile <32 x float>, ptr %a + %op2 = load volatile <32 x float>, ptr %b %sel = select i1 %mask, <32 x float> %op1, <32 x float> %op2 - store <32 x float> %sel, <32 x float>* %a + store <32 x float> %sel, ptr %a ret void } -define void @select_v64f32(<64 x float>* %a, <64 x float>* %b, i1 %mask) vscale_range(16,0) #0 { +define void @select_v64f32(ptr %a, ptr %b, i1 %mask) vscale_range(16,0) #0 { ; CHECK-LABEL: select_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -251,10 +251,10 @@ define void @select_v64f32(<64 x float>* %a, <64 x float>* %b, i1 %mask) vscale_ ; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <64 x float>, <64 x float>* %a - %op2 = load volatile <64 x float>, <64 x float>* %b + %op1 = load volatile <64 x float>, ptr %a + %op2 = load volatile <64 x float>, ptr %b %sel = select i1 %mask, <64 x float> %op1, <64 x float> %op2 - store <64 x float> %sel, <64 x float>* %a + store <64 x float> %sel, ptr %a ret void } @@ -284,7 +284,7 @@ define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, i1 %mask ret <2 x double> %sel } -define void @select_v4f64(<4 x double>* %a, <4 x double>* %b, i1 %mask) vscale_range(2,0) #0 { +define void @select_v4f64(ptr %a, ptr %b, i1 %mask) vscale_range(2,0) #0 { ; CHECK-LABEL: select_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -297,14 +297,14 @@ define void @select_v4f64(<4 x double>* %a, <4 x double>* %b, i1 %mask) vscale_r ; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <4 x double>, <4 x double>* %a - %op2 = load volatile <4 x double>, <4 x double>* %b + %op1 = load volatile <4 x double>, ptr %a + %op2 = load volatile <4 x double>, ptr %b %sel = select i1 %mask, <4 x double> %op1, <4 x double> %op2 - store <4 x double> %sel, <4 x double>* %a + store <4 x double> %sel, ptr %a ret void } -define void @select_v8f64(<8 x double>* %a, <8 x double>* %b, i1 %mask) #0 { +define void @select_v8f64(ptr %a, ptr %b, i1 %mask) #0 { ; VBITS_GE_256-LABEL: select_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -335,14 +335,14 @@ define void @select_v8f64(<8 x double>* %a, <8 x double>* %b, i1 %mask) #0 { ; VBITS_GE_512-NEXT: sel z0.d, p1, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load volatile <8 x double>, <8 x double>* %a - %op2 = load volatile <8 x double>, <8 x double>* %b + %op1 = load volatile <8 x double>, ptr %a + %op2 = load volatile <8 x double>, ptr %b %sel = select i1 %mask, <8 x double> %op1, <8 x double> %op2 - store <8 x double> %sel, <8 x double>* %a + store <8 x double> %sel, ptr %a ret void } -define void @select_v16f64(<16 x double>* %a, <16 x double>* %b, i1 %mask) vscale_range(8,0) #0 { +define void @select_v16f64(ptr %a, ptr %b, i1 %mask) vscale_range(8,0) #0 { ; CHECK-LABEL: select_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -355,14 +355,14 @@ define void @select_v16f64(<16 x double>* %a, <16 x double>* %b, i1 %mask) vscal ; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <16 x double>, <16 x double>* %a - %op2 = load volatile <16 x double>, <16 x double>* %b + %op1 = load volatile <16 x double>, ptr %a + %op2 = load volatile <16 x double>, ptr %b %sel = select i1 %mask, <16 x double> %op1, <16 x double> %op2 - store <16 x double> %sel, <16 x double>* %a + store <16 x double> %sel, ptr %a ret void } -define void @select_v32f64(<32 x double>* %a, <32 x double>* %b, i1 %mask) vscale_range(16,0) #0 { +define void @select_v32f64(ptr %a, ptr %b, i1 %mask) vscale_range(16,0) #0 { ; CHECK-LABEL: select_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -375,10 +375,10 @@ define void @select_v32f64(<32 x double>* %a, <32 x double>* %b, i1 %mask) vscal ; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <32 x double>, <32 x double>* %a - %op2 = load volatile <32 x double>, <32 x double>* %b + %op1 = load volatile <32 x double>, ptr %a + %op2 = load volatile <32 x double>, ptr %b %sel = select i1 %mask, <32 x double> %op1, <32 x double> %op2 - store <32 x double> %sel, <32 x double>* %a + store <32 x double> %sel, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll index ae37828..1bfc2de 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll @@ -20,20 +20,20 @@ define <4 x i16> @fcvtzu_v4f16_v4i16(<4 x half> %op1) vscale_range(2,0) #0 { } ; Don't use SVE for 128-bit vectors. -define void @fcvtzu_v8f16_v8i16(<8 x half>* %a, <8 x i16>* %b) vscale_range(2,0) #0 { +define void @fcvtzu_v8f16_v8i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzu_v8f16_v8i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: fcvtzu v0.8h, v0.8h ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %op1 = load <8 x half>, <8 x half>* %a + %op1 = load <8 x half>, ptr %a %res = fptoui <8 x half> %op1 to <8 x i16> - store <8 x i16> %res, <8 x i16>* %b + store <8 x i16> %res, ptr %b ret void } -define void @fcvtzu_v16f16_v16i16(<16 x half>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @fcvtzu_v16f16_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzu_v16f16_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -41,13 +41,13 @@ define void @fcvtzu_v16f16_v16i16(<16 x half>* %a, <16 x i16>* %b) vscale_range( ; CHECK-NEXT: fcvtzu z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a + %op1 = load <16 x half>, ptr %a %res = fptoui <16 x half> %op1 to <16 x i16> - store <16 x i16> %res, <16 x i16>* %b + store <16 x i16> %res, ptr %b ret void } -define void @fcvtzu_v32f16_v32i16(<32 x half>* %a, <32 x i16>* %b) #0 { +define void @fcvtzu_v32f16_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvtzu_v32f16_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -67,13 +67,13 @@ define void @fcvtzu_v32f16_v32i16(<32 x half>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: fcvtzu z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a + %op1 = load <32 x half>, ptr %a %res = fptoui <32 x half> %op1 to <32 x i16> - store <32 x i16> %res, <32 x i16>* %b + store <32 x i16> %res, ptr %b ret void } -define void @fcvtzu_v64f16_v64i16(<64 x half>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @fcvtzu_v64f16_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvtzu_v64f16_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -81,13 +81,13 @@ define void @fcvtzu_v64f16_v64i16(<64 x half>* %a, <64 x i16>* %b) vscale_range( ; CHECK-NEXT: fcvtzu z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a + %op1 = load <64 x half>, ptr %a %res = fptoui <64 x half> %op1 to <64 x i16> - store <64 x i16> %res, <64 x i16>* %b + store <64 x i16> %res, ptr %b ret void } -define void @fcvtzu_v128f16_v128i16(<128 x half>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @fcvtzu_v128f16_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvtzu_v128f16_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -95,9 +95,9 @@ define void @fcvtzu_v128f16_v128i16(<128 x half>* %a, <128 x i16>* %b) vscale_ra ; CHECK-NEXT: fcvtzu z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <128 x half>, <128 x half>* %a + %op1 = load <128 x half>, ptr %a %res = fptoui <128 x half> %op1 to <128 x i16> - store <128 x i16> %res, <128 x i16>* %b + store <128 x i16> %res, ptr %b ret void } @@ -128,7 +128,7 @@ define <4 x i32> @fcvtzu_v4f16_v4i32(<4 x half> %op1) vscale_range(2,0) #0 { ret <4 x i32> %res } -define void @fcvtzu_v8f16_v8i32(<8 x half>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @fcvtzu_v8f16_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzu_v8f16_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -137,13 +137,13 @@ define void @fcvtzu_v8f16_v8i32(<8 x half>* %a, <8 x i32>* %b) vscale_range(2,0) ; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <8 x half>, <8 x half>* %a + %op1 = load <8 x half>, ptr %a %res = fptoui <8 x half> %op1 to <8 x i32> - store <8 x i32> %res, <8 x i32>* %b + store <8 x i32> %res, ptr %b ret void } -define void @fcvtzu_v16f16_v16i32(<16 x half>* %a, <16 x i32>* %b) #0 { +define void @fcvtzu_v16f16_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvtzu_v16f16_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.h, vl16 @@ -166,13 +166,13 @@ define void @fcvtzu_v16f16_v16i32(<16 x half>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: fcvtzu z0.s, p0/m, z0.h ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a + %op1 = load <16 x half>, ptr %a %res = fptoui <16 x half> %op1 to <16 x i32> - store <16 x i32> %res, <16 x i32>* %b + store <16 x i32> %res, ptr %b ret void } -define void @fcvtzu_v32f16_v32i32(<32 x half>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @fcvtzu_v32f16_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvtzu_v32f16_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -180,13 +180,13 @@ define void @fcvtzu_v32f16_v32i32(<32 x half>* %a, <32 x i32>* %b) vscale_range( ; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a + %op1 = load <32 x half>, ptr %a %res = fptoui <32 x half> %op1 to <32 x i32> - store <32 x i32> %res, <32 x i32>* %b + store <32 x i32> %res, ptr %b ret void } -define void @fcvtzu_v64f16_v64i32(<64 x half>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @fcvtzu_v64f16_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvtzu_v64f16_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -194,9 +194,9 @@ define void @fcvtzu_v64f16_v64i32(<64 x half>* %a, <64 x i32>* %b) vscale_range( ; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a + %op1 = load <64 x half>, ptr %a %res = fptoui <64 x half> %op1 to <64 x i32> - store <64 x i32> %res, <64 x i32>* %b + store <64 x i32> %res, ptr %b ret void } @@ -230,7 +230,7 @@ define <2 x i64> @fcvtzu_v2f16_v2i64(<2 x half> %op1) vscale_range(2,0) #0 { ret <2 x i64> %res } -define void @fcvtzu_v4f16_v4i64(<4 x half>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @fcvtzu_v4f16_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzu_v4f16_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -240,13 +240,13 @@ define void @fcvtzu_v4f16_v4i64(<4 x half>* %a, <4 x i64>* %b) vscale_range(2,0) ; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x half>, <4 x half>* %a + %op1 = load <4 x half>, ptr %a %res = fptoui <4 x half> %op1 to <4 x i64> - store <4 x i64> %res, <4 x i64>* %b + store <4 x i64> %res, ptr %b ret void } -define void @fcvtzu_v8f16_v8i64(<8 x half>* %a, <8 x i64>* %b) #0 { +define void @fcvtzu_v8f16_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvtzu_v8f16_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ldr q0, [x0] @@ -272,13 +272,13 @@ define void @fcvtzu_v8f16_v8i64(<8 x half>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: fcvtzu z0.d, p0/m, z0.h ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x half>, <8 x half>* %a + %op1 = load <8 x half>, ptr %a %res = fptoui <8 x half> %op1 to <8 x i64> - store <8 x i64> %res, <8 x i64>* %b + store <8 x i64> %res, ptr %b ret void } -define void @fcvtzu_v16f16_v16i64(<16 x half>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @fcvtzu_v16f16_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvtzu_v16f16_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -286,13 +286,13 @@ define void @fcvtzu_v16f16_v16i64(<16 x half>* %a, <16 x i64>* %b) vscale_range( ; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a + %op1 = load <16 x half>, ptr %a %res = fptoui <16 x half> %op1 to <16 x i64> - store <16 x i64> %res, <16 x i64>* %b + store <16 x i64> %res, ptr %b ret void } -define void @fcvtzu_v32f16_v32i64(<32 x half>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @fcvtzu_v32f16_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvtzu_v32f16_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -300,9 +300,9 @@ define void @fcvtzu_v32f16_v32i64(<32 x half>* %a, <32 x i64>* %b) vscale_range( ; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a + %op1 = load <32 x half>, ptr %a %res = fptoui <32 x half> %op1 to <32 x i64> - store <32 x i64> %res, <32 x i64>* %b + store <32 x i64> %res, ptr %b ret void } @@ -338,7 +338,7 @@ define <4 x i16> @fcvtzu_v4f32_v4i16(<4 x float> %op1) vscale_range(2,0) #0 { ret <4 x i16> %res } -define <8 x i16> @fcvtzu_v8f32_v8i16(<8 x float>* %a) vscale_range(2,0) #0 { +define <8 x i16> @fcvtzu_v8f32_v8i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzu_v8f32_v8i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -348,12 +348,12 @@ define <8 x i16> @fcvtzu_v8f32_v8i16(<8 x float>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a + %op1 = load <8 x float>, ptr %a %res = fptoui <8 x float> %op1 to <8 x i16> ret <8 x i16> %res } -define void @fcvtzu_v16f32_v16i16(<16 x float>* %a, <16 x i16>* %b) #0 { +define void @fcvtzu_v16f32_v16i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvtzu_v16f32_v16i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -379,13 +379,13 @@ define void @fcvtzu_v16f32_v16i16(<16 x float>* %a, <16 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: fcvtzu z0.s, p1/m, z0.s ; VBITS_GE_512-NEXT: st1h { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a + %op1 = load <16 x float>, ptr %a %res = fptoui <16 x float> %op1 to <16 x i16> - store <16 x i16> %res, <16 x i16>* %b + store <16 x i16> %res, ptr %b ret void } -define void @fcvtzu_v32f32_v32i16(<32 x float>* %a, <32 x i16>* %b) vscale_range(8,0) #0 { +define void @fcvtzu_v32f32_v32i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvtzu_v32f32_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -394,13 +394,13 @@ define void @fcvtzu_v32f32_v32i16(<32 x float>* %a, <32 x i16>* %b) vscale_range ; CHECK-NEXT: fcvtzu z0.s, p1/m, z0.s ; CHECK-NEXT: st1h { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a + %op1 = load <32 x float>, ptr %a %res = fptoui <32 x float> %op1 to <32 x i16> - store <32 x i16> %res, <32 x i16>* %b + store <32 x i16> %res, ptr %b ret void } -define void @fcvtzu_v64f32_v64i16(<64 x float>* %a, <64 x i16>* %b) vscale_range(16,0) #0 { +define void @fcvtzu_v64f32_v64i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvtzu_v64f32_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -409,9 +409,9 @@ define void @fcvtzu_v64f32_v64i16(<64 x float>* %a, <64 x i16>* %b) vscale_range ; CHECK-NEXT: fcvtzu z0.s, p1/m, z0.s ; CHECK-NEXT: st1h { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a + %op1 = load <64 x float>, ptr %a %res = fptoui <64 x float> %op1 to <64 x i16> - store <64 x i16> %res, <64 x i16>* %b + store <64 x i16> %res, ptr %b ret void } @@ -439,7 +439,7 @@ define <4 x i32> @fcvtzu_v4f32_v4i32(<4 x float> %op1) vscale_range(2,0) #0 { ret <4 x i32> %res } -define void @fcvtzu_v8f32_v8i32(<8 x float>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @fcvtzu_v8f32_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzu_v8f32_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -447,13 +447,13 @@ define void @fcvtzu_v8f32_v8i32(<8 x float>* %a, <8 x i32>* %b) vscale_range(2,0 ; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a + %op1 = load <8 x float>, ptr %a %res = fptoui <8 x float> %op1 to <8 x i32> - store <8 x i32> %res, <8 x i32>* %b + store <8 x i32> %res, ptr %b ret void } -define void @fcvtzu_v16f32_v16i32(<16 x float>* %a, <16 x i32>* %b) #0 { +define void @fcvtzu_v16f32_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvtzu_v16f32_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -473,13 +473,13 @@ define void @fcvtzu_v16f32_v16i32(<16 x float>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: fcvtzu z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a + %op1 = load <16 x float>, ptr %a %res = fptoui <16 x float> %op1 to <16 x i32> - store <16 x i32> %res, <16 x i32>* %b + store <16 x i32> %res, ptr %b ret void } -define void @fcvtzu_v32f32_v32i32(<32 x float>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @fcvtzu_v32f32_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvtzu_v32f32_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -487,13 +487,13 @@ define void @fcvtzu_v32f32_v32i32(<32 x float>* %a, <32 x i32>* %b) vscale_range ; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a + %op1 = load <32 x float>, ptr %a %res = fptoui <32 x float> %op1 to <32 x i32> - store <32 x i32> %res, <32 x i32>* %b + store <32 x i32> %res, ptr %b ret void } -define void @fcvtzu_v64f32_v64i32(<64 x float>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @fcvtzu_v64f32_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvtzu_v64f32_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -501,9 +501,9 @@ define void @fcvtzu_v64f32_v64i32(<64 x float>* %a, <64 x i32>* %b) vscale_range ; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a + %op1 = load <64 x float>, ptr %a %res = fptoui <64 x float> %op1 to <64 x i32> - store <64 x i32> %res, <64 x i32>* %b + store <64 x i32> %res, ptr %b ret void } @@ -534,7 +534,7 @@ define <2 x i64> @fcvtzu_v2f32_v2i64(<2 x float> %op1) vscale_range(2,0) #0 { ret <2 x i64> %res } -define void @fcvtzu_v4f32_v4i64(<4 x float>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @fcvtzu_v4f32_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzu_v4f32_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -543,13 +543,13 @@ define void @fcvtzu_v4f32_v4i64(<4 x float>* %a, <4 x i64>* %b) vscale_range(2,0 ; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x float>, <4 x float>* %a + %op1 = load <4 x float>, ptr %a %res = fptoui <4 x float> %op1 to <4 x i64> - store <4 x i64> %res, <4 x i64>* %b + store <4 x i64> %res, ptr %b ret void } -define void @fcvtzu_v8f32_v8i64(<8 x float>* %a, <8 x i64>* %b) #0 { +define void @fcvtzu_v8f32_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvtzu_v8f32_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.s, vl8 @@ -572,13 +572,13 @@ define void @fcvtzu_v8f32_v8i64(<8 x float>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: fcvtzu z0.d, p0/m, z0.s ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a + %op1 = load <8 x float>, ptr %a %res = fptoui <8 x float> %op1 to <8 x i64> - store <8 x i64> %res, <8 x i64>* %b + store <8 x i64> %res, ptr %b ret void } -define void @fcvtzu_v16f32_v16i64(<16 x float>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @fcvtzu_v16f32_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvtzu_v16f32_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -586,13 +586,13 @@ define void @fcvtzu_v16f32_v16i64(<16 x float>* %a, <16 x i64>* %b) vscale_range ; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a + %op1 = load <16 x float>, ptr %a %res = fptoui <16 x float> %op1 to <16 x i64> - store <16 x i64> %res, <16 x i64>* %b + store <16 x i64> %res, ptr %b ret void } -define void @fcvtzu_v32f32_v32i64(<32 x float>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @fcvtzu_v32f32_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvtzu_v32f32_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -600,9 +600,9 @@ define void @fcvtzu_v32f32_v32i64(<32 x float>* %a, <32 x i64>* %b) vscale_range ; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a + %op1 = load <32 x float>, ptr %a %res = fptoui <32 x float> %op1 to <32 x i64> - store <32 x i64> %res, <32 x i64>* %b + store <32 x i64> %res, ptr %b ret void } @@ -637,7 +637,7 @@ define <2 x i16> @fcvtzu_v2f64_v2i16(<2 x double> %op1) vscale_range(2,0) #0 { ret <2 x i16> %res } -define <4 x i16> @fcvtzu_v4f64_v4i16(<4 x double>* %a) vscale_range(2,0) #0 { +define <4 x i16> @fcvtzu_v4f64_v4i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzu_v4f64_v4i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -648,12 +648,12 @@ define <4 x i16> @fcvtzu_v4f64_v4i16(<4 x double>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a + %op1 = load <4 x double>, ptr %a %res = fptoui <4 x double> %op1 to <4 x i16> ret <4 x i16> %res } -define <8 x i16> @fcvtzu_v8f64_v8i16(<8 x double>* %a) #0 { +define <8 x i16> @fcvtzu_v8f64_v8i16(ptr %a) #0 { ; VBITS_GE_256-LABEL: fcvtzu_v8f64_v8i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -681,12 +681,12 @@ define <8 x i16> @fcvtzu_v8f64_v8i16(<8 x double>* %a) #0 { ; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h ; VBITS_GE_512-NEXT: // kill: def $q0 killed $q0 killed $z0 ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a + %op1 = load <8 x double>, ptr %a %res = fptoui <8 x double> %op1 to <8 x i16> ret <8 x i16> %res } -define void @fcvtzu_v16f64_v16i16(<16 x double>* %a, <16 x i16>* %b) vscale_range(8,0) #0 { +define void @fcvtzu_v16f64_v16i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvtzu_v16f64_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -695,13 +695,13 @@ define void @fcvtzu_v16f64_v16i16(<16 x double>* %a, <16 x i16>* %b) vscale_rang ; CHECK-NEXT: fcvtzu z0.d, p1/m, z0.d ; CHECK-NEXT: st1h { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a + %op1 = load <16 x double>, ptr %a %res = fptoui <16 x double> %op1 to <16 x i16> - store <16 x i16> %res, <16 x i16>* %b + store <16 x i16> %res, ptr %b ret void } -define void @fcvtzu_v32f64_v32i16(<32 x double>* %a, <32 x i16>* %b) vscale_range(16,0) #0 { +define void @fcvtzu_v32f64_v32i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvtzu_v32f64_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -710,9 +710,9 @@ define void @fcvtzu_v32f64_v32i16(<32 x double>* %a, <32 x i16>* %b) vscale_rang ; CHECK-NEXT: fcvtzu z0.d, p1/m, z0.d ; CHECK-NEXT: st1h { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a + %op1 = load <32 x double>, ptr %a %res = fptoui <32 x double> %op1 to <32 x i16> - store <32 x i16> %res, <32 x i16>* %b + store <32 x i16> %res, ptr %b ret void } @@ -743,7 +743,7 @@ define <2 x i32> @fcvtzu_v2f64_v2i32(<2 x double> %op1) vscale_range(2,0) #0 { ret <2 x i32> %res } -define <4 x i32> @fcvtzu_v4f64_v4i32(<4 x double>* %a) vscale_range(2,0) #0 { +define <4 x i32> @fcvtzu_v4f64_v4i32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzu_v4f64_v4i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -753,12 +753,12 @@ define <4 x i32> @fcvtzu_v4f64_v4i32(<4 x double>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a + %op1 = load <4 x double>, ptr %a %res = fptoui <4 x double> %op1 to <4 x i32> ret <4 x i32> %res } -define void @fcvtzu_v8f64_v8i32(<8 x double>* %a, <8 x i32>* %b) #0 { +define void @fcvtzu_v8f64_v8i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvtzu_v8f64_v8i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -784,13 +784,13 @@ define void @fcvtzu_v8f64_v8i32(<8 x double>* %a, <8 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: fcvtzu z0.d, p1/m, z0.d ; VBITS_GE_512-NEXT: st1w { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a + %op1 = load <8 x double>, ptr %a %res = fptoui <8 x double> %op1 to <8 x i32> - store <8 x i32> %res, <8 x i32>* %b + store <8 x i32> %res, ptr %b ret void } -define void @fcvtzu_v16f64_v16i32(<16 x double>* %a, <16 x i32>* %b) vscale_range(8,0) #0 { +define void @fcvtzu_v16f64_v16i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvtzu_v16f64_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -799,13 +799,13 @@ define void @fcvtzu_v16f64_v16i32(<16 x double>* %a, <16 x i32>* %b) vscale_rang ; CHECK-NEXT: fcvtzu z0.d, p1/m, z0.d ; CHECK-NEXT: st1w { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a + %op1 = load <16 x double>, ptr %a %res = fptoui <16 x double> %op1 to <16 x i32> - store <16 x i32> %res, <16 x i32>* %b + store <16 x i32> %res, ptr %b ret void } -define void @fcvtzu_v32f64_v32i32(<32 x double>* %a, <32 x i32>* %b) vscale_range(16,0) #0 { +define void @fcvtzu_v32f64_v32i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvtzu_v32f64_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -814,9 +814,9 @@ define void @fcvtzu_v32f64_v32i32(<32 x double>* %a, <32 x i32>* %b) vscale_rang ; CHECK-NEXT: fcvtzu z0.d, p1/m, z0.d ; CHECK-NEXT: st1w { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a + %op1 = load <32 x double>, ptr %a %res = fptoui <32 x double> %op1 to <32 x i32> - store <32 x i32> %res, <32 x i32>* %b + store <32 x i32> %res, ptr %b ret void } @@ -845,7 +845,7 @@ define <2 x i64> @fcvtzu_v2f64_v2i64(<2 x double> %op1) vscale_range(2,0) #0 { ret <2 x i64> %res } -define void @fcvtzu_v4f64_v4i64(<4 x double>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @fcvtzu_v4f64_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzu_v4f64_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -853,13 +853,13 @@ define void @fcvtzu_v4f64_v4i64(<4 x double>* %a, <4 x i64>* %b) vscale_range(2, ; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a + %op1 = load <4 x double>, ptr %a %res = fptoui <4 x double> %op1 to <4 x i64> - store <4 x i64> %res, <4 x i64>* %b + store <4 x i64> %res, ptr %b ret void } -define void @fcvtzu_v8f64_v8i64(<8 x double>* %a, <8 x i64>* %b) #0 { +define void @fcvtzu_v8f64_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvtzu_v8f64_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -879,13 +879,13 @@ define void @fcvtzu_v8f64_v8i64(<8 x double>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: fcvtzu z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a + %op1 = load <8 x double>, ptr %a %res = fptoui <8 x double> %op1 to <8 x i64> - store <8 x i64> %res, <8 x i64>* %b + store <8 x i64> %res, ptr %b ret void } -define void @fcvtzu_v16f64_v16i64(<16 x double>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @fcvtzu_v16f64_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvtzu_v16f64_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -893,13 +893,13 @@ define void @fcvtzu_v16f64_v16i64(<16 x double>* %a, <16 x i64>* %b) vscale_rang ; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a + %op1 = load <16 x double>, ptr %a %res = fptoui <16 x double> %op1 to <16 x i64> - store <16 x i64> %res, <16 x i64>* %b + store <16 x i64> %res, ptr %b ret void } -define void @fcvtzu_v32f64_v32i64(<32 x double>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @fcvtzu_v32f64_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvtzu_v32f64_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -907,9 +907,9 @@ define void @fcvtzu_v32f64_v32i64(<32 x double>* %a, <32 x i64>* %b) vscale_rang ; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a + %op1 = load <32 x double>, ptr %a %res = fptoui <32 x double> %op1 to <32 x i64> - store <32 x i64> %res, <32 x i64>* %b + store <32 x i64> %res, ptr %b ret void } @@ -928,20 +928,20 @@ define <4 x i16> @fcvtzs_v4f16_v4i16(<4 x half> %op1) vscale_range(2,0) #0 { } ; Don't use SVE for 128-bit vectors. -define void @fcvtzs_v8f16_v8i16(<8 x half>* %a, <8 x i16>* %b) vscale_range(2,0) #0 { +define void @fcvtzs_v8f16_v8i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzs_v8f16_v8i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: fcvtzs v0.8h, v0.8h ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %op1 = load <8 x half>, <8 x half>* %a + %op1 = load <8 x half>, ptr %a %res = fptosi <8 x half> %op1 to <8 x i16> - store <8 x i16> %res, <8 x i16>* %b + store <8 x i16> %res, ptr %b ret void } -define void @fcvtzs_v16f16_v16i16(<16 x half>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @fcvtzs_v16f16_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzs_v16f16_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -949,13 +949,13 @@ define void @fcvtzs_v16f16_v16i16(<16 x half>* %a, <16 x i16>* %b) vscale_range( ; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a + %op1 = load <16 x half>, ptr %a %res = fptosi <16 x half> %op1 to <16 x i16> - store <16 x i16> %res, <16 x i16>* %b + store <16 x i16> %res, ptr %b ret void } -define void @fcvtzs_v32f16_v32i16(<32 x half>* %a, <32 x i16>* %b) #0 { +define void @fcvtzs_v32f16_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvtzs_v32f16_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -975,13 +975,13 @@ define void @fcvtzs_v32f16_v32i16(<32 x half>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: fcvtzs z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a + %op1 = load <32 x half>, ptr %a %res = fptosi <32 x half> %op1 to <32 x i16> - store <32 x i16> %res, <32 x i16>* %b + store <32 x i16> %res, ptr %b ret void } -define void @fcvtzs_v64f16_v64i16(<64 x half>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @fcvtzs_v64f16_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvtzs_v64f16_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -989,13 +989,13 @@ define void @fcvtzs_v64f16_v64i16(<64 x half>* %a, <64 x i16>* %b) vscale_range( ; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a + %op1 = load <64 x half>, ptr %a %res = fptosi <64 x half> %op1 to <64 x i16> - store <64 x i16> %res, <64 x i16>* %b + store <64 x i16> %res, ptr %b ret void } -define void @fcvtzs_v128f16_v128i16(<128 x half>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @fcvtzs_v128f16_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvtzs_v128f16_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1003,9 +1003,9 @@ define void @fcvtzs_v128f16_v128i16(<128 x half>* %a, <128 x i16>* %b) vscale_ra ; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <128 x half>, <128 x half>* %a + %op1 = load <128 x half>, ptr %a %res = fptosi <128 x half> %op1 to <128 x i16> - store <128 x i16> %res, <128 x i16>* %b + store <128 x i16> %res, ptr %b ret void } @@ -1036,7 +1036,7 @@ define <4 x i32> @fcvtzs_v4f16_v4i32(<4 x half> %op1) vscale_range(2,0) #0 { ret <4 x i32> %res } -define void @fcvtzs_v8f16_v8i32(<8 x half>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @fcvtzs_v8f16_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzs_v8f16_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -1045,13 +1045,13 @@ define void @fcvtzs_v8f16_v8i32(<8 x half>* %a, <8 x i32>* %b) vscale_range(2,0) ; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <8 x half>, <8 x half>* %a + %op1 = load <8 x half>, ptr %a %res = fptosi <8 x half> %op1 to <8 x i32> - store <8 x i32> %res, <8 x i32>* %b + store <8 x i32> %res, ptr %b ret void } -define void @fcvtzs_v16f16_v16i32(<16 x half>* %a, <16 x i32>* %b) #0 { +define void @fcvtzs_v16f16_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvtzs_v16f16_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.h, vl16 @@ -1074,13 +1074,13 @@ define void @fcvtzs_v16f16_v16i32(<16 x half>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: fcvtzs z0.s, p0/m, z0.h ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a + %op1 = load <16 x half>, ptr %a %res = fptosi <16 x half> %op1 to <16 x i32> - store <16 x i32> %res, <16 x i32>* %b + store <16 x i32> %res, ptr %b ret void } -define void @fcvtzs_v32f16_v32i32(<32 x half>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @fcvtzs_v32f16_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvtzs_v32f16_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1088,13 +1088,13 @@ define void @fcvtzs_v32f16_v32i32(<32 x half>* %a, <32 x i32>* %b) vscale_range( ; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a + %op1 = load <32 x half>, ptr %a %res = fptosi <32 x half> %op1 to <32 x i32> - store <32 x i32> %res, <32 x i32>* %b + store <32 x i32> %res, ptr %b ret void } -define void @fcvtzs_v64f16_v64i32(<64 x half>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @fcvtzs_v64f16_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvtzs_v64f16_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1102,9 +1102,9 @@ define void @fcvtzs_v64f16_v64i32(<64 x half>* %a, <64 x i32>* %b) vscale_range( ; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a + %op1 = load <64 x half>, ptr %a %res = fptosi <64 x half> %op1 to <64 x i32> - store <64 x i32> %res, <64 x i32>* %b + store <64 x i32> %res, ptr %b ret void } @@ -1138,7 +1138,7 @@ define <2 x i64> @fcvtzs_v2f16_v2i64(<2 x half> %op1) vscale_range(2,0) #0 { ret <2 x i64> %res } -define void @fcvtzs_v4f16_v4i64(<4 x half>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @fcvtzs_v4f16_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzs_v4f16_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -1148,13 +1148,13 @@ define void @fcvtzs_v4f16_v4i64(<4 x half>* %a, <4 x i64>* %b) vscale_range(2,0) ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x half>, <4 x half>* %a + %op1 = load <4 x half>, ptr %a %res = fptosi <4 x half> %op1 to <4 x i64> - store <4 x i64> %res, <4 x i64>* %b + store <4 x i64> %res, ptr %b ret void } -define void @fcvtzs_v8f16_v8i64(<8 x half>* %a, <8 x i64>* %b) #0 { +define void @fcvtzs_v8f16_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvtzs_v8f16_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ldr q0, [x0] @@ -1180,13 +1180,13 @@ define void @fcvtzs_v8f16_v8i64(<8 x half>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: fcvtzs z0.d, p0/m, z0.h ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x half>, <8 x half>* %a + %op1 = load <8 x half>, ptr %a %res = fptosi <8 x half> %op1 to <8 x i64> - store <8 x i64> %res, <8 x i64>* %b + store <8 x i64> %res, ptr %b ret void } -define void @fcvtzs_v16f16_v16i64(<16 x half>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @fcvtzs_v16f16_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvtzs_v16f16_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1194,13 +1194,13 @@ define void @fcvtzs_v16f16_v16i64(<16 x half>* %a, <16 x i64>* %b) vscale_range( ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a + %op1 = load <16 x half>, ptr %a %res = fptosi <16 x half> %op1 to <16 x i64> - store <16 x i64> %res, <16 x i64>* %b + store <16 x i64> %res, ptr %b ret void } -define void @fcvtzs_v32f16_v32i64(<32 x half>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @fcvtzs_v32f16_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvtzs_v32f16_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1208,9 +1208,9 @@ define void @fcvtzs_v32f16_v32i64(<32 x half>* %a, <32 x i64>* %b) vscale_range( ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a + %op1 = load <32 x half>, ptr %a %res = fptosi <32 x half> %op1 to <32 x i64> - store <32 x i64> %res, <32 x i64>* %b + store <32 x i64> %res, ptr %b ret void } @@ -1246,7 +1246,7 @@ define <4 x i16> @fcvtzs_v4f32_v4i16(<4 x float> %op1) vscale_range(2,0) #0 { ret <4 x i16> %res } -define <8 x i16> @fcvtzs_v8f32_v8i16(<8 x float>* %a) vscale_range(2,0) #0 { +define <8 x i16> @fcvtzs_v8f32_v8i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzs_v8f32_v8i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1256,12 +1256,12 @@ define <8 x i16> @fcvtzs_v8f32_v8i16(<8 x float>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a + %op1 = load <8 x float>, ptr %a %res = fptosi <8 x float> %op1 to <8 x i16> ret <8 x i16> %res } -define void @fcvtzs_v16f32_v16i16(<16 x float>* %a, <16 x i16>* %b) #0 { +define void @fcvtzs_v16f32_v16i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvtzs_v16f32_v16i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1287,13 +1287,13 @@ define void @fcvtzs_v16f32_v16i16(<16 x float>* %a, <16 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: fcvtzs z0.s, p1/m, z0.s ; VBITS_GE_512-NEXT: st1h { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a + %op1 = load <16 x float>, ptr %a %res = fptosi <16 x float> %op1 to <16 x i16> - store <16 x i16> %res, <16 x i16>* %b + store <16 x i16> %res, ptr %b ret void } -define void @fcvtzs_v32f32_v32i16(<32 x float>* %a, <32 x i16>* %b) vscale_range(8,0) #0 { +define void @fcvtzs_v32f32_v32i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvtzs_v32f32_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1302,13 +1302,13 @@ define void @fcvtzs_v32f32_v32i16(<32 x float>* %a, <32 x i16>* %b) vscale_range ; CHECK-NEXT: fcvtzs z0.s, p1/m, z0.s ; CHECK-NEXT: st1h { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a + %op1 = load <32 x float>, ptr %a %res = fptosi <32 x float> %op1 to <32 x i16> - store <32 x i16> %res, <32 x i16>* %b + store <32 x i16> %res, ptr %b ret void } -define void @fcvtzs_v64f32_v64i16(<64 x float>* %a, <64 x i16>* %b) vscale_range(16,0) #0 { +define void @fcvtzs_v64f32_v64i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvtzs_v64f32_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1317,9 +1317,9 @@ define void @fcvtzs_v64f32_v64i16(<64 x float>* %a, <64 x i16>* %b) vscale_range ; CHECK-NEXT: fcvtzs z0.s, p1/m, z0.s ; CHECK-NEXT: st1h { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a + %op1 = load <64 x float>, ptr %a %res = fptosi <64 x float> %op1 to <64 x i16> - store <64 x i16> %res, <64 x i16>* %b + store <64 x i16> %res, ptr %b ret void } @@ -1347,7 +1347,7 @@ define <4 x i32> @fcvtzs_v4f32_v4i32(<4 x float> %op1) vscale_range(2,0) #0 { ret <4 x i32> %res } -define void @fcvtzs_v8f32_v8i32(<8 x float>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @fcvtzs_v8f32_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzs_v8f32_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1355,13 +1355,13 @@ define void @fcvtzs_v8f32_v8i32(<8 x float>* %a, <8 x i32>* %b) vscale_range(2,0 ; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a + %op1 = load <8 x float>, ptr %a %res = fptosi <8 x float> %op1 to <8 x i32> - store <8 x i32> %res, <8 x i32>* %b + store <8 x i32> %res, ptr %b ret void } -define void @fcvtzs_v16f32_v16i32(<16 x float>* %a, <16 x i32>* %b) #0 { +define void @fcvtzs_v16f32_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvtzs_v16f32_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1381,13 +1381,13 @@ define void @fcvtzs_v16f32_v16i32(<16 x float>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: fcvtzs z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a + %op1 = load <16 x float>, ptr %a %res = fptosi <16 x float> %op1 to <16 x i32> - store <16 x i32> %res, <16 x i32>* %b + store <16 x i32> %res, ptr %b ret void } -define void @fcvtzs_v32f32_v32i32(<32 x float>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @fcvtzs_v32f32_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvtzs_v32f32_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1395,13 +1395,13 @@ define void @fcvtzs_v32f32_v32i32(<32 x float>* %a, <32 x i32>* %b) vscale_range ; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a + %op1 = load <32 x float>, ptr %a %res = fptosi <32 x float> %op1 to <32 x i32> - store <32 x i32> %res, <32 x i32>* %b + store <32 x i32> %res, ptr %b ret void } -define void @fcvtzs_v64f32_v64i32(<64 x float>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @fcvtzs_v64f32_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvtzs_v64f32_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1409,9 +1409,9 @@ define void @fcvtzs_v64f32_v64i32(<64 x float>* %a, <64 x i32>* %b) vscale_range ; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a + %op1 = load <64 x float>, ptr %a %res = fptosi <64 x float> %op1 to <64 x i32> - store <64 x i32> %res, <64 x i32>* %b + store <64 x i32> %res, ptr %b ret void } @@ -1442,7 +1442,7 @@ define <2 x i64> @fcvtzs_v2f32_v2i64(<2 x float> %op1) vscale_range(2,0) #0 { ret <2 x i64> %res } -define void @fcvtzs_v4f32_v4i64(<4 x float>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @fcvtzs_v4f32_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzs_v4f32_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -1451,13 +1451,13 @@ define void @fcvtzs_v4f32_v4i64(<4 x float>* %a, <4 x i64>* %b) vscale_range(2,0 ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x float>, <4 x float>* %a + %op1 = load <4 x float>, ptr %a %res = fptosi <4 x float> %op1 to <4 x i64> - store <4 x i64> %res, <4 x i64>* %b + store <4 x i64> %res, ptr %b ret void } -define void @fcvtzs_v8f32_v8i64(<8 x float>* %a, <8 x i64>* %b) #0 { +define void @fcvtzs_v8f32_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvtzs_v8f32_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.s, vl8 @@ -1480,13 +1480,13 @@ define void @fcvtzs_v8f32_v8i64(<8 x float>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: fcvtzs z0.d, p0/m, z0.s ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a + %op1 = load <8 x float>, ptr %a %res = fptosi <8 x float> %op1 to <8 x i64> - store <8 x i64> %res, <8 x i64>* %b + store <8 x i64> %res, ptr %b ret void } -define void @fcvtzs_v16f32_v16i64(<16 x float>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @fcvtzs_v16f32_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvtzs_v16f32_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1494,13 +1494,13 @@ define void @fcvtzs_v16f32_v16i64(<16 x float>* %a, <16 x i64>* %b) vscale_range ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a + %op1 = load <16 x float>, ptr %a %res = fptosi <16 x float> %op1 to <16 x i64> - store <16 x i64> %res, <16 x i64>* %b + store <16 x i64> %res, ptr %b ret void } -define void @fcvtzs_v32f32_v32i64(<32 x float>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @fcvtzs_v32f32_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvtzs_v32f32_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1508,9 +1508,9 @@ define void @fcvtzs_v32f32_v32i64(<32 x float>* %a, <32 x i64>* %b) vscale_range ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a + %op1 = load <32 x float>, ptr %a %res = fptosi <32 x float> %op1 to <32 x i64> - store <32 x i64> %res, <32 x i64>* %b + store <32 x i64> %res, ptr %b ret void } @@ -1545,7 +1545,7 @@ define <2 x i16> @fcvtzs_v2f64_v2i16(<2 x double> %op1) vscale_range(2,0) #0 { ret <2 x i16> %res } -define <4 x i16> @fcvtzs_v4f64_v4i16(<4 x double>* %a) vscale_range(2,0) #0 { +define <4 x i16> @fcvtzs_v4f64_v4i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzs_v4f64_v4i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1556,12 +1556,12 @@ define <4 x i16> @fcvtzs_v4f64_v4i16(<4 x double>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a + %op1 = load <4 x double>, ptr %a %res = fptosi <4 x double> %op1 to <4 x i16> ret <4 x i16> %res } -define <8 x i16> @fcvtzs_v8f64_v8i16(<8 x double>* %a) #0 { +define <8 x i16> @fcvtzs_v8f64_v8i16(ptr %a) #0 { ; VBITS_GE_256-LABEL: fcvtzs_v8f64_v8i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1589,12 +1589,12 @@ define <8 x i16> @fcvtzs_v8f64_v8i16(<8 x double>* %a) #0 { ; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h ; VBITS_GE_512-NEXT: // kill: def $q0 killed $q0 killed $z0 ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a + %op1 = load <8 x double>, ptr %a %res = fptosi <8 x double> %op1 to <8 x i16> ret <8 x i16> %res } -define void @fcvtzs_v16f64_v16i16(<16 x double>* %a, <16 x i16>* %b) vscale_range(8,0) #0 { +define void @fcvtzs_v16f64_v16i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvtzs_v16f64_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1603,13 +1603,13 @@ define void @fcvtzs_v16f64_v16i16(<16 x double>* %a, <16 x i16>* %b) vscale_rang ; CHECK-NEXT: fcvtzs z0.d, p1/m, z0.d ; CHECK-NEXT: st1h { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a + %op1 = load <16 x double>, ptr %a %res = fptosi <16 x double> %op1 to <16 x i16> - store <16 x i16> %res, <16 x i16>* %b + store <16 x i16> %res, ptr %b ret void } -define void @fcvtzs_v32f64_v32i16(<32 x double>* %a, <32 x i16>* %b) vscale_range(16,0) #0 { +define void @fcvtzs_v32f64_v32i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvtzs_v32f64_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1618,9 +1618,9 @@ define void @fcvtzs_v32f64_v32i16(<32 x double>* %a, <32 x i16>* %b) vscale_rang ; CHECK-NEXT: fcvtzs z0.d, p1/m, z0.d ; CHECK-NEXT: st1h { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a + %op1 = load <32 x double>, ptr %a %res = fptosi <32 x double> %op1 to <32 x i16> - store <32 x i16> %res, <32 x i16>* %b + store <32 x i16> %res, ptr %b ret void } @@ -1651,7 +1651,7 @@ define <2 x i32> @fcvtzs_v2f64_v2i32(<2 x double> %op1) vscale_range(2,0) #0 { ret <2 x i32> %res } -define <4 x i32> @fcvtzs_v4f64_v4i32(<4 x double>* %a) vscale_range(2,0) #0 { +define <4 x i32> @fcvtzs_v4f64_v4i32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzs_v4f64_v4i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1661,12 +1661,12 @@ define <4 x i32> @fcvtzs_v4f64_v4i32(<4 x double>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a + %op1 = load <4 x double>, ptr %a %res = fptosi <4 x double> %op1 to <4 x i32> ret <4 x i32> %res } -define void @fcvtzs_v8f64_v8i32(<8 x double>* %a, <8 x i32>* %b) #0 { +define void @fcvtzs_v8f64_v8i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvtzs_v8f64_v8i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1692,13 +1692,13 @@ define void @fcvtzs_v8f64_v8i32(<8 x double>* %a, <8 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: fcvtzs z0.d, p1/m, z0.d ; VBITS_GE_512-NEXT: st1w { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a + %op1 = load <8 x double>, ptr %a %res = fptosi <8 x double> %op1 to <8 x i32> - store <8 x i32> %res, <8 x i32>* %b + store <8 x i32> %res, ptr %b ret void } -define void @fcvtzs_v16f64_v16i32(<16 x double>* %a, <16 x i32>* %b) vscale_range(8,0) #0 { +define void @fcvtzs_v16f64_v16i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvtzs_v16f64_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1707,13 +1707,13 @@ define void @fcvtzs_v16f64_v16i32(<16 x double>* %a, <16 x i32>* %b) vscale_rang ; CHECK-NEXT: fcvtzs z0.d, p1/m, z0.d ; CHECK-NEXT: st1w { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a + %op1 = load <16 x double>, ptr %a %res = fptosi <16 x double> %op1 to <16 x i32> - store <16 x i32> %res, <16 x i32>* %b + store <16 x i32> %res, ptr %b ret void } -define void @fcvtzs_v32f64_v32i32(<32 x double>* %a, <32 x i32>* %b) vscale_range(16,0) #0 { +define void @fcvtzs_v32f64_v32i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvtzs_v32f64_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1722,9 +1722,9 @@ define void @fcvtzs_v32f64_v32i32(<32 x double>* %a, <32 x i32>* %b) vscale_rang ; CHECK-NEXT: fcvtzs z0.d, p1/m, z0.d ; CHECK-NEXT: st1w { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a + %op1 = load <32 x double>, ptr %a %res = fptosi <32 x double> %op1 to <32 x i32> - store <32 x i32> %res, <32 x i32>* %b + store <32 x i32> %res, ptr %b ret void } @@ -1753,7 +1753,7 @@ define <2 x i64> @fcvtzs_v2f64_v2i64(<2 x double> %op1) vscale_range(2,0) #0 { ret <2 x i64> %res } -define void @fcvtzs_v4f64_v4i64(<4 x double>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @fcvtzs_v4f64_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: fcvtzs_v4f64_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1761,13 +1761,13 @@ define void @fcvtzs_v4f64_v4i64(<4 x double>* %a, <4 x i64>* %b) vscale_range(2, ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a + %op1 = load <4 x double>, ptr %a %res = fptosi <4 x double> %op1 to <4 x i64> - store <4 x i64> %res, <4 x i64>* %b + store <4 x i64> %res, ptr %b ret void } -define void @fcvtzs_v8f64_v8i64(<8 x double>* %a, <8 x i64>* %b) #0 { +define void @fcvtzs_v8f64_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: fcvtzs_v8f64_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1787,13 +1787,13 @@ define void @fcvtzs_v8f64_v8i64(<8 x double>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: fcvtzs z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a + %op1 = load <8 x double>, ptr %a %res = fptosi <8 x double> %op1 to <8 x i64> - store <8 x i64> %res, <8 x i64>* %b + store <8 x i64> %res, ptr %b ret void } -define void @fcvtzs_v16f64_v16i64(<16 x double>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @fcvtzs_v16f64_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: fcvtzs_v16f64_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1801,13 +1801,13 @@ define void @fcvtzs_v16f64_v16i64(<16 x double>* %a, <16 x i64>* %b) vscale_rang ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a + %op1 = load <16 x double>, ptr %a %res = fptosi <16 x double> %op1 to <16 x i64> - store <16 x i64> %res, <16 x i64>* %b + store <16 x i64> %res, ptr %b ret void } -define void @fcvtzs_v32f64_v32i64(<32 x double>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @fcvtzs_v32f64_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: fcvtzs_v32f64_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1815,9 +1815,9 @@ define void @fcvtzs_v32f64_v32i64(<32 x double>* %a, <32 x i64>* %b) vscale_rang ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a + %op1 = load <32 x double>, ptr %a %res = fptosi <32 x double> %op1 to <32 x i64> - store <32 x i64> %res, <32 x i64>* %b + store <32 x i64> %res, ptr %b ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll index 73e6693..d79ef79 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll @@ -30,7 +30,7 @@ define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x i1> %mask ret <8 x half> %sel } -define void @select_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 { +define void @select_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: select_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -40,15 +40,15 @@ define void @select_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) # ; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %mask = fcmp oeq <16 x half> %op1, %op2 %sel = select <16 x i1> %mask, <16 x half> %op1, <16 x half> %op2 - store <16 x half> %sel, <16 x half>* %a + store <16 x half> %sel, ptr %a ret void } -define void @select_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { +define void @select_v32f16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: select_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -74,15 +74,15 @@ define void @select_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { ; VBITS_GE_512-NEXT: sel z0.h, p1, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a - %op2 = load <32 x half>, <32 x half>* %b + %op1 = load <32 x half>, ptr %a + %op2 = load <32 x half>, ptr %b %mask = fcmp oeq <32 x half> %op1, %op2 %sel = select <32 x i1> %mask, <32 x half> %op1, <32 x half> %op2 - store <32 x half> %sel, <32 x half>* %a + store <32 x half> %sel, ptr %a ret void } -define void @select_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) #0 { +define void @select_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: select_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -92,15 +92,15 @@ define void @select_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) # ; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a - %op2 = load <64 x half>, <64 x half>* %b + %op1 = load <64 x half>, ptr %a + %op2 = load <64 x half>, ptr %b %mask = fcmp oeq <64 x half> %op1, %op2 %sel = select <64 x i1> %mask, <64 x half> %op1, <64 x half> %op2 - store <64 x half> %sel, <64 x half>* %a + store <64 x half> %sel, ptr %a ret void } -define void @select_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16,0) #0 { +define void @select_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: select_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -110,11 +110,11 @@ define void @select_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16, ; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x half>, <128 x half>* %a - %op2 = load <128 x half>, <128 x half>* %b + %op1 = load <128 x half>, ptr %a + %op2 = load <128 x half>, ptr %b %mask = fcmp oeq <128 x half> %op1, %op2 %sel = select <128 x i1> %mask, <128 x half> %op1, <128 x half> %op2 - store <128 x half> %sel, <128 x half>* %a + store <128 x half> %sel, ptr %a ret void } @@ -143,7 +143,7 @@ define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x i1> %m ret <4 x float> %sel } -define void @select_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 { +define void @select_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: select_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -153,15 +153,15 @@ define void @select_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a - %op2 = load <8 x float>, <8 x float>* %b + %op1 = load <8 x float>, ptr %a + %op2 = load <8 x float>, ptr %b %mask = fcmp oeq <8 x float> %op1, %op2 %sel = select <8 x i1> %mask, <8 x float> %op1, <8 x float> %op2 - store <8 x float> %sel, <8 x float>* %a + store <8 x float> %sel, ptr %a ret void } -define void @select_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { +define void @select_v16f32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: select_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -187,15 +187,15 @@ define void @select_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { ; VBITS_GE_512-NEXT: sel z0.s, p1, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a - %op2 = load <16 x float>, <16 x float>* %b + %op1 = load <16 x float>, ptr %a + %op2 = load <16 x float>, ptr %b %mask = fcmp oeq <16 x float> %op1, %op2 %sel = select <16 x i1> %mask, <16 x float> %op1, <16 x float> %op2 - store <16 x float> %sel, <16 x float>* %a + store <16 x float> %sel, ptr %a ret void } -define void @select_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) #0 { +define void @select_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: select_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -205,15 +205,15 @@ define void @select_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) ; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a - %op2 = load <32 x float>, <32 x float>* %b + %op1 = load <32 x float>, ptr %a + %op2 = load <32 x float>, ptr %b %mask = fcmp oeq <32 x float> %op1, %op2 %sel = select <32 x i1> %mask, <32 x float> %op1, <32 x float> %op2 - store <32 x float> %sel, <32 x float>* %a + store <32 x float> %sel, ptr %a ret void } -define void @select_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0) #0 { +define void @select_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: select_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -223,11 +223,11 @@ define void @select_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0 ; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a - %op2 = load <64 x float>, <64 x float>* %b + %op1 = load <64 x float>, ptr %a + %op2 = load <64 x float>, ptr %b %mask = fcmp oeq <64 x float> %op1, %op2 %sel = select <64 x i1> %mask, <64 x float> %op1, <64 x float> %op2 - store <64 x float> %sel, <64 x float>* %a + store <64 x float> %sel, ptr %a ret void } @@ -257,7 +257,7 @@ define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x i1> ret <2 x double> %sel } -define void @select_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @select_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: select_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -267,15 +267,15 @@ define void @select_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) ; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a - %op2 = load <4 x double>, <4 x double>* %b + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b %mask = fcmp oeq <4 x double> %op1, %op2 %sel = select <4 x i1> %mask, <4 x double> %op1, <4 x double> %op2 - store <4 x double> %sel, <4 x double>* %a + store <4 x double> %sel, ptr %a ret void } -define void @select_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { +define void @select_v8f64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: select_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -301,15 +301,15 @@ define void @select_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: sel z0.d, p1, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a - %op2 = load <8 x double>, <8 x double>* %b + %op1 = load <8 x double>, ptr %a + %op2 = load <8 x double>, ptr %b %mask = fcmp oeq <8 x double> %op1, %op2 %sel = select <8 x i1> %mask, <8 x double> %op1, <8 x double> %op2 - store <8 x double> %sel, <8 x double>* %a + store <8 x double> %sel, ptr %a ret void } -define void @select_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @select_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: select_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -319,15 +319,15 @@ define void @select_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8, ; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a - %op2 = load <16 x double>, <16 x double>* %b + %op1 = load <16 x double>, ptr %a + %op2 = load <16 x double>, ptr %b %mask = fcmp oeq <16 x double> %op1, %op2 %sel = select <16 x i1> %mask, <16 x double> %op1, <16 x double> %op2 - store <16 x double> %sel, <16 x double>* %a + store <16 x double> %sel, ptr %a ret void } -define void @select_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @select_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: select_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -337,11 +337,11 @@ define void @select_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16 ; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a - %op2 = load <32 x double>, <32 x double>* %b + %op1 = load <32 x double>, ptr %a + %op2 = load <32 x double>, ptr %b %mask = fcmp oeq <32 x double> %op1, %op2 %sel = select <32 x i1> %mask, <32 x double> %op1, <32 x double> %op2 - store <32 x double> %sel, <32 x double>* %a + store <32 x double> %sel, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests-crash.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests-crash.ll index 235538f..4dc3c5e 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests-crash.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests-crash.ll @@ -8,7 +8,7 @@ target triple = "aarch64-unknown-linux-gnu" ; too many extra vregs during frame lowering, when we don't have an emergency ; spill slot. -define dso_local void @func1(i64* %v1, i64* %v2, i64* %v3, i64* %v4, i64* %v5, i64* %v6, i64* %v7, i64* %v8, +define dso_local void @func1(ptr %v1, ptr %v2, ptr %v3, ptr %v4, ptr %v5, ptr %v6, ptr %v7, ptr %v8, ; CHECK-LABEL: func1: ; CHECK: // %bb.0: ; CHECK-NEXT: str x25, [sp, #-64]! // 8-byte Folded Spill @@ -63,28 +63,28 @@ define dso_local void @func1(i64* %v1, i64* %v2, i64* %v3, i64* %v4, i64* %v5, i ; CHECK-NEXT: str x8, [sp, #352] ; CHECK-NEXT: ldr x25, [sp], #64 // 8-byte Folded Reload ; CHECK-NEXT: b func2 - i64* %v9, i64* %v10, i64* %v11, i64* %v12, i64* %v13, i64* %v14, i64* %v15, i64* %v16, - i64* %v17, i64* %v18, i64* %v19, i64* %v20, i64* %v21, i64* %v22, i64* %v23, i64* %v24, - i64* %v25, i64* %v26, i64* %v27, i64* %v28, i64* %v29, i64* %v30, i64* %v31, i64* %v32, - i64* %v33, i64* %v34, i64* %v35, i64* %v36, i64* %v37, i64* %v38, i64* %v39, i64* %v40, - i64* %v41, i64* %v42, i64* %v43, i64* %v44, i64* %v45, i64* %v46, i64* %v47, i64* %v48, + ptr %v9, ptr %v10, ptr %v11, ptr %v12, ptr %v13, ptr %v14, ptr %v15, ptr %v16, + ptr %v17, ptr %v18, ptr %v19, ptr %v20, ptr %v21, ptr %v22, ptr %v23, ptr %v24, + ptr %v25, ptr %v26, ptr %v27, ptr %v28, ptr %v29, ptr %v30, ptr %v31, ptr %v32, + ptr %v33, ptr %v34, ptr %v35, ptr %v36, ptr %v37, ptr %v38, ptr %v39, ptr %v40, + ptr %v41, ptr %v42, ptr %v43, ptr %v44, ptr %v45, ptr %v46, ptr %v47, ptr %v48, i64 %v49) #0 { - tail call void @func2(i64* %v1, i64* %v2, i64* %v3, i64* %v4, i64* %v5, i64* %v6, i64* %v7, i64* %v8, - i64* %v9, i64* %v10, i64* %v11, i64* %v12, i64* undef, i64* %v14, i64* %v15, i64* %v16, - i64* %v17, i64* %v18, i64* %v19, i64* %v20, i64* %v21, i64* %v22, i64* %v23, i64* %v24, - i64* %v25, i64* %v26, i64* %v27, i64* %v28, i64* %v29, i64* %v30, i64* undef, i64* undef, - i64* undef, i64* undef, i64* undef, i64* undef, i64* %v37, i64* %v38, i64* %v39, i64* %v40, - i64* %v41, i64* %v42, i64* %v43, i64* %v44, i64* %v45, i64* undef, i64* %v47, i64* %v48, + tail call void @func2(ptr %v1, ptr %v2, ptr %v3, ptr %v4, ptr %v5, ptr %v6, ptr %v7, ptr %v8, + ptr %v9, ptr %v10, ptr %v11, ptr %v12, ptr undef, ptr %v14, ptr %v15, ptr %v16, + ptr %v17, ptr %v18, ptr %v19, ptr %v20, ptr %v21, ptr %v22, ptr %v23, ptr %v24, + ptr %v25, ptr %v26, ptr %v27, ptr %v28, ptr %v29, ptr %v30, ptr undef, ptr undef, + ptr undef, ptr undef, ptr undef, ptr undef, ptr %v37, ptr %v38, ptr %v39, ptr %v40, + ptr %v41, ptr %v42, ptr %v43, ptr %v44, ptr %v45, ptr undef, ptr %v47, ptr %v48, i64 undef) ret void } -declare dso_local void @func2(i64*, i64*, i64*, i64*, i64*, i64*, i64*, i64*, - i64*, i64*, i64*, i64*, i64*, i64*, i64*, i64*, - i64*, i64*, i64*, i64*, i64*, i64*, i64*, i64*, - i64*, i64*, i64*, i64*, i64*, i64*, i64*, i64*, - i64*, i64*, i64*, i64*, i64*, i64*, i64*, i64*, - i64*, i64*, i64*, i64*, i64*, i64*, i64*, i64*, +declare dso_local void @func2(ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, + ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, + ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, + ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, + ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, + ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i64) attributes #0 = { "target-features"="+sve" vscale_range(2,2) } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests.ll index 62681cd..320d171 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests.ll @@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu" ; Ensure that only no offset frame indexes are folded into SVE load/stores when ; accessing fixed width objects. -define void @foo(<8 x i64>* %a) #0 { +define void @foo(ptr %a) #0 { ; CHECK-LABEL: foo: ; CHECK: SelectionDAG has 14 nodes: ; CHECK-NEXT: t0: ch,glue = EntryToken @@ -22,9 +22,9 @@ define void @foo(<8 x i64>* %a) #0 { entry: %r0 = alloca <8 x i64> %r1 = alloca <8 x i64> - %r = load volatile <8 x i64>, <8 x i64>* %a - store volatile <8 x i64> %r, <8 x i64>* %r0 - store volatile <8 x i64> %r, <8 x i64>* %r1 + %r = load volatile <8 x i64>, ptr %a + store volatile <8 x i64> %r, ptr %r0 + store volatile <8 x i64> %r, ptr %r1 ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll index 456d9fe..4fdeb81 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll @@ -33,7 +33,7 @@ define <8 x half> @insertelement_v8f16(<8 x half> %op1) vscale_range(2,0) #0 { ret <8 x half> %r } -define <16 x half> @insertelement_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { +define <16 x half> @insertelement_v16f16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: insertelement_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w9, #15 @@ -47,12 +47,12 @@ define <16 x half> @insertelement_v16f16(<16 x half>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: mov z0.h, p1/m, h2 ; CHECK-NEXT: st1h { z0.h }, p0, [x8] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a + %op1 = load <16 x half>, ptr %a %r = insertelement <16 x half> %op1, half 5.0, i64 15 ret <16 x half> %r } -define <32 x half> @insertelement_v32f16(<32 x half>* %a) #0 { +define <32 x half> @insertelement_v32f16(ptr %a) #0 { ; VBITS_GE_256-LABEL: insertelement_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #16 @@ -83,12 +83,12 @@ define <32 x half> @insertelement_v32f16(<32 x half>* %a) #0 { ; VBITS_GE_512-NEXT: mov z0.h, p1/m, h2 ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a + %op1 = load <32 x half>, ptr %a %r = insertelement <32 x half> %op1, half 5.0, i64 31 ret <32 x half> %r } -define <64 x half> @insertelement_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { +define <64 x half> @insertelement_v64f16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: insertelement_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w9, #63 @@ -102,12 +102,12 @@ define <64 x half> @insertelement_v64f16(<64 x half>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: mov z0.h, p1/m, h2 ; CHECK-NEXT: st1h { z0.h }, p0, [x8] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a + %op1 = load <64 x half>, ptr %a %r = insertelement <64 x half> %op1, half 5.0, i64 63 ret <64 x half> %r } -define <128 x half> @insertelement_v128f16(<128 x half>* %a) vscale_range(16,0) #0 { +define <128 x half> @insertelement_v128f16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: insertelement_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w9, #127 @@ -121,7 +121,7 @@ define <128 x half> @insertelement_v128f16(<128 x half>* %a) vscale_range(16,0) ; CHECK-NEXT: mov z0.h, p1/m, h2 ; CHECK-NEXT: st1h { z0.h }, p0, [x8] ; CHECK-NEXT: ret - %op1 = load <128 x half>, <128 x half>* %a + %op1 = load <128 x half>, ptr %a %r = insertelement <128 x half> %op1, half 5.0, i64 127 ret <128 x half> %r } @@ -150,7 +150,7 @@ define <4 x float> @insertelement_v4f32(<4 x float> %op1) vscale_range(2,0) #0 { ret <4 x float> %r } -define <8 x float> @insertelement_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { +define <8 x float> @insertelement_v8f32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: insertelement_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w9, #7 @@ -164,12 +164,12 @@ define <8 x float> @insertelement_v8f32(<8 x float>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: mov z0.s, p1/m, s2 ; CHECK-NEXT: st1w { z0.s }, p0, [x8] ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a + %op1 = load <8 x float>, ptr %a %r = insertelement <8 x float> %op1, float 5.0, i64 7 ret <8 x float> %r } -define <16 x float> @insertelement_v16f32(<16 x float>* %a) #0 { +define <16 x float> @insertelement_v16f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: insertelement_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #8 @@ -200,12 +200,12 @@ define <16 x float> @insertelement_v16f32(<16 x float>* %a) #0 { ; VBITS_GE_512-NEXT: mov z0.s, p1/m, s2 ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a + %op1 = load <16 x float>, ptr %a %r = insertelement <16 x float> %op1, float 5.0, i64 15 ret <16 x float> %r } -define <32 x float> @insertelement_v32f32(<32 x float>* %a) vscale_range(8,0) #0 { +define <32 x float> @insertelement_v32f32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: insertelement_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w9, #31 @@ -219,12 +219,12 @@ define <32 x float> @insertelement_v32f32(<32 x float>* %a) vscale_range(8,0) #0 ; CHECK-NEXT: mov z0.s, p1/m, s2 ; CHECK-NEXT: st1w { z0.s }, p0, [x8] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a + %op1 = load <32 x float>, ptr %a %r = insertelement <32 x float> %op1, float 5.0, i64 31 ret <32 x float> %r } -define <64 x float> @insertelement_v64f32(<64 x float>* %a) vscale_range(16,0) #0 { +define <64 x float> @insertelement_v64f32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: insertelement_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w9, #63 @@ -238,7 +238,7 @@ define <64 x float> @insertelement_v64f32(<64 x float>* %a) vscale_range(16,0) # ; CHECK-NEXT: mov z0.s, p1/m, s2 ; CHECK-NEXT: st1w { z0.s }, p0, [x8] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a + %op1 = load <64 x float>, ptr %a %r = insertelement <64 x float> %op1, float 5.0, i64 63 ret <64 x float> %r } @@ -265,7 +265,7 @@ define <2 x double> @insertelement_v2f64(<2 x double> %op1) vscale_range(2,0) #0 ret <2 x double> %r } -define <4 x double> @insertelement_v4f64(<4 x double>* %a) vscale_range(2,0) #0 { +define <4 x double> @insertelement_v4f64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: insertelement_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w9, #3 @@ -279,12 +279,12 @@ define <4 x double> @insertelement_v4f64(<4 x double>* %a) vscale_range(2,0) #0 ; CHECK-NEXT: mov z0.d, p1/m, d2 ; CHECK-NEXT: st1d { z0.d }, p0, [x8] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a + %op1 = load <4 x double>, ptr %a %r = insertelement <4 x double> %op1, double 5.0, i64 3 ret <4 x double> %r } -define <8 x double> @insertelement_v8f64(<8 x double>* %a) #0 { +define <8 x double> @insertelement_v8f64(ptr %a) #0 { ; VBITS_GE_256-LABEL: insertelement_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #4 @@ -315,12 +315,12 @@ define <8 x double> @insertelement_v8f64(<8 x double>* %a) #0 { ; VBITS_GE_512-NEXT: mov z0.d, p1/m, d2 ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a + %op1 = load <8 x double>, ptr %a %r = insertelement <8 x double> %op1, double 5.0, i64 7 ret <8 x double> %r } -define <16 x double> @insertelement_v16f64(<16 x double>* %a) vscale_range(8,0) #0 { +define <16 x double> @insertelement_v16f64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: insertelement_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w9, #15 @@ -334,12 +334,12 @@ define <16 x double> @insertelement_v16f64(<16 x double>* %a) vscale_range(8,0) ; CHECK-NEXT: mov z0.d, p1/m, d2 ; CHECK-NEXT: st1d { z0.d }, p0, [x8] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a + %op1 = load <16 x double>, ptr %a %r = insertelement <16 x double> %op1, double 5.0, i64 15 ret <16 x double> %r } -define <32 x double> @insertelement_v32f64(<32 x double>* %a) vscale_range(16,0) #0 { +define <32 x double> @insertelement_v32f64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: insertelement_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w9, #31 @@ -353,7 +353,7 @@ define <32 x double> @insertelement_v32f64(<32 x double>* %a) vscale_range(16,0) ; CHECK-NEXT: mov z0.d, p1/m, d2 ; CHECK-NEXT: st1d { z0.d }, p0, [x8] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a + %op1 = load <32 x double>, ptr %a %r = insertelement <32 x double> %op1, double 5.0, i64 31 ret <32 x double> %r } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll index 09d7595..91e0c62 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll @@ -29,7 +29,7 @@ define <16 x i8> @add_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) #0 ret <16 x i8> %res } -define void @add_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @add_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: add_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -38,14 +38,14 @@ define void @add_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: add z0.b, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %res = add <32 x i8> %op1, %op2 - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @add_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @add_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: add_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -68,14 +68,14 @@ define void @add_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: add z0.b, z0.b, z1.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = add <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @add_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @add_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: add_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -84,14 +84,14 @@ define void @add_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: add z0.b, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %res = add <128 x i8> %op1, %op2 - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @add_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @add_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: add_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -100,10 +100,10 @@ define void @add_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: add z0.b, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %res = add <256 x i8> %op1, %op2 - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -127,7 +127,7 @@ define <8 x i16> @add_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) #0 ret <8 x i16> %res } -define void @add_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @add_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: add_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -136,14 +136,14 @@ define void @add_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: add z0.h, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %res = add <16 x i16> %op1, %op2 - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @add_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @add_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: add_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -166,14 +166,14 @@ define void @add_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: add z0.h, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = add <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @add_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @add_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: add_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -182,14 +182,14 @@ define void @add_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: add z0.h, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %res = add <64 x i16> %op1, %op2 - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @add_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @add_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: add_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -198,10 +198,10 @@ define void @add_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 ; CHECK-NEXT: add z0.h, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %res = add <128 x i16> %op1, %op2 - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -225,7 +225,7 @@ define <4 x i32> @add_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) #0 ret <4 x i32> %res } -define void @add_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @add_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: add_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -234,14 +234,14 @@ define void @add_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: add z0.s, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %res = add <8 x i32> %op1, %op2 - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @add_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @add_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: add_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -264,14 +264,14 @@ define void @add_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: add z0.s, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %res = add <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @add_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @add_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: add_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -280,14 +280,14 @@ define void @add_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: add z0.s, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %res = add <32 x i32> %op1, %op2 - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @add_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @add_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: add_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -296,10 +296,10 @@ define void @add_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: add z0.s, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %res = add <64 x i32> %op1, %op2 - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -323,7 +323,7 @@ define <2 x i64> @add_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) #0 ret <2 x i64> %res } -define void @add_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @add_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: add_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -332,14 +332,14 @@ define void @add_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: add z0.d, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %res = add <4 x i64> %op1, %op2 - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @add_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @add_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: add_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -362,14 +362,14 @@ define void @add_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: add z0.d, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %res = add <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @add_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @add_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: add_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -378,14 +378,14 @@ define void @add_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: add z0.d, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %res = add <16 x i64> %op1, %op2 - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @add_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(8,0) #0 { +define void @add_v32i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: add_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: mov x8, #16 @@ -399,10 +399,10 @@ define void @add_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3] ; CHECK-NEXT: st1d { z1.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %res = add <32 x i64> %op1, %op2 - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } @@ -430,7 +430,7 @@ define <16 x i8> @mul_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) #0 ret <16 x i8> %res } -define void @mul_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @mul_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: mul_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -439,14 +439,14 @@ define void @mul_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: mul z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %res = mul <32 x i8> %op1, %op2 - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @mul_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @mul_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: mul_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -469,14 +469,14 @@ define void @mul_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: mul z0.b, p0/m, z0.b, z1.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = mul <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @mul_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @mul_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: mul_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -485,14 +485,14 @@ define void @mul_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: mul z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %res = mul <128 x i8> %op1, %op2 - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @mul_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @mul_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: mul_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -501,10 +501,10 @@ define void @mul_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: mul z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %res = mul <256 x i8> %op1, %op2 - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -528,7 +528,7 @@ define <8 x i16> @mul_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) #0 ret <8 x i16> %res } -define void @mul_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @mul_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: mul_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -537,14 +537,14 @@ define void @mul_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %res = mul <16 x i16> %op1, %op2 - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @mul_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @mul_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: mul_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -567,14 +567,14 @@ define void @mul_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: mul z0.h, p0/m, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = mul <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @mul_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @mul_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: mul_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -583,14 +583,14 @@ define void @mul_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %res = mul <64 x i16> %op1, %op2 - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @mul_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @mul_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: mul_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -599,10 +599,10 @@ define void @mul_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 ; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %res = mul <128 x i16> %op1, %op2 - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -626,7 +626,7 @@ define <4 x i32> @mul_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) #0 ret <4 x i32> %res } -define void @mul_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @mul_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: mul_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -635,14 +635,14 @@ define void @mul_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %res = mul <8 x i32> %op1, %op2 - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @mul_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @mul_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: mul_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -665,14 +665,14 @@ define void @mul_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: mul z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %res = mul <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @mul_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @mul_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: mul_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -681,14 +681,14 @@ define void @mul_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %res = mul <32 x i32> %op1, %op2 - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @mul_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @mul_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: mul_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -697,10 +697,10 @@ define void @mul_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %res = mul <64 x i32> %op1, %op2 - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -730,7 +730,7 @@ define <2 x i64> @mul_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 { ret <2 x i64> %res } -define void @mul_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @mul_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: mul_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -739,14 +739,14 @@ define void @mul_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %res = mul <4 x i64> %op1, %op2 - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @mul_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @mul_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: mul_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -769,14 +769,14 @@ define void @mul_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: mul z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %res = mul <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @mul_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @mul_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: mul_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -785,14 +785,14 @@ define void @mul_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %res = mul <16 x i64> %op1, %op2 - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @mul_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @mul_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: mul_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -801,10 +801,10 @@ define void @mul_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %res = mul <32 x i64> %op1, %op2 - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } @@ -832,7 +832,7 @@ define <16 x i8> @sub_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) #0 ret <16 x i8> %res } -define void @sub_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @sub_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: sub_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -841,14 +841,14 @@ define void @sub_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: sub z0.b, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %res = sub <32 x i8> %op1, %op2 - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @sub_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @sub_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: sub_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -871,14 +871,14 @@ define void @sub_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: sub z0.b, z0.b, z1.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = sub <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @sub_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @sub_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: sub_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -887,14 +887,14 @@ define void @sub_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: sub z0.b, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %res = sub <128 x i8> %op1, %op2 - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @sub_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @sub_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: sub_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -903,10 +903,10 @@ define void @sub_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: sub z0.b, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %res = sub <256 x i8> %op1, %op2 - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -930,7 +930,7 @@ define <8 x i16> @sub_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) #0 ret <8 x i16> %res } -define void @sub_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @sub_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: sub_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -939,14 +939,14 @@ define void @sub_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: sub z0.h, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %res = sub <16 x i16> %op1, %op2 - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @sub_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @sub_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: sub_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -969,14 +969,14 @@ define void @sub_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: sub z0.h, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = sub <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @sub_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @sub_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: sub_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -985,14 +985,14 @@ define void @sub_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: sub z0.h, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %res = sub <64 x i16> %op1, %op2 - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @sub_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @sub_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: sub_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1001,10 +1001,10 @@ define void @sub_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 ; CHECK-NEXT: sub z0.h, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %res = sub <128 x i16> %op1, %op2 - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -1028,7 +1028,7 @@ define <4 x i32> @sub_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) #0 ret <4 x i32> %res } -define void @sub_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @sub_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: sub_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1037,14 +1037,14 @@ define void @sub_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: sub z0.s, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %res = sub <8 x i32> %op1, %op2 - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @sub_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @sub_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: sub_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1067,14 +1067,14 @@ define void @sub_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: sub z0.s, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %res = sub <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @sub_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @sub_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: sub_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1083,14 +1083,14 @@ define void @sub_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: sub z0.s, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %res = sub <32 x i32> %op1, %op2 - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @sub_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @sub_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: sub_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1099,10 +1099,10 @@ define void @sub_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: sub z0.s, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %res = sub <64 x i32> %op1, %op2 - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -1126,7 +1126,7 @@ define <2 x i64> @sub_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) #0 ret <2 x i64> %res } -define void @sub_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @sub_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: sub_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1135,14 +1135,14 @@ define void @sub_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: sub z0.d, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %res = sub <4 x i64> %op1, %op2 - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @sub_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @sub_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: sub_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1165,14 +1165,14 @@ define void @sub_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: sub z0.d, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %res = sub <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @sub_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @sub_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: sub_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1181,14 +1181,14 @@ define void @sub_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: sub z0.d, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %res = sub <16 x i64> %op1, %op2 - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @sub_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @sub_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: sub_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1197,10 +1197,10 @@ define void @sub_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: sub z0.d, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %res = sub <32 x i64> %op1, %op2 - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } @@ -1229,7 +1229,7 @@ define <16 x i8> @abs_v16i8(<16 x i8> %op1) vscale_range(2,0) #0 { ret <16 x i8> %res } -define void @abs_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { +define void @abs_v32i8(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: abs_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -1237,13 +1237,13 @@ define void @abs_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: abs z0.b, p0/m, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a + %op1 = load <32 x i8>, ptr %a %res = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %op1, i1 false) - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @abs_v64i8(<64 x i8>* %a) #0 { +define void @abs_v64i8(ptr %a) #0 { ; VBITS_GE_256-LABEL: abs_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -1263,13 +1263,13 @@ define void @abs_v64i8(<64 x i8>* %a) #0 { ; VBITS_GE_512-NEXT: abs z0.b, p0/m, z0.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a + %op1 = load <64 x i8>, ptr %a %res = call <64 x i8> @llvm.abs.v64i8(<64 x i8> %op1, i1 false) - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @abs_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { +define void @abs_v128i8(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: abs_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -1277,13 +1277,13 @@ define void @abs_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: abs z0.b, p0/m, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a + %op1 = load <128 x i8>, ptr %a %res = call <128 x i8> @llvm.abs.v128i8(<128 x i8> %op1, i1 false) - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @abs_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { +define void @abs_v256i8(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: abs_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -1291,9 +1291,9 @@ define void @abs_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: abs z0.b, p0/m, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a + %op1 = load <256 x i8>, ptr %a %res = call <256 x i8> @llvm.abs.v256i8(<256 x i8> %op1, i1 false) - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -1317,7 +1317,7 @@ define <8 x i16> @abs_v8i16(<8 x i16> %op1) vscale_range(2,0) #0 { ret <8 x i16> %res } -define void @abs_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { +define void @abs_v16i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: abs_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -1325,13 +1325,13 @@ define void @abs_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: abs z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a + %op1 = load <16 x i16>, ptr %a %res = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %op1, i1 false) - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @abs_v32i16(<32 x i16>* %a) vscale_range(2,0) #0 { +define void @abs_v32i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: abs_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: mov x8, #16 @@ -1343,13 +1343,13 @@ define void @abs_v32i16(<32 x i16>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1] ; CHECK-NEXT: st1h { z1.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %res = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %op1, i1 false) - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @abs_v64i16(<64 x i16>* %a) vscale_range(2,0) #0 { +define void @abs_v64i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: abs_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: mov x8, #48 @@ -1369,13 +1369,13 @@ define void @abs_v64i16(<64 x i16>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: st1h { z1.h }, p0, [x0, x9, lsl #1] ; CHECK-NEXT: st1h { z3.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a + %op1 = load <64 x i16>, ptr %a %res = call <64 x i16> @llvm.abs.v64i16(<64 x i16> %op1, i1 false) - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @abs_v128i16(<128 x i16>* %a) vscale_range(2,0) #0 { +define void @abs_v128i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: abs_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: mov x8, #96 @@ -1411,9 +1411,9 @@ define void @abs_v128i16(<128 x i16>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: st1h { z1.h }, p0, [x0, x10, lsl #1] ; CHECK-NEXT: st1h { z7.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a + %op1 = load <128 x i16>, ptr %a %res = call <128 x i16> @llvm.abs.v128i16(<128 x i16> %op1, i1 false) - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -1437,7 +1437,7 @@ define <4 x i32> @abs_v4i32(<4 x i32> %op1) vscale_range(2,0) #0 { ret <4 x i32> %res } -define void @abs_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { +define void @abs_v8i32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: abs_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1445,13 +1445,13 @@ define void @abs_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: abs z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a + %op1 = load <8 x i32>, ptr %a %res = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %op1, i1 false) - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @abs_v16i32(<16 x i32>* %a) #0 { +define void @abs_v16i32(ptr %a) #0 { ; VBITS_GE_256-LABEL: abs_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1471,13 +1471,13 @@ define void @abs_v16i32(<16 x i32>* %a) #0 { ; VBITS_GE_512-NEXT: abs z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %res = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %op1, i1 false) - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @abs_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { +define void @abs_v32i32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: abs_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1485,13 +1485,13 @@ define void @abs_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: abs z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a + %op1 = load <32 x i32>, ptr %a %res = call <32 x i32> @llvm.abs.v32i32(<32 x i32> %op1, i1 false) - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @abs_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { +define void @abs_v64i32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: abs_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1499,9 +1499,9 @@ define void @abs_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: abs z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a + %op1 = load <64 x i32>, ptr %a %res = call <64 x i32> @llvm.abs.v64i32(<64 x i32> %op1, i1 false) - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -1525,7 +1525,7 @@ define <2 x i64> @abs_v2i64(<2 x i64> %op1) vscale_range(2,0) #0 { ret <2 x i64> %res } -define void @abs_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { +define void @abs_v4i64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: abs_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1533,13 +1533,13 @@ define void @abs_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: abs z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a + %op1 = load <4 x i64>, ptr %a %res = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %op1, i1 false) - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @abs_v8i64(<8 x i64>* %a) #0 { +define void @abs_v8i64(ptr %a) #0 { ; VBITS_GE_256-LABEL: abs_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1559,13 +1559,13 @@ define void @abs_v8i64(<8 x i64>* %a) #0 { ; VBITS_GE_512-NEXT: abs z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %res = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %op1, i1 false) - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @abs_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { +define void @abs_v16i64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: abs_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1573,13 +1573,13 @@ define void @abs_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: abs z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a + %op1 = load <16 x i64>, ptr %a %res = call <16 x i64> @llvm.abs.v16i64(<16 x i64> %op1, i1 false) - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @abs_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { +define void @abs_v32i64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: abs_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1587,9 +1587,9 @@ define void @abs_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: abs z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a + %op1 = load <32 x i64>, ptr %a %res = call <32 x i64> @llvm.abs.v32i64(<32 x i64> %op1, i1 false) - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-compares.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-compares.ll index 29b9392..2962e35 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-compares.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-compares.ll @@ -31,7 +31,7 @@ define <16 x i8> @icmp_eq_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0 ret <16 x i8> %sext } -define void @icmp_eq_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @icmp_eq_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: icmp_eq_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -41,15 +41,15 @@ define void @icmp_eq_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: mov z0.b, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %cmp = icmp eq <32 x i8> %op1, %op2 %sext = sext <32 x i1> %cmp to <32 x i8> - store <32 x i8> %sext, <32 x i8>* %a + store <32 x i8> %sext, ptr %a ret void } -define void @icmp_eq_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @icmp_eq_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: icmp_eq_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -75,15 +75,15 @@ define void @icmp_eq_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: mov z0.b, p1/z, #-1 // =0xffffffffffffffff ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %cmp = icmp eq <64 x i8> %op1, %op2 %sext = sext <64 x i1> %cmp to <64 x i8> - store <64 x i8> %sext, <64 x i8>* %a + store <64 x i8> %sext, ptr %a ret void } -define void @icmp_eq_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @icmp_eq_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: icmp_eq_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -93,15 +93,15 @@ define void @icmp_eq_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 ; CHECK-NEXT: mov z0.b, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %cmp = icmp eq <128 x i8> %op1, %op2 %sext = sext <128 x i1> %cmp to <128 x i8> - store <128 x i8> %sext, <128 x i8>* %a + store <128 x i8> %sext, ptr %a ret void } -define void @icmp_eq_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @icmp_eq_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: icmp_eq_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -111,11 +111,11 @@ define void @icmp_eq_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) # ; CHECK-NEXT: mov z0.b, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %cmp = icmp eq <256 x i8> %op1, %op2 %sext = sext <256 x i1> %cmp to <256 x i8> - store <256 x i8> %sext, <256 x i8>* %a + store <256 x i8> %sext, ptr %a ret void } @@ -141,7 +141,7 @@ define <8 x i16> @icmp_eq_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0 ret <8 x i16> %sext } -define void @icmp_eq_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @icmp_eq_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: icmp_eq_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -151,15 +151,15 @@ define void @icmp_eq_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %cmp = icmp eq <16 x i16> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %a + store <16 x i16> %sext, ptr %a ret void } -define void @icmp_eq_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @icmp_eq_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: icmp_eq_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -185,15 +185,15 @@ define void @icmp_eq_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %cmp = icmp eq <32 x i16> %op1, %op2 %sext = sext <32 x i1> %cmp to <32 x i16> - store <32 x i16> %sext, <32 x i16>* %a + store <32 x i16> %sext, ptr %a ret void } -define void @icmp_eq_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @icmp_eq_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: icmp_eq_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -203,15 +203,15 @@ define void @icmp_eq_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %cmp = icmp eq <64 x i16> %op1, %op2 %sext = sext <64 x i1> %cmp to <64 x i16> - store <64 x i16> %sext, <64 x i16>* %a + store <64 x i16> %sext, ptr %a ret void } -define void @icmp_eq_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @icmp_eq_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: icmp_eq_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -221,11 +221,11 @@ define void @icmp_eq_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0 ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %cmp = icmp eq <128 x i16> %op1, %op2 %sext = sext <128 x i1> %cmp to <128 x i16> - store <128 x i16> %sext, <128 x i16>* %a + store <128 x i16> %sext, ptr %a ret void } @@ -251,7 +251,7 @@ define <4 x i32> @icmp_eq_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0 ret <4 x i32> %sext } -define void @icmp_eq_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @icmp_eq_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: icmp_eq_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -261,15 +261,15 @@ define void @icmp_eq_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %cmp = icmp eq <8 x i32> %op1, %op2 %sext = sext <8 x i1> %cmp to <8 x i32> - store <8 x i32> %sext, <8 x i32>* %a + store <8 x i32> %sext, ptr %a ret void } -define void @icmp_eq_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @icmp_eq_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: icmp_eq_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -295,15 +295,15 @@ define void @icmp_eq_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %cmp = icmp eq <16 x i32> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i32> - store <16 x i32> %sext, <16 x i32>* %a + store <16 x i32> %sext, ptr %a ret void } -define void @icmp_eq_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @icmp_eq_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: icmp_eq_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -313,15 +313,15 @@ define void @icmp_eq_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 ; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %cmp = icmp eq <32 x i32> %op1, %op2 %sext = sext <32 x i1> %cmp to <32 x i32> - store <32 x i32> %sext, <32 x i32>* %a + store <32 x i32> %sext, ptr %a ret void } -define void @icmp_eq_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @icmp_eq_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: icmp_eq_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -331,11 +331,11 @@ define void @icmp_eq_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) # ; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %cmp = icmp eq <64 x i32> %op1, %op2 %sext = sext <64 x i1> %cmp to <64 x i32> - store <64 x i32> %sext, <64 x i32>* %a + store <64 x i32> %sext, ptr %a ret void } @@ -361,7 +361,7 @@ define <2 x i64> @icmp_eq_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0 ret <2 x i64> %sext } -define void @icmp_eq_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @icmp_eq_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: icmp_eq_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -371,15 +371,15 @@ define void @icmp_eq_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %cmp = icmp eq <4 x i64> %op1, %op2 %sext = sext <4 x i1> %cmp to <4 x i64> - store <4 x i64> %sext, <4 x i64>* %a + store <4 x i64> %sext, ptr %a ret void } -define void @icmp_eq_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @icmp_eq_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: icmp_eq_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -405,15 +405,15 @@ define void @icmp_eq_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %cmp = icmp eq <8 x i64> %op1, %op2 %sext = sext <8 x i1> %cmp to <8 x i64> - store <8 x i64> %sext, <8 x i64>* %a + store <8 x i64> %sext, ptr %a ret void } -define void @icmp_eq_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @icmp_eq_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: icmp_eq_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -423,15 +423,15 @@ define void @icmp_eq_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 ; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %cmp = icmp eq <16 x i64> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i64> - store <16 x i64> %sext, <16 x i64>* %a + store <16 x i64> %sext, ptr %a ret void } -define void @icmp_eq_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @icmp_eq_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: icmp_eq_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -441,11 +441,11 @@ define void @icmp_eq_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) # ; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %cmp = icmp eq <32 x i64> %op1, %op2 %sext = sext <32 x i1> %cmp to <32 x i64> - store <32 x i64> %sext, <32 x i64>* %a + store <32 x i64> %sext, ptr %a ret void } @@ -453,7 +453,7 @@ define void @icmp_eq_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) # ; ICMP NE ; -define void @icmp_ne_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @icmp_ne_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: icmp_ne_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -463,11 +463,11 @@ define void @icmp_ne_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: mov z0.b, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %cmp = icmp ne <32 x i8> %op1, %op2 %sext = sext <32 x i1> %cmp to <32 x i8> - store <32 x i8> %sext, <32 x i8>* %a + store <32 x i8> %sext, ptr %a ret void } @@ -475,7 +475,7 @@ define void @icmp_ne_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; ICMP SGE ; -define void @icmp_sge_v32i16(<32 x i16>* %a, <32 x i16>* %b) vscale_range(4,0) #0 { +define void @icmp_sge_v32i16(ptr %a, ptr %b) vscale_range(4,0) #0 { ; CHECK-LABEL: icmp_sge_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -485,11 +485,11 @@ define void @icmp_sge_v32i16(<32 x i16>* %a, <32 x i16>* %b) vscale_range(4,0) # ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %cmp = icmp sge <32 x i16> %op1, %op2 %sext = sext <32 x i1> %cmp to <32 x i16> - store <32 x i16> %sext, <32 x i16>* %a + store <32 x i16> %sext, ptr %a ret void } @@ -497,7 +497,7 @@ define void @icmp_sge_v32i16(<32 x i16>* %a, <32 x i16>* %b) vscale_range(4,0) # ; ICMP SGT ; -define void @icmp_sgt_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @icmp_sgt_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: icmp_sgt_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -507,11 +507,11 @@ define void @icmp_sgt_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) # ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %cmp = icmp sgt <16 x i16> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, <16 x i16>* %a + store <16 x i16> %sext, ptr %a ret void } @@ -519,7 +519,7 @@ define void @icmp_sgt_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) # ; ICMP SLE ; -define void @icmp_sle_v16i32(<16 x i32>* %a, <16 x i32>* %b) vscale_range(4,0) #0 { +define void @icmp_sle_v16i32(ptr %a, ptr %b) vscale_range(4,0) #0 { ; CHECK-LABEL: icmp_sle_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -529,11 +529,11 @@ define void @icmp_sle_v16i32(<16 x i32>* %a, <16 x i32>* %b) vscale_range(4,0) # ; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %cmp = icmp sle <16 x i32> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i32> - store <16 x i32> %sext, <16 x i32>* %a + store <16 x i32> %sext, ptr %a ret void } @@ -541,7 +541,7 @@ define void @icmp_sle_v16i32(<16 x i32>* %a, <16 x i32>* %b) vscale_range(4,0) # ; ICMP SLT ; -define void @icmp_slt_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @icmp_slt_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: icmp_slt_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -551,11 +551,11 @@ define void @icmp_slt_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %cmp = icmp slt <8 x i32> %op1, %op2 %sext = sext <8 x i1> %cmp to <8 x i32> - store <8 x i32> %sext, <8 x i32>* %a + store <8 x i32> %sext, ptr %a ret void } @@ -563,7 +563,7 @@ define void @icmp_slt_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; ICMP UGE ; -define void @icmp_uge_v8i64(<8 x i64>* %a, <8 x i64>* %b) vscale_range(4,0) #0 { +define void @icmp_uge_v8i64(ptr %a, ptr %b) vscale_range(4,0) #0 { ; CHECK-LABEL: icmp_uge_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl8 @@ -573,11 +573,11 @@ define void @icmp_uge_v8i64(<8 x i64>* %a, <8 x i64>* %b) vscale_range(4,0) #0 { ; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %cmp = icmp uge <8 x i64> %op1, %op2 %sext = sext <8 x i1> %cmp to <8 x i64> - store <8 x i64> %sext, <8 x i64>* %a + store <8 x i64> %sext, ptr %a ret void } @@ -585,7 +585,7 @@ define void @icmp_uge_v8i64(<8 x i64>* %a, <8 x i64>* %b) vscale_range(4,0) #0 { ; ICMP UGT ; -define void @icmp_ugt_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @icmp_ugt_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: icmp_ugt_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -595,11 +595,11 @@ define void @icmp_ugt_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %cmp = icmp ugt <4 x i64> %op1, %op2 %sext = sext <4 x i1> %cmp to <4 x i64> - store <4 x i64> %sext, <4 x i64>* %a + store <4 x i64> %sext, ptr %a ret void } @@ -607,7 +607,7 @@ define void @icmp_ugt_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; ICMP ULE ; -define void @icmp_ule_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @icmp_ule_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: icmp_ule_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -617,11 +617,11 @@ define void @icmp_ule_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) # ; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %cmp = icmp ule <16 x i64> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i64> - store <16 x i64> %sext, <16 x i64>* %a + store <16 x i64> %sext, ptr %a ret void } @@ -629,7 +629,7 @@ define void @icmp_ule_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) # ; ICMP ULT ; -define void @icmp_ult_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @icmp_ult_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: icmp_ult_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -639,11 +639,11 @@ define void @icmp_ult_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) ; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %cmp = icmp ult <32 x i64> %op1, %op2 %sext = sext <32 x i1> %cmp to <32 x i64> - store <32 x i64> %sext, <32 x i64>* %a + store <32 x i64> %sext, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll index bbcc19d..ca39635 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll @@ -155,7 +155,7 @@ define <16 x i8> @sdiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 { ret <16 x i8> %res } -define void @sdiv_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(8,0) #0 { +define void @sdiv_v32i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: sdiv_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -169,14 +169,14 @@ define void @sdiv_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1b { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %res = sdiv <32 x i8> %op1, %op2 - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @sdiv_v64i8(<64 x i8>* %a, <64 x i8>* %b) vscale_range(16,0) #0 { +define void @sdiv_v64i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: sdiv_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -190,14 +190,14 @@ define void @sdiv_v64i8(<64 x i8>* %a, <64 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1b { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = sdiv <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @sdiv_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(16,0) #0 { +define void @sdiv_v128i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: sdiv_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -216,14 +216,14 @@ define void @sdiv_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: ptrue p0.h, vl128 ; CHECK-NEXT: st1b { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %res = sdiv <128 x i8> %op1, %op2 - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @sdiv_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @sdiv_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: sdiv_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -251,10 +251,10 @@ define void @sdiv_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %res = sdiv <256 x i8> %op1, %op2 - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -348,7 +348,7 @@ define <8 x i16> @sdiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 { ret <8 x i16> %res } -define void @sdiv_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { +define void @sdiv_v16i16(ptr %a, ptr %b) #0 { ; VBITS_GE_128-LABEL: sdiv_v16i16: ; VBITS_GE_128: // %bb.0: ; VBITS_GE_128-NEXT: ldp q0, q1, [x1] @@ -398,14 +398,14 @@ define void @sdiv_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: sdiv z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1h { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %res = sdiv <16 x i16> %op1, %op2 - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @sdiv_v32i16(<32 x i16>* %a, <32 x i16>* %b) vscale_range(8,0) #0 { +define void @sdiv_v32i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: sdiv_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -417,14 +417,14 @@ define void @sdiv_v32i16(<32 x i16>* %a, <32 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1h { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = sdiv <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @sdiv_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(16,0) #0 { +define void @sdiv_v64i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: sdiv_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -436,14 +436,14 @@ define void @sdiv_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1h { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %res = sdiv <64 x i16> %op1, %op2 - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @sdiv_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @sdiv_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: sdiv_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -459,10 +459,10 @@ define void @sdiv_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) # ; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %res = sdiv <128 x i16> %op1, %op2 - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -494,7 +494,7 @@ define <4 x i32> @sdiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(1,0) # ret <4 x i32> %res } -define void @sdiv_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @sdiv_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: sdiv_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -503,14 +503,14 @@ define void @sdiv_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %res = sdiv <8 x i32> %op1, %op2 - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @sdiv_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @sdiv_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_128-LABEL: sdiv_v16i32: ; VBITS_GE_128: // %bb.0: ; VBITS_GE_128-NEXT: ldp q0, q1, [x0, #32] @@ -550,14 +550,14 @@ define void @sdiv_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: sdiv z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %res = sdiv <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @sdiv_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @sdiv_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: sdiv_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -566,14 +566,14 @@ define void @sdiv_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %res = sdiv <32 x i32> %op1, %op2 - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @sdiv_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @sdiv_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: sdiv_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -582,10 +582,10 @@ define void @sdiv_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %res = sdiv <64 x i32> %op1, %op2 - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -617,7 +617,7 @@ define <2 x i64> @sdiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(1,0) # ret <2 x i64> %res } -define void @sdiv_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @sdiv_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: sdiv_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -626,14 +626,14 @@ define void @sdiv_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %res = sdiv <4 x i64> %op1, %op2 - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @sdiv_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @sdiv_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_128-LABEL: sdiv_v8i64: ; VBITS_GE_128: // %bb.0: ; VBITS_GE_128-NEXT: ldp q0, q1, [x0, #32] @@ -673,14 +673,14 @@ define void @sdiv_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: sdiv z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %res = sdiv <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @sdiv_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @sdiv_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: sdiv_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -689,14 +689,14 @@ define void @sdiv_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %res = sdiv <16 x i64> %op1, %op2 - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @sdiv_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @sdiv_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: sdiv_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -705,10 +705,10 @@ define void @sdiv_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %res = sdiv <32 x i64> %op1, %op2 - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } @@ -861,7 +861,7 @@ define <16 x i8> @udiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 { ret <16 x i8> %res } -define void @udiv_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(8,0) #0 { +define void @udiv_v32i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: udiv_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -870,14 +870,14 @@ define void @udiv_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: udivr z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1b { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %res = udiv <32 x i8> %op1, %op2 - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @udiv_v64i8(<64 x i8>* %a, <64 x i8>* %b) vscale_range(16,0) #0 { +define void @udiv_v64i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: udiv_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -886,14 +886,14 @@ define void @udiv_v64i8(<64 x i8>* %a, <64 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: udivr z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1b { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = udiv <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @udiv_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(16,0) #0 { +define void @udiv_v128i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: udiv_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -909,14 +909,14 @@ define void @udiv_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h ; CHECK-NEXT: st1b { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %res = udiv <128 x i8> %op1, %op2 - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @udiv_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @udiv_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: udiv_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -944,10 +944,10 @@ define void @udiv_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %res = udiv <256 x i8> %op1, %op2 - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -1041,7 +1041,7 @@ define <8 x i16> @udiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 { ret <8 x i16> %res } -define void @udiv_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { +define void @udiv_v16i16(ptr %a, ptr %b) #0 { ; VBITS_GE_128-LABEL: udiv_v16i16: ; VBITS_GE_128: // %bb.0: ; VBITS_GE_128-NEXT: ldp q0, q1, [x1] @@ -1088,14 +1088,14 @@ define void @udiv_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: udivr z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1h { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %res = udiv <16 x i16> %op1, %op2 - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @udiv_v32i16(<32 x i16>* %a, <32 x i16>* %b) vscale_range(8,0) #0 { +define void @udiv_v32i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: udiv_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1104,14 +1104,14 @@ define void @udiv_v32i16(<32 x i16>* %a, <32 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: udivr z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1h { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = udiv <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @udiv_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(16,0) #0 { +define void @udiv_v64i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: udiv_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1120,14 +1120,14 @@ define void @udiv_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: udivr z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1h { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %res = udiv <64 x i16> %op1, %op2 - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @udiv_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @udiv_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: udiv_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1143,10 +1143,10 @@ define void @udiv_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) # ; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %res = udiv <128 x i16> %op1, %op2 - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -1178,7 +1178,7 @@ define <4 x i32> @udiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(1,0) # ret <4 x i32> %res } -define void @udiv_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @udiv_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: udiv_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1187,14 +1187,14 @@ define void @udiv_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %res = udiv <8 x i32> %op1, %op2 - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @udiv_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @udiv_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_128-LABEL: udiv_v16i32: ; VBITS_GE_128: // %bb.0: ; VBITS_GE_128-NEXT: ldp q0, q1, [x0, #32] @@ -1234,14 +1234,14 @@ define void @udiv_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: udiv z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %res = udiv <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @udiv_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @udiv_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: udiv_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1250,14 +1250,14 @@ define void @udiv_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %res = udiv <32 x i32> %op1, %op2 - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @udiv_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @udiv_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: udiv_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1266,10 +1266,10 @@ define void @udiv_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %res = udiv <64 x i32> %op1, %op2 - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -1301,7 +1301,7 @@ define <2 x i64> @udiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(1,0) # ret <2 x i64> %res } -define void @udiv_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @udiv_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: udiv_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1310,14 +1310,14 @@ define void @udiv_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %res = udiv <4 x i64> %op1, %op2 - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @udiv_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @udiv_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_128-LABEL: udiv_v8i64: ; VBITS_GE_128: // %bb.0: ; VBITS_GE_128-NEXT: ldp q0, q1, [x0, #32] @@ -1357,14 +1357,14 @@ define void @udiv_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: udiv z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %res = udiv <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @udiv_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @udiv_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: udiv_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1373,14 +1373,14 @@ define void @udiv_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %res = udiv <16 x i64> %op1, %op2 - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @udiv_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @udiv_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: udiv_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1389,16 +1389,16 @@ define void @udiv_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %res = udiv <32 x i64> %op1, %op2 - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } ; This used to crash because isUnaryPredicate and BuildUDIV don't know how ; a SPLAT_VECTOR of fixed vector type should be handled. -define void @udiv_constantsplat_v8i32(<8 x i32>* %a) vscale_range(2,0) #1 { +define void @udiv_constantsplat_v8i32(ptr %a) vscale_range(2,0) #1 { ; CHECK-LABEL: udiv_constantsplat_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1407,9 +1407,9 @@ define void @udiv_constantsplat_v8i32(<8 x i32>* %a) vscale_range(2,0) #1 { ; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a + %op1 = load <8 x i32>, ptr %a %res = udiv <8 x i32> %op1, - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll index b9f5c12..8521da6 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll @@ -12,7 +12,7 @@ target triple = "aarch64-unknown-linux-gnu" ; NOTE: Covers the scenario where a SIGN_EXTEND_INREG is required, whose inreg ; type's element type is not byte based and thus cannot be lowered directly to ; an SVE instruction. -define void @sext_v8i1_v8i32(<8 x i1> %a, <8 x i32>* %out) vscale_range(2,0) #0 { +define void @sext_v8i1_v8i32(<8 x i1> %a, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: sext_v8i1_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 @@ -24,7 +24,7 @@ define void @sext_v8i1_v8i32(<8 x i1> %a, <8 x i32>* %out) vscale_range(2,0) #0 ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret %b = sext <8 x i1> %a to <8 x i32> - store <8 x i32> %b, <8 x i32>* %out + store <8 x i32> %b, ptr %out ret void } @@ -35,7 +35,7 @@ define void @sext_v8i1_v8i32(<8 x i1> %a, <8 x i32>* %out) vscale_range(2,0) #0 ; NOTE: Covers the scenario where a SIGN_EXTEND_INREG is required, whose inreg ; type's element type is not power-of-2 based and thus cannot be lowered ; directly to an SVE instruction. -define void @sext_v4i3_v4i64(<4 x i3> %a, <4 x i64>* %out) vscale_range(2,0) #0 { +define void @sext_v4i3_v4i64(<4 x i3> %a, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: sext_v4i3_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 @@ -47,7 +47,7 @@ define void @sext_v4i3_v4i64(<4 x i3> %a, <4 x i64>* %out) vscale_range(2,0) #0 ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret %b = sext <4 x i3> %a to <4 x i64> - store <4 x i64> %b, <4 x i64>* %out + store <4 x i64> %b, ptr %out ret void } @@ -55,7 +55,7 @@ define void @sext_v4i3_v4i64(<4 x i3> %a, <4 x i64>* %out) vscale_range(2,0) #0 ; sext i8 -> i16 ; -define void @sext_v16i8_v16i16(<16 x i8> %a, <16 x i16>* %out) vscale_range(2,0) #0 { +define void @sext_v16i8_v16i16(<16 x i8> %a, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: sext_v16i8_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 @@ -64,12 +64,12 @@ define void @sext_v16i8_v16i16(<16 x i8> %a, <16 x i16>* %out) vscale_range(2,0) ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret %b = sext <16 x i8> %a to <16 x i16> - store <16 x i16>%b, <16 x i16>* %out + store <16 x i16>%b, ptr %out ret void } ; NOTE: Extra 'add' is to prevent the extend being combined with the load. -define void @sext_v32i8_v32i16(<32 x i8>* %in, <32 x i16>* %out) #0 { +define void @sext_v32i8_v32i16(ptr %in, ptr %out) #0 { ; VBITS_GE_256-LABEL: sext_v32i8_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.b, vl32 @@ -93,14 +93,14 @@ define void @sext_v32i8_v32i16(<32 x i8>* %in, <32 x i16>* %out) #0 { ; VBITS_GE_512-NEXT: sunpklo z0.h, z0.b ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <32 x i8>, <32 x i8>* %in + %a = load <32 x i8>, ptr %in %b = add <32 x i8> %a, %a %c = sext <32 x i8> %b to <32 x i16> - store <32 x i16> %c, <32 x i16>* %out + store <32 x i16> %c, ptr %out ret void } -define void @sext_v64i8_v64i16(<64 x i8>* %in, <64 x i16>* %out) vscale_range(8,0) #0 { +define void @sext_v64i8_v64i16(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: sext_v64i8_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -110,14 +110,14 @@ define void @sext_v64i8_v64i16(<64 x i8>* %in, <64 x i16>* %out) vscale_range(8, ; CHECK-NEXT: sunpklo z0.h, z0.b ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %a = load <64 x i8>, <64 x i8>* %in + %a = load <64 x i8>, ptr %in %b = add <64 x i8> %a, %a %c = sext <64 x i8> %b to <64 x i16> - store <64 x i16> %c, <64 x i16>* %out + store <64 x i16> %c, ptr %out ret void } -define void @sext_v128i8_v128i16(<128 x i8>* %in, <128 x i16>* %out) vscale_range(16,0) #0 { +define void @sext_v128i8_v128i16(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: sext_v128i8_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -127,10 +127,10 @@ define void @sext_v128i8_v128i16(<128 x i8>* %in, <128 x i16>* %out) vscale_rang ; CHECK-NEXT: sunpklo z0.h, z0.b ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %a = load <128 x i8>, <128 x i8>* %in + %a = load <128 x i8>, ptr %in %b = add <128 x i8> %a, %a %c = sext <128 x i8> %b to <128 x i16> - store <128 x i16> %c, <128 x i16>* %out + store <128 x i16> %c, ptr %out ret void } @@ -138,7 +138,7 @@ define void @sext_v128i8_v128i16(<128 x i8>* %in, <128 x i16>* %out) vscale_rang ; sext i8 -> i32 ; -define void @sext_v8i8_v8i32(<8 x i8> %a, <8 x i32>* %out) vscale_range(2,0) #0 { +define void @sext_v8i8_v8i32(<8 x i8> %a, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: sext_v8i8_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 @@ -148,11 +148,11 @@ define void @sext_v8i8_v8i32(<8 x i8> %a, <8 x i32>* %out) vscale_range(2,0) #0 ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret %b = sext <8 x i8> %a to <8 x i32> - store <8 x i32>%b, <8 x i32>* %out + store <8 x i32>%b, ptr %out ret void } -define void @sext_v16i8_v16i32(<16 x i8> %a, <16 x i32>* %out) #0 { +define void @sext_v16i8_v16i32(<16 x i8> %a, ptr %out) #0 { ; VBITS_GE_256-LABEL: sext_v16i8_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: // kill: def $q0 killed $q0 def $z0 @@ -176,11 +176,11 @@ define void @sext_v16i8_v16i32(<16 x i8> %a, <16 x i32>* %out) #0 { ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret %b = sext <16 x i8> %a to <16 x i32> - store <16 x i32> %b, <16 x i32>* %out + store <16 x i32> %b, ptr %out ret void } -define void @sext_v32i8_v32i32(<32 x i8>* %in, <32 x i32>* %out) vscale_range(8,0) #0 { +define void @sext_v32i8_v32i32(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: sext_v32i8_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -191,14 +191,14 @@ define void @sext_v32i8_v32i32(<32 x i8>* %in, <32 x i32>* %out) vscale_range(8, ; CHECK-NEXT: sunpklo z0.s, z0.h ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x i8>, <32 x i8>* %in + %a = load <32 x i8>, ptr %in %b = add <32 x i8> %a, %a %c = sext <32 x i8> %b to <32 x i32> - store <32 x i32> %c, <32 x i32>* %out + store <32 x i32> %c, ptr %out ret void } -define void @sext_v64i8_v64i32(<64 x i8>* %in, <64 x i32>* %out) vscale_range(16,0) #0 { +define void @sext_v64i8_v64i32(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: sext_v64i8_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -209,10 +209,10 @@ define void @sext_v64i8_v64i32(<64 x i8>* %in, <64 x i32>* %out) vscale_range(16 ; CHECK-NEXT: sunpklo z0.s, z0.h ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <64 x i8>, <64 x i8>* %in + %a = load <64 x i8>, ptr %in %b = add <64 x i8> %a, %a %c = sext <64 x i8> %b to <64 x i32> - store <64 x i32> %c, <64 x i32>* %out + store <64 x i32> %c, ptr %out ret void } @@ -223,7 +223,7 @@ define void @sext_v64i8_v64i32(<64 x i8>* %in, <64 x i32>* %out) vscale_range(16 ; NOTE: v4i8 is an unpacked typed stored within a v4i16 container. The sign ; extend is a two step process where the container is any_extend'd with the ; result feeding an inreg sign extend. -define void @sext_v4i8_v4i64(<4 x i8> %a, <4 x i64>* %out) vscale_range(2,0) #0 { +define void @sext_v4i8_v4i64(<4 x i8> %a, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: sext_v4i8_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 @@ -234,11 +234,11 @@ define void @sext_v4i8_v4i64(<4 x i8> %a, <4 x i64>* %out) vscale_range(2,0) #0 ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret %b = sext <4 x i8> %a to <4 x i64> - store <4 x i64>%b, <4 x i64>* %out + store <4 x i64>%b, ptr %out ret void } -define void @sext_v8i8_v8i64(<8 x i8> %a, <8 x i64>* %out) #0 { +define void @sext_v8i8_v8i64(<8 x i8> %a, ptr %out) #0 { ; VBITS_GE_256-LABEL: sext_v8i8_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: sshll v0.8h, v0.8b, #0 @@ -263,11 +263,11 @@ define void @sext_v8i8_v8i64(<8 x i8> %a, <8 x i64>* %out) #0 { ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret %b = sext <8 x i8> %a to <8 x i64> - store <8 x i64>%b, <8 x i64>* %out + store <8 x i64>%b, ptr %out ret void } -define void @sext_v16i8_v16i64(<16 x i8> %a, <16 x i64>* %out) vscale_range(8,0) #0 { +define void @sext_v16i8_v16i64(<16 x i8> %a, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: sext_v16i8_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 @@ -278,11 +278,11 @@ define void @sext_v16i8_v16i64(<16 x i8> %a, <16 x i64>* %out) vscale_range(8,0) ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret %b = sext <16 x i8> %a to <16 x i64> - store <16 x i64> %b, <16 x i64>* %out + store <16 x i64> %b, ptr %out ret void } -define void @sext_v32i8_v32i64(<32 x i8>* %in, <32 x i64>* %out) vscale_range(16,0) #0 { +define void @sext_v32i8_v32i64(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: sext_v32i8_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -294,10 +294,10 @@ define void @sext_v32i8_v32i64(<32 x i8>* %in, <32 x i64>* %out) vscale_range(16 ; CHECK-NEXT: sunpklo z0.d, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x i8>, <32 x i8>* %in + %a = load <32 x i8>, ptr %in %b = add <32 x i8> %a, %a %c = sext <32 x i8> %b to <32 x i64> - store <32 x i64> %c, <32 x i64>* %out + store <32 x i64> %c, ptr %out ret void } @@ -305,7 +305,7 @@ define void @sext_v32i8_v32i64(<32 x i8>* %in, <32 x i64>* %out) vscale_range(16 ; sext i16 -> i32 ; -define void @sext_v8i16_v8i32(<8 x i16> %a, <8 x i32>* %out) vscale_range(2,0) #0 { +define void @sext_v8i16_v8i32(<8 x i16> %a, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: sext_v8i16_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 @@ -314,11 +314,11 @@ define void @sext_v8i16_v8i32(<8 x i16> %a, <8 x i32>* %out) vscale_range(2,0) # ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret %b = sext <8 x i16> %a to <8 x i32> - store <8 x i32>%b, <8 x i32>* %out + store <8 x i32>%b, ptr %out ret void } -define void @sext_v16i16_v16i32(<16 x i16>* %in, <16 x i32>* %out) #0 { +define void @sext_v16i16_v16i32(ptr %in, ptr %out) #0 { ; VBITS_GE_256-LABEL: sext_v16i16_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.h, vl16 @@ -342,14 +342,14 @@ define void @sext_v16i16_v16i32(<16 x i16>* %in, <16 x i32>* %out) #0 { ; VBITS_GE_512-NEXT: sunpklo z0.s, z0.h ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <16 x i16>, <16 x i16>* %in + %a = load <16 x i16>, ptr %in %b = add <16 x i16> %a, %a %c = sext <16 x i16> %b to <16 x i32> - store <16 x i32> %c, <16 x i32>* %out + store <16 x i32> %c, ptr %out ret void } -define void @sext_v32i16_v32i32(<32 x i16>* %in, <32 x i32>* %out) vscale_range(8,0) #0 { +define void @sext_v32i16_v32i32(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: sext_v32i16_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -359,14 +359,14 @@ define void @sext_v32i16_v32i32(<32 x i16>* %in, <32 x i32>* %out) vscale_range( ; CHECK-NEXT: sunpklo z0.s, z0.h ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x i16>, <32 x i16>* %in + %a = load <32 x i16>, ptr %in %b = add <32 x i16> %a, %a %c = sext <32 x i16> %b to <32 x i32> - store <32 x i32> %c, <32 x i32>* %out + store <32 x i32> %c, ptr %out ret void } -define void @sext_v64i16_v64i32(<64 x i16>* %in, <64 x i32>* %out) vscale_range(16,0) #0 { +define void @sext_v64i16_v64i32(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: sext_v64i16_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -376,10 +376,10 @@ define void @sext_v64i16_v64i32(<64 x i16>* %in, <64 x i32>* %out) vscale_range( ; CHECK-NEXT: sunpklo z0.s, z0.h ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <64 x i16>, <64 x i16>* %in + %a = load <64 x i16>, ptr %in %b = add <64 x i16> %a, %a %c = sext <64 x i16> %b to <64 x i32> - store <64 x i32> %c, <64 x i32>* %out + store <64 x i32> %c, ptr %out ret void } @@ -387,7 +387,7 @@ define void @sext_v64i16_v64i32(<64 x i16>* %in, <64 x i32>* %out) vscale_range( ; sext i16 -> i64 ; -define void @sext_v4i16_v4i64(<4 x i16> %a, <4 x i64>* %out) vscale_range(2,0) #0 { +define void @sext_v4i16_v4i64(<4 x i16> %a, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: sext_v4i16_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 @@ -397,11 +397,11 @@ define void @sext_v4i16_v4i64(<4 x i16> %a, <4 x i64>* %out) vscale_range(2,0) # ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret %b = sext <4 x i16> %a to <4 x i64> - store <4 x i64>%b, <4 x i64>* %out + store <4 x i64>%b, ptr %out ret void } -define void @sext_v8i16_v8i64(<8 x i16> %a, <8 x i64>* %out) #0 { +define void @sext_v8i16_v8i64(<8 x i16> %a, ptr %out) #0 { ; VBITS_GE_256-LABEL: sext_v8i16_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: // kill: def $q0 killed $q0 def $z0 @@ -425,11 +425,11 @@ define void @sext_v8i16_v8i64(<8 x i16> %a, <8 x i64>* %out) #0 { ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret %b = sext <8 x i16> %a to <8 x i64> - store <8 x i64>%b, <8 x i64>* %out + store <8 x i64>%b, ptr %out ret void } -define void @sext_v16i16_v16i64(<16 x i16>* %in, <16 x i64>* %out) vscale_range(8,0) #0 { +define void @sext_v16i16_v16i64(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: sext_v16i16_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -440,14 +440,14 @@ define void @sext_v16i16_v16i64(<16 x i16>* %in, <16 x i64>* %out) vscale_range( ; CHECK-NEXT: sunpklo z0.d, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <16 x i16>, <16 x i16>* %in + %a = load <16 x i16>, ptr %in %b = add <16 x i16> %a, %a %c = sext <16 x i16> %b to <16 x i64> - store <16 x i64> %c, <16 x i64>* %out + store <16 x i64> %c, ptr %out ret void } -define void @sext_v32i16_v32i64(<32 x i16>* %in, <32 x i64>* %out) vscale_range(16,0) #0 { +define void @sext_v32i16_v32i64(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: sext_v32i16_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -458,10 +458,10 @@ define void @sext_v32i16_v32i64(<32 x i16>* %in, <32 x i64>* %out) vscale_range( ; CHECK-NEXT: sunpklo z0.d, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x i16>, <32 x i16>* %in + %a = load <32 x i16>, ptr %in %b = add <32 x i16> %a, %a %c = sext <32 x i16> %b to <32 x i64> - store <32 x i64> %c, <32 x i64>* %out + store <32 x i64> %c, ptr %out ret void } @@ -469,7 +469,7 @@ define void @sext_v32i16_v32i64(<32 x i16>* %in, <32 x i64>* %out) vscale_range( ; sext i32 -> i64 ; -define void @sext_v4i32_v4i64(<4 x i32> %a, <4 x i64>* %out) vscale_range(2,0) #0 { +define void @sext_v4i32_v4i64(<4 x i32> %a, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: sext_v4i32_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 @@ -478,11 +478,11 @@ define void @sext_v4i32_v4i64(<4 x i32> %a, <4 x i64>* %out) vscale_range(2,0) # ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret %b = sext <4 x i32> %a to <4 x i64> - store <4 x i64>%b, <4 x i64>* %out + store <4 x i64>%b, ptr %out ret void } -define void @sext_v8i32_v8i64(<8 x i32>* %in, <8 x i64>* %out) #0 { +define void @sext_v8i32_v8i64(ptr %in, ptr %out) #0 { ; VBITS_GE_256-LABEL: sext_v8i32_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.s, vl8 @@ -506,14 +506,14 @@ define void @sext_v8i32_v8i64(<8 x i32>* %in, <8 x i64>* %out) #0 { ; VBITS_GE_512-NEXT: sunpklo z0.d, z0.s ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <8 x i32>, <8 x i32>* %in + %a = load <8 x i32>, ptr %in %b = add <8 x i32> %a, %a %c = sext <8 x i32> %b to <8 x i64> - store <8 x i64> %c, <8 x i64>* %out + store <8 x i64> %c, ptr %out ret void } -define void @sext_v16i32_v16i64(<16 x i32>* %in, <16 x i64>* %out) vscale_range(8,0) #0 { +define void @sext_v16i32_v16i64(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: sext_v16i32_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -523,14 +523,14 @@ define void @sext_v16i32_v16i64(<16 x i32>* %in, <16 x i64>* %out) vscale_range( ; CHECK-NEXT: sunpklo z0.d, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <16 x i32>, <16 x i32>* %in + %a = load <16 x i32>, ptr %in %b = add <16 x i32> %a, %a %c = sext <16 x i32> %b to <16 x i64> - store <16 x i64> %c, <16 x i64>* %out + store <16 x i64> %c, ptr %out ret void } -define void @sext_v32i32_v32i64(<32 x i32>* %in, <32 x i64>* %out) vscale_range(16,0) #0 { +define void @sext_v32i32_v32i64(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: sext_v32i32_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -540,10 +540,10 @@ define void @sext_v32i32_v32i64(<32 x i32>* %in, <32 x i64>* %out) vscale_range( ; CHECK-NEXT: sunpklo z0.d, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x i32>, <32 x i32>* %in + %a = load <32 x i32>, ptr %in %b = add <32 x i32> %a, %a %c = sext <32 x i32> %b to <32 x i64> - store <32 x i64> %c, <32 x i64>* %out + store <32 x i64> %c, ptr %out ret void } @@ -551,7 +551,7 @@ define void @sext_v32i32_v32i64(<32 x i32>* %in, <32 x i64>* %out) vscale_range( ; zext i8 -> i16 ; -define void @zext_v16i8_v16i16(<16 x i8> %a, <16 x i16>* %out) vscale_range(2,0) #0 { +define void @zext_v16i8_v16i16(<16 x i8> %a, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: zext_v16i8_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 @@ -560,12 +560,12 @@ define void @zext_v16i8_v16i16(<16 x i8> %a, <16 x i16>* %out) vscale_range(2,0) ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret %b = zext <16 x i8> %a to <16 x i16> - store <16 x i16>%b, <16 x i16>* %out + store <16 x i16>%b, ptr %out ret void } ; NOTE: Extra 'add' is to prevent the extend being combined with the load. -define void @zext_v32i8_v32i16(<32 x i8>* %in, <32 x i16>* %out) #0 { +define void @zext_v32i8_v32i16(ptr %in, ptr %out) #0 { ; VBITS_GE_256-LABEL: zext_v32i8_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.b, vl32 @@ -589,14 +589,14 @@ define void @zext_v32i8_v32i16(<32 x i8>* %in, <32 x i16>* %out) #0 { ; VBITS_GE_512-NEXT: uunpklo z0.h, z0.b ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <32 x i8>, <32 x i8>* %in + %a = load <32 x i8>, ptr %in %b = add <32 x i8> %a, %a %c = zext <32 x i8> %b to <32 x i16> - store <32 x i16> %c, <32 x i16>* %out + store <32 x i16> %c, ptr %out ret void } -define void @zext_v64i8_v64i16(<64 x i8>* %in, <64 x i16>* %out) vscale_range(8,0) #0 { +define void @zext_v64i8_v64i16(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: zext_v64i8_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -606,14 +606,14 @@ define void @zext_v64i8_v64i16(<64 x i8>* %in, <64 x i16>* %out) vscale_range(8, ; CHECK-NEXT: uunpklo z0.h, z0.b ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %a = load <64 x i8>, <64 x i8>* %in + %a = load <64 x i8>, ptr %in %b = add <64 x i8> %a, %a %c = zext <64 x i8> %b to <64 x i16> - store <64 x i16> %c, <64 x i16>* %out + store <64 x i16> %c, ptr %out ret void } -define void @zext_v128i8_v128i16(<128 x i8>* %in, <128 x i16>* %out) vscale_range(16,0) #0 { +define void @zext_v128i8_v128i16(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: zext_v128i8_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -623,10 +623,10 @@ define void @zext_v128i8_v128i16(<128 x i8>* %in, <128 x i16>* %out) vscale_rang ; CHECK-NEXT: uunpklo z0.h, z0.b ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %a = load <128 x i8>, <128 x i8>* %in + %a = load <128 x i8>, ptr %in %b = add <128 x i8> %a, %a %c = zext <128 x i8> %b to <128 x i16> - store <128 x i16> %c, <128 x i16>* %out + store <128 x i16> %c, ptr %out ret void } @@ -634,7 +634,7 @@ define void @zext_v128i8_v128i16(<128 x i8>* %in, <128 x i16>* %out) vscale_rang ; zext i8 -> i32 ; -define void @zext_v8i8_v8i32(<8 x i8> %a, <8 x i32>* %out) vscale_range(2,0) #0 { +define void @zext_v8i8_v8i32(<8 x i8> %a, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: zext_v8i8_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 @@ -644,11 +644,11 @@ define void @zext_v8i8_v8i32(<8 x i8> %a, <8 x i32>* %out) vscale_range(2,0) #0 ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret %b = zext <8 x i8> %a to <8 x i32> - store <8 x i32>%b, <8 x i32>* %out + store <8 x i32>%b, ptr %out ret void } -define void @zext_v16i8_v16i32(<16 x i8> %a, <16 x i32>* %out) #0 { +define void @zext_v16i8_v16i32(<16 x i8> %a, ptr %out) #0 { ; VBITS_GE_256-LABEL: zext_v16i8_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: // kill: def $q0 killed $q0 def $z0 @@ -672,11 +672,11 @@ define void @zext_v16i8_v16i32(<16 x i8> %a, <16 x i32>* %out) #0 { ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret %b = zext <16 x i8> %a to <16 x i32> - store <16 x i32> %b, <16 x i32>* %out + store <16 x i32> %b, ptr %out ret void } -define void @zext_v32i8_v32i32(<32 x i8>* %in, <32 x i32>* %out) vscale_range(8,0) #0 { +define void @zext_v32i8_v32i32(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: zext_v32i8_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -687,14 +687,14 @@ define void @zext_v32i8_v32i32(<32 x i8>* %in, <32 x i32>* %out) vscale_range(8, ; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x i8>, <32 x i8>* %in + %a = load <32 x i8>, ptr %in %b = add <32 x i8> %a, %a %c = zext <32 x i8> %b to <32 x i32> - store <32 x i32> %c, <32 x i32>* %out + store <32 x i32> %c, ptr %out ret void } -define void @zext_v64i8_v64i32(<64 x i8>* %in, <64 x i32>* %out) vscale_range(16,0) #0 { +define void @zext_v64i8_v64i32(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: zext_v64i8_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -705,10 +705,10 @@ define void @zext_v64i8_v64i32(<64 x i8>* %in, <64 x i32>* %out) vscale_range(16 ; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <64 x i8>, <64 x i8>* %in + %a = load <64 x i8>, ptr %in %b = add <64 x i8> %a, %a %c = zext <64 x i8> %b to <64 x i32> - store <64 x i32> %c, <64 x i32>* %out + store <64 x i32> %c, ptr %out ret void } @@ -719,7 +719,7 @@ define void @zext_v64i8_v64i32(<64 x i8>* %in, <64 x i32>* %out) vscale_range(16 ; NOTE: v4i8 is an unpacked typed stored within a v4i16 container. The zero ; extend is a two step process where the container is zero_extend_inreg'd with ; the result feeding a normal zero extend from halfs to doublewords. -define void @zext_v4i8_v4i64(<4 x i8> %a, <4 x i64>* %out) vscale_range(2,0) #0 { +define void @zext_v4i8_v4i64(<4 x i8> %a, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: zext_v4i8_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 @@ -730,11 +730,11 @@ define void @zext_v4i8_v4i64(<4 x i8> %a, <4 x i64>* %out) vscale_range(2,0) #0 ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret %b = zext <4 x i8> %a to <4 x i64> - store <4 x i64>%b, <4 x i64>* %out + store <4 x i64>%b, ptr %out ret void } -define void @zext_v8i8_v8i64(<8 x i8> %a, <8 x i64>* %out) #0 { +define void @zext_v8i8_v8i64(<8 x i8> %a, ptr %out) #0 { ; VBITS_GE_256-LABEL: zext_v8i8_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ushll v0.8h, v0.8b, #0 @@ -759,11 +759,11 @@ define void @zext_v8i8_v8i64(<8 x i8> %a, <8 x i64>* %out) #0 { ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret %b = zext <8 x i8> %a to <8 x i64> - store <8 x i64>%b, <8 x i64>* %out + store <8 x i64>%b, ptr %out ret void } -define void @zext_v16i8_v16i64(<16 x i8> %a, <16 x i64>* %out) vscale_range(8,0) #0 { +define void @zext_v16i8_v16i64(<16 x i8> %a, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: zext_v16i8_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 @@ -774,11 +774,11 @@ define void @zext_v16i8_v16i64(<16 x i8> %a, <16 x i64>* %out) vscale_range(8,0) ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret %b = zext <16 x i8> %a to <16 x i64> - store <16 x i64> %b, <16 x i64>* %out + store <16 x i64> %b, ptr %out ret void } -define void @zext_v32i8_v32i64(<32 x i8>* %in, <32 x i64>* %out) vscale_range(16,0) #0 { +define void @zext_v32i8_v32i64(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: zext_v32i8_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -790,10 +790,10 @@ define void @zext_v32i8_v32i64(<32 x i8>* %in, <32 x i64>* %out) vscale_range(16 ; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x i8>, <32 x i8>* %in + %a = load <32 x i8>, ptr %in %b = add <32 x i8> %a, %a %c = zext <32 x i8> %b to <32 x i64> - store <32 x i64> %c, <32 x i64>* %out + store <32 x i64> %c, ptr %out ret void } @@ -801,7 +801,7 @@ define void @zext_v32i8_v32i64(<32 x i8>* %in, <32 x i64>* %out) vscale_range(16 ; zext i16 -> i32 ; -define void @zext_v8i16_v8i32(<8 x i16> %a, <8 x i32>* %out) vscale_range(2,0) #0 { +define void @zext_v8i16_v8i32(<8 x i16> %a, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: zext_v8i16_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 @@ -810,11 +810,11 @@ define void @zext_v8i16_v8i32(<8 x i16> %a, <8 x i32>* %out) vscale_range(2,0) # ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret %b = zext <8 x i16> %a to <8 x i32> - store <8 x i32>%b, <8 x i32>* %out + store <8 x i32>%b, ptr %out ret void } -define void @zext_v16i16_v16i32(<16 x i16>* %in, <16 x i32>* %out) #0 { +define void @zext_v16i16_v16i32(ptr %in, ptr %out) #0 { ; VBITS_GE_256-LABEL: zext_v16i16_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.h, vl16 @@ -838,14 +838,14 @@ define void @zext_v16i16_v16i32(<16 x i16>* %in, <16 x i32>* %out) #0 { ; VBITS_GE_512-NEXT: uunpklo z0.s, z0.h ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <16 x i16>, <16 x i16>* %in + %a = load <16 x i16>, ptr %in %b = add <16 x i16> %a, %a %c = zext <16 x i16> %b to <16 x i32> - store <16 x i32> %c, <16 x i32>* %out + store <16 x i32> %c, ptr %out ret void } -define void @zext_v32i16_v32i32(<32 x i16>* %in, <32 x i32>* %out) vscale_range(8,0) #0 { +define void @zext_v32i16_v32i32(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: zext_v32i16_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -855,14 +855,14 @@ define void @zext_v32i16_v32i32(<32 x i16>* %in, <32 x i32>* %out) vscale_range( ; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x i16>, <32 x i16>* %in + %a = load <32 x i16>, ptr %in %b = add <32 x i16> %a, %a %c = zext <32 x i16> %b to <32 x i32> - store <32 x i32> %c, <32 x i32>* %out + store <32 x i32> %c, ptr %out ret void } -define void @zext_v64i16_v64i32(<64 x i16>* %in, <64 x i32>* %out) vscale_range(16,0) #0 { +define void @zext_v64i16_v64i32(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: zext_v64i16_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -872,10 +872,10 @@ define void @zext_v64i16_v64i32(<64 x i16>* %in, <64 x i32>* %out) vscale_range( ; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <64 x i16>, <64 x i16>* %in + %a = load <64 x i16>, ptr %in %b = add <64 x i16> %a, %a %c = zext <64 x i16> %b to <64 x i32> - store <64 x i32> %c, <64 x i32>* %out + store <64 x i32> %c, ptr %out ret void } @@ -883,7 +883,7 @@ define void @zext_v64i16_v64i32(<64 x i16>* %in, <64 x i32>* %out) vscale_range( ; zext i16 -> i64 ; -define void @zext_v4i16_v4i64(<4 x i16> %a, <4 x i64>* %out) vscale_range(2,0) #0 { +define void @zext_v4i16_v4i64(<4 x i16> %a, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: zext_v4i16_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 @@ -893,11 +893,11 @@ define void @zext_v4i16_v4i64(<4 x i16> %a, <4 x i64>* %out) vscale_range(2,0) # ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret %b = zext <4 x i16> %a to <4 x i64> - store <4 x i64>%b, <4 x i64>* %out + store <4 x i64>%b, ptr %out ret void } -define void @zext_v8i16_v8i64(<8 x i16> %a, <8 x i64>* %out) #0 { +define void @zext_v8i16_v8i64(<8 x i16> %a, ptr %out) #0 { ; VBITS_GE_256-LABEL: zext_v8i16_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: // kill: def $q0 killed $q0 def $z0 @@ -921,11 +921,11 @@ define void @zext_v8i16_v8i64(<8 x i16> %a, <8 x i64>* %out) #0 { ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret %b = zext <8 x i16> %a to <8 x i64> - store <8 x i64>%b, <8 x i64>* %out + store <8 x i64>%b, ptr %out ret void } -define void @zext_v16i16_v16i64(<16 x i16>* %in, <16 x i64>* %out) vscale_range(8,0) #0 { +define void @zext_v16i16_v16i64(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: zext_v16i16_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -936,14 +936,14 @@ define void @zext_v16i16_v16i64(<16 x i16>* %in, <16 x i64>* %out) vscale_range( ; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <16 x i16>, <16 x i16>* %in + %a = load <16 x i16>, ptr %in %b = add <16 x i16> %a, %a %c = zext <16 x i16> %b to <16 x i64> - store <16 x i64> %c, <16 x i64>* %out + store <16 x i64> %c, ptr %out ret void } -define void @zext_v32i16_v32i64(<32 x i16>* %in, <32 x i64>* %out) vscale_range(16,0) #0 { +define void @zext_v32i16_v32i64(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: zext_v32i16_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -954,10 +954,10 @@ define void @zext_v32i16_v32i64(<32 x i16>* %in, <32 x i64>* %out) vscale_range( ; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x i16>, <32 x i16>* %in + %a = load <32 x i16>, ptr %in %b = add <32 x i16> %a, %a %c = zext <32 x i16> %b to <32 x i64> - store <32 x i64> %c, <32 x i64>* %out + store <32 x i64> %c, ptr %out ret void } @@ -965,7 +965,7 @@ define void @zext_v32i16_v32i64(<32 x i16>* %in, <32 x i64>* %out) vscale_range( ; zext i32 -> i64 ; -define void @zext_v4i32_v4i64(<4 x i32> %a, <4 x i64>* %out) vscale_range(2,0) #0 { +define void @zext_v4i32_v4i64(<4 x i32> %a, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: zext_v4i32_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 @@ -974,11 +974,11 @@ define void @zext_v4i32_v4i64(<4 x i32> %a, <4 x i64>* %out) vscale_range(2,0) # ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret %b = zext <4 x i32> %a to <4 x i64> - store <4 x i64>%b, <4 x i64>* %out + store <4 x i64>%b, ptr %out ret void } -define void @zext_v8i32_v8i64(<8 x i32>* %in, <8 x i64>* %out) #0 { +define void @zext_v8i32_v8i64(ptr %in, ptr %out) #0 { ; VBITS_GE_256-LABEL: zext_v8i32_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.s, vl8 @@ -1002,14 +1002,14 @@ define void @zext_v8i32_v8i64(<8 x i32>* %in, <8 x i64>* %out) #0 { ; VBITS_GE_512-NEXT: uunpklo z0.d, z0.s ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <8 x i32>, <8 x i32>* %in + %a = load <8 x i32>, ptr %in %b = add <8 x i32> %a, %a %c = zext <8 x i32> %b to <8 x i64> - store <8 x i64> %c, <8 x i64>* %out + store <8 x i64> %c, ptr %out ret void } -define void @zext_v16i32_v16i64(<16 x i32>* %in, <16 x i64>* %out) vscale_range(8,0) #0 { +define void @zext_v16i32_v16i64(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: zext_v16i32_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -1019,14 +1019,14 @@ define void @zext_v16i32_v16i64(<16 x i32>* %in, <16 x i64>* %out) vscale_range( ; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <16 x i32>, <16 x i32>* %in + %a = load <16 x i32>, ptr %in %b = add <16 x i32> %a, %a %c = zext <16 x i32> %b to <16 x i64> - store <16 x i64> %c, <16 x i64>* %out + store <16 x i64> %c, ptr %out ret void } -define void @zext_v32i32_v32i64(<32 x i32>* %in, <32 x i64>* %out) vscale_range(16,0) #0 { +define void @zext_v32i32_v32i64(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: zext_v32i32_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1036,10 +1036,10 @@ define void @zext_v32i32_v32i64(<32 x i32>* %in, <32 x i64>* %out) vscale_range( ; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x i32>, <32 x i32>* %in + %a = load <32 x i32>, ptr %in %b = add <32 x i32> %a, %a %c = zext <32 x i32> %b to <32 x i64> - store <32 x i64> %c, <32 x i64>* %out + store <32 x i64> %c, ptr %out ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll index f6bc72f..3ff9c90 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll @@ -11,7 +11,7 @@ target triple = "aarch64-unknown-linux-gnu" ; ADD ; -define void @add_v64i8(<64 x i8>* %a) #0 { +define void @add_v64i8(ptr %a) #0 { ; CHECK-LABEL: add_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -19,15 +19,15 @@ define void @add_v64i8(<64 x i8>* %a) #0 { ; CHECK-NEXT: add z0.b, z0.b, #7 // =0x7 ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a + %op1 = load <64 x i8>, ptr %a %ins = insertelement <64 x i8> undef, i8 7, i64 0 %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer %res = add <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @add_v32i16(<32 x i16>* %a) #0 { +define void @add_v32i16(ptr %a) #0 { ; CHECK-LABEL: add_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -35,15 +35,15 @@ define void @add_v32i16(<32 x i16>* %a) #0 { ; CHECK-NEXT: add z0.h, z0.h, #15 // =0xf ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %ins = insertelement <32 x i16> undef, i16 15, i64 0 %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer %res = add <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @add_v16i32(<16 x i32>* %a) #0 { +define void @add_v16i32(ptr %a) #0 { ; CHECK-LABEL: add_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -51,15 +51,15 @@ define void @add_v16i32(<16 x i32>* %a) #0 { ; CHECK-NEXT: add z0.s, z0.s, #31 // =0x1f ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %ins = insertelement <16 x i32> undef, i32 31, i64 0 %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer %res = add <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @add_v8i64(<8 x i64>* %a) #0 { +define void @add_v8i64(ptr %a) #0 { ; CHECK-LABEL: add_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl8 @@ -67,11 +67,11 @@ define void @add_v8i64(<8 x i64>* %a) #0 { ; CHECK-NEXT: add z0.d, z0.d, #63 // =0x3f ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %ins = insertelement <8 x i64> undef, i64 63, i64 0 %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer %res = add <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } @@ -79,7 +79,7 @@ define void @add_v8i64(<8 x i64>* %a) #0 { ; AND ; -define void @and_v64i8(<64 x i8>* %a) #0 { +define void @and_v64i8(ptr %a) #0 { ; CHECK-LABEL: and_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -87,15 +87,15 @@ define void @and_v64i8(<64 x i8>* %a) #0 { ; CHECK-NEXT: and z0.b, z0.b, #0x7 ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a + %op1 = load <64 x i8>, ptr %a %ins = insertelement <64 x i8> undef, i8 7, i64 0 %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer %res = and <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @and_v32i16(<32 x i16>* %a) #0 { +define void @and_v32i16(ptr %a) #0 { ; CHECK-LABEL: and_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -103,15 +103,15 @@ define void @and_v32i16(<32 x i16>* %a) #0 { ; CHECK-NEXT: and z0.h, z0.h, #0xf ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %ins = insertelement <32 x i16> undef, i16 15, i64 0 %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer %res = and <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @and_v16i32(<16 x i32>* %a) #0 { +define void @and_v16i32(ptr %a) #0 { ; CHECK-LABEL: and_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -119,15 +119,15 @@ define void @and_v16i32(<16 x i32>* %a) #0 { ; CHECK-NEXT: and z0.s, z0.s, #0x1f ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %ins = insertelement <16 x i32> undef, i32 31, i64 0 %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer %res = and <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @and_v8i64(<8 x i64>* %a) #0 { +define void @and_v8i64(ptr %a) #0 { ; CHECK-LABEL: and_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl8 @@ -135,11 +135,11 @@ define void @and_v8i64(<8 x i64>* %a) #0 { ; CHECK-NEXT: and z0.d, z0.d, #0x3f ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %ins = insertelement <8 x i64> undef, i64 63, i64 0 %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer %res = and <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } @@ -147,7 +147,7 @@ define void @and_v8i64(<8 x i64>* %a) #0 { ; ASHR ; -define void @ashr_v64i8(<64 x i8>* %a) #0 { +define void @ashr_v64i8(ptr %a) #0 { ; CHECK-LABEL: ashr_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -155,15 +155,15 @@ define void @ashr_v64i8(<64 x i8>* %a) #0 { ; CHECK-NEXT: asr z0.b, p0/m, z0.b, #7 ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a + %op1 = load <64 x i8>, ptr %a %ins = insertelement <64 x i8> undef, i8 7, i64 0 %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer %res = ashr <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @ashr_v32i16(<32 x i16>* %a) #0 { +define void @ashr_v32i16(ptr %a) #0 { ; CHECK-LABEL: ashr_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -171,15 +171,15 @@ define void @ashr_v32i16(<32 x i16>* %a) #0 { ; CHECK-NEXT: asr z0.h, p0/m, z0.h, #15 ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %ins = insertelement <32 x i16> undef, i16 15, i64 0 %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer %res = ashr <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @ashr_v16i32(<16 x i32>* %a) #0 { +define void @ashr_v16i32(ptr %a) #0 { ; CHECK-LABEL: ashr_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -187,15 +187,15 @@ define void @ashr_v16i32(<16 x i32>* %a) #0 { ; CHECK-NEXT: asr z0.s, p0/m, z0.s, #31 ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %ins = insertelement <16 x i32> undef, i32 31, i64 0 %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer %res = ashr <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @ashr_v8i64(<8 x i64>* %a) #0 { +define void @ashr_v8i64(ptr %a) #0 { ; CHECK-LABEL: ashr_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl8 @@ -203,11 +203,11 @@ define void @ashr_v8i64(<8 x i64>* %a) #0 { ; CHECK-NEXT: asr z0.d, p0/m, z0.d, #63 ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %ins = insertelement <8 x i64> undef, i64 63, i64 0 %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer %res = ashr <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } @@ -215,7 +215,7 @@ define void @ashr_v8i64(<8 x i64>* %a) #0 { ; ICMP ; -define void @icmp_eq_v64i8(<64 x i8>* %a) #0 { +define void @icmp_eq_v64i8(ptr %a) #0 { ; CHECK-LABEL: icmp_eq_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -224,16 +224,16 @@ define void @icmp_eq_v64i8(<64 x i8>* %a) #0 { ; CHECK-NEXT: mov z0.b, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a + %op1 = load <64 x i8>, ptr %a %ins = insertelement <64 x i8> undef, i8 7, i64 0 %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer %cmp = icmp eq <64 x i8> %op1, %op2 %res = sext <64 x i1> %cmp to <64 x i8> - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @icmp_sge_v32i16(<32 x i16>* %a) #0 { +define void @icmp_sge_v32i16(ptr %a) #0 { ; CHECK-LABEL: icmp_sge_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -242,16 +242,16 @@ define void @icmp_sge_v32i16(<32 x i16>* %a) #0 { ; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %ins = insertelement <32 x i16> undef, i16 15, i64 0 %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer %cmp = icmp sge <32 x i16> %op1, %op2 %res = sext <32 x i1> %cmp to <32 x i16> - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @icmp_sgt_v16i32(<16 x i32>* %a) #0 { +define void @icmp_sgt_v16i32(ptr %a) #0 { ; CHECK-LABEL: icmp_sgt_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -260,16 +260,16 @@ define void @icmp_sgt_v16i32(<16 x i32>* %a) #0 { ; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %ins = insertelement <16 x i32> undef, i32 -16, i64 0 %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer %cmp = icmp sgt <16 x i32> %op1, %op2 %res = sext <16 x i1> %cmp to <16 x i32> - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @icmp_ult_v8i64(<8 x i64>* %a) #0 { +define void @icmp_ult_v8i64(ptr %a) #0 { ; CHECK-LABEL: icmp_ult_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl8 @@ -278,12 +278,12 @@ define void @icmp_ult_v8i64(<8 x i64>* %a) #0 { ; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %ins = insertelement <8 x i64> undef, i64 63, i64 0 %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer %cmp = icmp ult <8 x i64> %op1, %op2 %res = sext <8 x i1> %cmp to <8 x i64> - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } @@ -291,7 +291,7 @@ define void @icmp_ult_v8i64(<8 x i64>* %a) #0 { ; LSHR ; -define void @lshr_v64i8(<64 x i8>* %a) #0 { +define void @lshr_v64i8(ptr %a) #0 { ; CHECK-LABEL: lshr_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -299,15 +299,15 @@ define void @lshr_v64i8(<64 x i8>* %a) #0 { ; CHECK-NEXT: lsr z0.b, p0/m, z0.b, #7 ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a + %op1 = load <64 x i8>, ptr %a %ins = insertelement <64 x i8> undef, i8 7, i64 0 %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer %res = lshr <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @lshr_v32i16(<32 x i16>* %a) #0 { +define void @lshr_v32i16(ptr %a) #0 { ; CHECK-LABEL: lshr_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -315,15 +315,15 @@ define void @lshr_v32i16(<32 x i16>* %a) #0 { ; CHECK-NEXT: lsr z0.h, p0/m, z0.h, #15 ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %ins = insertelement <32 x i16> undef, i16 15, i64 0 %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer %res = lshr <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @lshr_v16i32(<16 x i32>* %a) #0 { +define void @lshr_v16i32(ptr %a) #0 { ; CHECK-LABEL: lshr_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -331,15 +331,15 @@ define void @lshr_v16i32(<16 x i32>* %a) #0 { ; CHECK-NEXT: lsr z0.s, p0/m, z0.s, #31 ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %ins = insertelement <16 x i32> undef, i32 31, i64 0 %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer %res = lshr <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @lshr_v8i64(<8 x i64>* %a) #0 { +define void @lshr_v8i64(ptr %a) #0 { ; CHECK-LABEL: lshr_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl8 @@ -347,11 +347,11 @@ define void @lshr_v8i64(<8 x i64>* %a) #0 { ; CHECK-NEXT: lsr z0.d, p0/m, z0.d, #63 ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %ins = insertelement <8 x i64> undef, i64 63, i64 0 %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer %res = lshr <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } @@ -359,7 +359,7 @@ define void @lshr_v8i64(<8 x i64>* %a) #0 { ; MUL ; -define void @mul_v64i8(<64 x i8>* %a) #0 { +define void @mul_v64i8(ptr %a) #0 { ; CHECK-LABEL: mul_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -368,15 +368,15 @@ define void @mul_v64i8(<64 x i8>* %a) #0 { ; CHECK-NEXT: mul z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a + %op1 = load <64 x i8>, ptr %a %ins = insertelement <64 x i8> undef, i8 7, i64 0 %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer %res = mul <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @mul_v32i16(<32 x i16>* %a) #0 { +define void @mul_v32i16(ptr %a) #0 { ; CHECK-LABEL: mul_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -385,15 +385,15 @@ define void @mul_v32i16(<32 x i16>* %a) #0 { ; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %ins = insertelement <32 x i16> undef, i16 15, i64 0 %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer %res = mul <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @mul_v16i32(<16 x i32>* %a) #0 { +define void @mul_v16i32(ptr %a) #0 { ; CHECK-LABEL: mul_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -402,15 +402,15 @@ define void @mul_v16i32(<16 x i32>* %a) #0 { ; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %ins = insertelement <16 x i32> undef, i32 31, i64 0 %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer %res = mul <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @mul_v8i64(<8 x i64>* %a) #0 { +define void @mul_v8i64(ptr %a) #0 { ; CHECK-LABEL: mul_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl8 @@ -419,11 +419,11 @@ define void @mul_v8i64(<8 x i64>* %a) #0 { ; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %ins = insertelement <8 x i64> undef, i64 63, i64 0 %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer %res = mul <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } @@ -431,7 +431,7 @@ define void @mul_v8i64(<8 x i64>* %a) #0 { ; OR ; -define void @or_v64i8(<64 x i8>* %a) #0 { +define void @or_v64i8(ptr %a) #0 { ; CHECK-LABEL: or_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -439,15 +439,15 @@ define void @or_v64i8(<64 x i8>* %a) #0 { ; CHECK-NEXT: orr z0.b, z0.b, #0x7 ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a + %op1 = load <64 x i8>, ptr %a %ins = insertelement <64 x i8> undef, i8 7, i64 0 %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer %res = or <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @or_v32i16(<32 x i16>* %a) #0 { +define void @or_v32i16(ptr %a) #0 { ; CHECK-LABEL: or_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -455,15 +455,15 @@ define void @or_v32i16(<32 x i16>* %a) #0 { ; CHECK-NEXT: orr z0.h, z0.h, #0xf ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %ins = insertelement <32 x i16> undef, i16 15, i64 0 %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer %res = or <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @or_v16i32(<16 x i32>* %a) #0 { +define void @or_v16i32(ptr %a) #0 { ; CHECK-LABEL: or_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -471,15 +471,15 @@ define void @or_v16i32(<16 x i32>* %a) #0 { ; CHECK-NEXT: orr z0.s, z0.s, #0x1f ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %ins = insertelement <16 x i32> undef, i32 31, i64 0 %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer %res = or <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @or_v8i64(<8 x i64>* %a) #0 { +define void @or_v8i64(ptr %a) #0 { ; CHECK-LABEL: or_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl8 @@ -487,11 +487,11 @@ define void @or_v8i64(<8 x i64>* %a) #0 { ; CHECK-NEXT: orr z0.d, z0.d, #0x3f ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %ins = insertelement <8 x i64> undef, i64 63, i64 0 %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer %res = or <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } @@ -499,7 +499,7 @@ define void @or_v8i64(<8 x i64>* %a) #0 { ; SHL ; -define void @shl_v64i8(<64 x i8>* %a) #0 { +define void @shl_v64i8(ptr %a) #0 { ; CHECK-LABEL: shl_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -507,15 +507,15 @@ define void @shl_v64i8(<64 x i8>* %a) #0 { ; CHECK-NEXT: lsl z0.b, p0/m, z0.b, #7 ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a + %op1 = load <64 x i8>, ptr %a %ins = insertelement <64 x i8> undef, i8 7, i64 0 %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer %res = shl <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @shl_v32i16(<32 x i16>* %a) #0 { +define void @shl_v32i16(ptr %a) #0 { ; CHECK-LABEL: shl_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -523,15 +523,15 @@ define void @shl_v32i16(<32 x i16>* %a) #0 { ; CHECK-NEXT: lsl z0.h, p0/m, z0.h, #15 ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %ins = insertelement <32 x i16> undef, i16 15, i64 0 %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer %res = shl <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @shl_v16i32(<16 x i32>* %a) #0 { +define void @shl_v16i32(ptr %a) #0 { ; CHECK-LABEL: shl_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -539,15 +539,15 @@ define void @shl_v16i32(<16 x i32>* %a) #0 { ; CHECK-NEXT: lsl z0.s, p0/m, z0.s, #31 ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %ins = insertelement <16 x i32> undef, i32 31, i64 0 %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer %res = shl <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @shl_v8i64(<8 x i64>* %a) #0 { +define void @shl_v8i64(ptr %a) #0 { ; CHECK-LABEL: shl_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl8 @@ -555,11 +555,11 @@ define void @shl_v8i64(<8 x i64>* %a) #0 { ; CHECK-NEXT: lsl z0.d, p0/m, z0.d, #63 ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %ins = insertelement <8 x i64> undef, i64 63, i64 0 %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer %res = shl <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } @@ -567,7 +567,7 @@ define void @shl_v8i64(<8 x i64>* %a) #0 { ; SMAX ; -define void @smax_v64i8(<64 x i8>* %a) #0 { +define void @smax_v64i8(ptr %a) #0 { ; CHECK-LABEL: smax_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -576,15 +576,15 @@ define void @smax_v64i8(<64 x i8>* %a) #0 { ; CHECK-NEXT: smax z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a + %op1 = load <64 x i8>, ptr %a %ins = insertelement <64 x i8> undef, i8 7, i64 0 %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer %res = call <64 x i8> @llvm.smax.v64i8(<64 x i8> %op1, <64 x i8> %op2) - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @smax_v32i16(<32 x i16>* %a) #0 { +define void @smax_v32i16(ptr %a) #0 { ; CHECK-LABEL: smax_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -593,15 +593,15 @@ define void @smax_v32i16(<32 x i16>* %a) #0 { ; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %ins = insertelement <32 x i16> undef, i16 15, i64 0 %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer %res = call <32 x i16> @llvm.smax.v32i16(<32 x i16> %op1, <32 x i16> %op2) - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @smax_v16i32(<16 x i32>* %a) #0 { +define void @smax_v16i32(ptr %a) #0 { ; CHECK-LABEL: smax_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -610,15 +610,15 @@ define void @smax_v16i32(<16 x i32>* %a) #0 { ; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %ins = insertelement <16 x i32> undef, i32 31, i64 0 %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer %res = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %op1, <16 x i32> %op2) - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @smax_v8i64(<8 x i64>* %a) #0 { +define void @smax_v8i64(ptr %a) #0 { ; CHECK-LABEL: smax_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl8 @@ -627,11 +627,11 @@ define void @smax_v8i64(<8 x i64>* %a) #0 { ; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %ins = insertelement <8 x i64> undef, i64 63, i64 0 %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer %res = call <8 x i64> @llvm.smax.v8i64(<8 x i64> %op1, <8 x i64> %op2) - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } @@ -639,7 +639,7 @@ define void @smax_v8i64(<8 x i64>* %a) #0 { ; SMIN ; -define void @smin_v64i8(<64 x i8>* %a) #0 { +define void @smin_v64i8(ptr %a) #0 { ; CHECK-LABEL: smin_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -648,15 +648,15 @@ define void @smin_v64i8(<64 x i8>* %a) #0 { ; CHECK-NEXT: smin z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a + %op1 = load <64 x i8>, ptr %a %ins = insertelement <64 x i8> undef, i8 7, i64 0 %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer %res = call <64 x i8> @llvm.smin.v64i8(<64 x i8> %op1, <64 x i8> %op2) - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @smin_v32i16(<32 x i16>* %a) #0 { +define void @smin_v32i16(ptr %a) #0 { ; CHECK-LABEL: smin_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -665,15 +665,15 @@ define void @smin_v32i16(<32 x i16>* %a) #0 { ; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %ins = insertelement <32 x i16> undef, i16 15, i64 0 %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer %res = call <32 x i16> @llvm.smin.v32i16(<32 x i16> %op1, <32 x i16> %op2) - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @smin_v16i32(<16 x i32>* %a) #0 { +define void @smin_v16i32(ptr %a) #0 { ; CHECK-LABEL: smin_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -682,15 +682,15 @@ define void @smin_v16i32(<16 x i32>* %a) #0 { ; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %ins = insertelement <16 x i32> undef, i32 31, i64 0 %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer %res = call <16 x i32> @llvm.smin.v16i32(<16 x i32> %op1, <16 x i32> %op2) - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @smin_v8i64(<8 x i64>* %a) #0 { +define void @smin_v8i64(ptr %a) #0 { ; CHECK-LABEL: smin_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl8 @@ -699,11 +699,11 @@ define void @smin_v8i64(<8 x i64>* %a) #0 { ; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %ins = insertelement <8 x i64> undef, i64 63, i64 0 %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer %res = call <8 x i64> @llvm.smin.v8i64(<8 x i64> %op1, <8 x i64> %op2) - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } @@ -711,7 +711,7 @@ define void @smin_v8i64(<8 x i64>* %a) #0 { ; SUB ; -define void @sub_v64i8(<64 x i8>* %a) #0 { +define void @sub_v64i8(ptr %a) #0 { ; CHECK-LABEL: sub_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -719,15 +719,15 @@ define void @sub_v64i8(<64 x i8>* %a) #0 { ; CHECK-NEXT: sub z0.b, z0.b, #7 // =0x7 ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a + %op1 = load <64 x i8>, ptr %a %ins = insertelement <64 x i8> undef, i8 7, i64 0 %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer %res = sub <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @sub_v32i16(<32 x i16>* %a) #0 { +define void @sub_v32i16(ptr %a) #0 { ; CHECK-LABEL: sub_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -735,15 +735,15 @@ define void @sub_v32i16(<32 x i16>* %a) #0 { ; CHECK-NEXT: sub z0.h, z0.h, #15 // =0xf ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %ins = insertelement <32 x i16> undef, i16 15, i64 0 %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer %res = sub <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @sub_v16i32(<16 x i32>* %a) #0 { +define void @sub_v16i32(ptr %a) #0 { ; CHECK-LABEL: sub_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -751,15 +751,15 @@ define void @sub_v16i32(<16 x i32>* %a) #0 { ; CHECK-NEXT: sub z0.s, z0.s, #31 // =0x1f ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %ins = insertelement <16 x i32> undef, i32 31, i64 0 %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer %res = sub <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @sub_v8i64(<8 x i64>* %a) #0 { +define void @sub_v8i64(ptr %a) #0 { ; CHECK-LABEL: sub_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl8 @@ -767,11 +767,11 @@ define void @sub_v8i64(<8 x i64>* %a) #0 { ; CHECK-NEXT: sub z0.d, z0.d, #63 // =0x3f ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %ins = insertelement <8 x i64> undef, i64 63, i64 0 %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer %res = sub <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } @@ -779,7 +779,7 @@ define void @sub_v8i64(<8 x i64>* %a) #0 { ; UMAX ; -define void @umax_v64i8(<64 x i8>* %a) #0 { +define void @umax_v64i8(ptr %a) #0 { ; CHECK-LABEL: umax_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -788,15 +788,15 @@ define void @umax_v64i8(<64 x i8>* %a) #0 { ; CHECK-NEXT: umax z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a + %op1 = load <64 x i8>, ptr %a %ins = insertelement <64 x i8> undef, i8 7, i64 0 %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer %res = call <64 x i8> @llvm.umax.v64i8(<64 x i8> %op1, <64 x i8> %op2) - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @umax_v32i16(<32 x i16>* %a) #0 { +define void @umax_v32i16(ptr %a) #0 { ; CHECK-LABEL: umax_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -805,15 +805,15 @@ define void @umax_v32i16(<32 x i16>* %a) #0 { ; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %ins = insertelement <32 x i16> undef, i16 15, i64 0 %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer %res = call <32 x i16> @llvm.umax.v32i16(<32 x i16> %op1, <32 x i16> %op2) - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @umax_v16i32(<16 x i32>* %a) #0 { +define void @umax_v16i32(ptr %a) #0 { ; CHECK-LABEL: umax_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -822,15 +822,15 @@ define void @umax_v16i32(<16 x i32>* %a) #0 { ; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %ins = insertelement <16 x i32> undef, i32 31, i64 0 %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer %res = call <16 x i32> @llvm.umax.v16i32(<16 x i32> %op1, <16 x i32> %op2) - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @umax_v8i64(<8 x i64>* %a) #0 { +define void @umax_v8i64(ptr %a) #0 { ; CHECK-LABEL: umax_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl8 @@ -839,11 +839,11 @@ define void @umax_v8i64(<8 x i64>* %a) #0 { ; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %ins = insertelement <8 x i64> undef, i64 63, i64 0 %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer %res = call <8 x i64> @llvm.umax.v8i64(<8 x i64> %op1, <8 x i64> %op2) - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } @@ -851,7 +851,7 @@ define void @umax_v8i64(<8 x i64>* %a) #0 { ; UMIN ; -define void @umin_v64i8(<64 x i8>* %a) #0 { +define void @umin_v64i8(ptr %a) #0 { ; CHECK-LABEL: umin_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -860,15 +860,15 @@ define void @umin_v64i8(<64 x i8>* %a) #0 { ; CHECK-NEXT: umin z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a + %op1 = load <64 x i8>, ptr %a %ins = insertelement <64 x i8> undef, i8 7, i64 0 %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer %res = call <64 x i8> @llvm.umin.v64i8(<64 x i8> %op1, <64 x i8> %op2) - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @umin_v32i16(<32 x i16>* %a) #0 { +define void @umin_v32i16(ptr %a) #0 { ; CHECK-LABEL: umin_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -877,15 +877,15 @@ define void @umin_v32i16(<32 x i16>* %a) #0 { ; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %ins = insertelement <32 x i16> undef, i16 15, i64 0 %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer %res = call <32 x i16> @llvm.umin.v32i16(<32 x i16> %op1, <32 x i16> %op2) - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @umin_v16i32(<16 x i32>* %a) #0 { +define void @umin_v16i32(ptr %a) #0 { ; CHECK-LABEL: umin_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -894,15 +894,15 @@ define void @umin_v16i32(<16 x i32>* %a) #0 { ; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %ins = insertelement <16 x i32> undef, i32 31, i64 0 %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer %res = call <16 x i32> @llvm.umin.v16i32(<16 x i32> %op1, <16 x i32> %op2) - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @umin_v8i64(<8 x i64>* %a) #0 { +define void @umin_v8i64(ptr %a) #0 { ; CHECK-LABEL: umin_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl8 @@ -911,11 +911,11 @@ define void @umin_v8i64(<8 x i64>* %a) #0 { ; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %ins = insertelement <8 x i64> undef, i64 63, i64 0 %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer %res = call <8 x i64> @llvm.umin.v8i64(<8 x i64> %op1, <8 x i64> %op2) - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } @@ -923,7 +923,7 @@ define void @umin_v8i64(<8 x i64>* %a) #0 { ; XOR ; -define void @xor_v64i8(<64 x i8>* %a) #0 { +define void @xor_v64i8(ptr %a) #0 { ; CHECK-LABEL: xor_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -931,15 +931,15 @@ define void @xor_v64i8(<64 x i8>* %a) #0 { ; CHECK-NEXT: eor z0.b, z0.b, #0x7 ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a + %op1 = load <64 x i8>, ptr %a %ins = insertelement <64 x i8> undef, i8 7, i64 0 %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer %res = xor <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @xor_v32i16(<32 x i16>* %a) #0 { +define void @xor_v32i16(ptr %a) #0 { ; CHECK-LABEL: xor_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -947,15 +947,15 @@ define void @xor_v32i16(<32 x i16>* %a) #0 { ; CHECK-NEXT: eor z0.h, z0.h, #0xf ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %ins = insertelement <32 x i16> undef, i16 15, i64 0 %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer %res = xor <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @xor_v16i32(<16 x i32>* %a) #0 { +define void @xor_v16i32(ptr %a) #0 { ; CHECK-LABEL: xor_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -963,15 +963,15 @@ define void @xor_v16i32(<16 x i32>* %a) #0 { ; CHECK-NEXT: eor z0.s, z0.s, #0x1f ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %ins = insertelement <16 x i32> undef, i32 31, i64 0 %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer %res = xor <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @xor_v8i64(<8 x i64>* %a) #0 { +define void @xor_v8i64(ptr %a) #0 { ; CHECK-LABEL: xor_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl8 @@ -979,11 +979,11 @@ define void @xor_v8i64(<8 x i64>* %a) #0 { ; CHECK-NEXT: eor z0.d, z0.d, #0x3f ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %ins = insertelement <8 x i64> undef, i64 63, i64 0 %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer %res = xor <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-log.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-log.ll index 9e9ce74..d8e6374 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-log.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-log.ll @@ -29,7 +29,7 @@ define <16 x i8> @and_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) #0 ret <16 x i8> %res } -define void @and_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @and_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: and_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -38,14 +38,14 @@ define void @and_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %res = and <32 x i8> %op1, %op2 - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @and_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @and_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: and_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -68,14 +68,14 @@ define void @and_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: and z0.d, z0.d, z1.d ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = and <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @and_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @and_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: and_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -84,14 +84,14 @@ define void @and_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %res = and <128 x i8> %op1, %op2 - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @and_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @and_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: and_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -100,10 +100,10 @@ define void @and_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %res = and <256 x i8> %op1, %op2 - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -127,7 +127,7 @@ define <8 x i16> @and_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) #0 ret <8 x i16> %res } -define void @and_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @and_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: and_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -136,14 +136,14 @@ define void @and_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %res = and <16 x i16> %op1, %op2 - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @and_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @and_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: and_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -166,14 +166,14 @@ define void @and_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: and z0.d, z0.d, z1.d ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = and <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @and_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @and_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: and_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -182,14 +182,14 @@ define void @and_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %res = and <64 x i16> %op1, %op2 - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @and_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @and_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: and_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -198,10 +198,10 @@ define void @and_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %res = and <128 x i16> %op1, %op2 - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -225,7 +225,7 @@ define <4 x i32> @and_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) #0 ret <4 x i32> %res } -define void @and_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @and_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: and_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -234,14 +234,14 @@ define void @and_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %res = and <8 x i32> %op1, %op2 - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @and_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @and_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: and_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -264,14 +264,14 @@ define void @and_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: and z0.d, z0.d, z1.d ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %res = and <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @and_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @and_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: and_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -280,14 +280,14 @@ define void @and_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %res = and <32 x i32> %op1, %op2 - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @and_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @and_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: and_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -296,10 +296,10 @@ define void @and_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %res = and <64 x i32> %op1, %op2 - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -323,7 +323,7 @@ define <2 x i64> @and_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) #0 ret <2 x i64> %res } -define void @and_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @and_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: and_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -332,14 +332,14 @@ define void @and_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %res = and <4 x i64> %op1, %op2 - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @and_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @and_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: and_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -362,14 +362,14 @@ define void @and_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: and z0.d, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %res = and <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @and_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @and_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: and_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -378,14 +378,14 @@ define void @and_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %res = and <16 x i64> %op1, %op2 - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @and_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @and_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: and_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -394,10 +394,10 @@ define void @and_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %res = and <32 x i64> %op1, %op2 - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } @@ -425,7 +425,7 @@ define <16 x i8> @or_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) #0 ret <16 x i8> %res } -define void @or_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @or_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: or_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -434,14 +434,14 @@ define void @or_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %res = or <32 x i8> %op1, %op2 - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @or_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @or_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: or_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -464,14 +464,14 @@ define void @or_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: orr z0.d, z0.d, z1.d ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = or <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @or_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @or_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: or_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -480,14 +480,14 @@ define void @or_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %res = or <128 x i8> %op1, %op2 - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @or_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @or_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: or_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -496,10 +496,10 @@ define void @or_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %res = or <256 x i8> %op1, %op2 - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -523,7 +523,7 @@ define <8 x i16> @or_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) #0 ret <8 x i16> %res } -define void @or_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @or_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: or_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -532,14 +532,14 @@ define void @or_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %res = or <16 x i16> %op1, %op2 - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @or_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @or_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: or_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -562,14 +562,14 @@ define void @or_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: orr z0.d, z0.d, z1.d ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = or <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @or_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @or_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: or_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -578,14 +578,14 @@ define void @or_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %res = or <64 x i16> %op1, %op2 - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @or_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @or_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: or_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -594,10 +594,10 @@ define void @or_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %res = or <128 x i16> %op1, %op2 - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -621,7 +621,7 @@ define <4 x i32> @or_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) #0 ret <4 x i32> %res } -define void @or_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @or_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: or_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -630,14 +630,14 @@ define void @or_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %res = or <8 x i32> %op1, %op2 - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @or_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @or_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: or_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -660,14 +660,14 @@ define void @or_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: orr z0.d, z0.d, z1.d ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %res = or <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @or_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @or_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: or_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -676,14 +676,14 @@ define void @or_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %res = or <32 x i32> %op1, %op2 - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @or_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @or_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: or_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -692,10 +692,10 @@ define void @or_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %res = or <64 x i32> %op1, %op2 - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -719,7 +719,7 @@ define <2 x i64> @or_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) #0 ret <2 x i64> %res } -define void @or_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @or_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: or_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -728,14 +728,14 @@ define void @or_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %res = or <4 x i64> %op1, %op2 - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @or_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @or_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: or_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -758,14 +758,14 @@ define void @or_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: orr z0.d, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %res = or <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @or_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @or_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: or_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -774,14 +774,14 @@ define void @or_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %res = or <16 x i64> %op1, %op2 - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @or_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @or_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: or_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -790,10 +790,10 @@ define void @or_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %res = or <32 x i64> %op1, %op2 - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } @@ -821,7 +821,7 @@ define <16 x i8> @xor_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) #0 ret <16 x i8> %res } -define void @xor_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @xor_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: xor_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -830,14 +830,14 @@ define void @xor_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %res = xor <32 x i8> %op1, %op2 - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @xor_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @xor_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: xor_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -860,14 +860,14 @@ define void @xor_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: eor z0.d, z0.d, z1.d ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = xor <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @xor_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @xor_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: xor_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -876,14 +876,14 @@ define void @xor_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %res = xor <128 x i8> %op1, %op2 - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @xor_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @xor_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: xor_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -892,10 +892,10 @@ define void @xor_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %res = xor <256 x i8> %op1, %op2 - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -919,7 +919,7 @@ define <8 x i16> @xor_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) #0 ret <8 x i16> %res } -define void @xor_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @xor_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: xor_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -928,14 +928,14 @@ define void @xor_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %res = xor <16 x i16> %op1, %op2 - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @xor_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @xor_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: xor_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -958,14 +958,14 @@ define void @xor_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: eor z0.d, z0.d, z1.d ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = xor <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @xor_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @xor_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: xor_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -974,14 +974,14 @@ define void @xor_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %res = xor <64 x i16> %op1, %op2 - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @xor_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @xor_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: xor_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -990,10 +990,10 @@ define void @xor_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %res = xor <128 x i16> %op1, %op2 - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -1017,7 +1017,7 @@ define <4 x i32> @xor_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) #0 ret <4 x i32> %res } -define void @xor_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @xor_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: xor_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1026,14 +1026,14 @@ define void @xor_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %res = xor <8 x i32> %op1, %op2 - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @xor_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @xor_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: xor_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1056,14 +1056,14 @@ define void @xor_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: eor z0.d, z0.d, z1.d ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %res = xor <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @xor_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @xor_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: xor_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1072,14 +1072,14 @@ define void @xor_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %res = xor <32 x i32> %op1, %op2 - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @xor_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @xor_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: xor_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1088,10 +1088,10 @@ define void @xor_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %res = xor <64 x i32> %op1, %op2 - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -1115,7 +1115,7 @@ define <2 x i64> @xor_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) #0 ret <2 x i64> %res } -define void @xor_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @xor_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: xor_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1124,14 +1124,14 @@ define void @xor_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %res = xor <4 x i64> %op1, %op2 - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @xor_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @xor_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: xor_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1154,14 +1154,14 @@ define void @xor_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: eor z0.d, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %res = xor <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @xor_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @xor_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: xor_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1170,14 +1170,14 @@ define void @xor_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %res = xor <16 x i64> %op1, %op2 - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @xor_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @xor_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: xor_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1186,10 +1186,10 @@ define void @xor_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %res = xor <32 x i64> %op1, %op2 - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll index ca8bf94..b13852a 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll @@ -29,7 +29,7 @@ define <16 x i8> @smax_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) # ret <16 x i8> %res } -define void @smax_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @smax_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: smax_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -38,14 +38,14 @@ define void @smax_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: smax z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %res = call <32 x i8> @llvm.smax.v32i8(<32 x i8> %op1, <32 x i8> %op2) - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @smax_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @smax_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: smax_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -68,14 +68,14 @@ define void @smax_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: smax z0.b, p0/m, z0.b, z1.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = call <64 x i8> @llvm.smax.v64i8(<64 x i8> %op1, <64 x i8> %op2) - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @smax_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @smax_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: smax_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -84,14 +84,14 @@ define void @smax_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: smax z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %res = call <128 x i8> @llvm.smax.v128i8(<128 x i8> %op1, <128 x i8> %op2) - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @smax_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @smax_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: smax_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -100,10 +100,10 @@ define void @smax_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: smax z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %res = call <256 x i8> @llvm.smax.v256i8(<256 x i8> %op1, <256 x i8> %op2) - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -127,7 +127,7 @@ define <8 x i16> @smax_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) # ret <8 x i16> %res } -define void @smax_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @smax_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: smax_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -136,14 +136,14 @@ define void @smax_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %res = call <16 x i16> @llvm.smax.v16i16(<16 x i16> %op1, <16 x i16> %op2) - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @smax_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @smax_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: smax_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -166,14 +166,14 @@ define void @smax_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: smax z0.h, p0/m, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = call <32 x i16> @llvm.smax.v32i16(<32 x i16> %op1, <32 x i16> %op2) - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @smax_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @smax_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: smax_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -182,14 +182,14 @@ define void @smax_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %res = call <64 x i16> @llvm.smax.v64i16(<64 x i16> %op1, <64 x i16> %op2) - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @smax_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @smax_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: smax_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -198,10 +198,10 @@ define void @smax_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) # ; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %res = call <128 x i16> @llvm.smax.v128i16(<128 x i16> %op1, <128 x i16> %op2) - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -225,7 +225,7 @@ define <4 x i32> @smax_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) # ret <4 x i32> %res } -define void @smax_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @smax_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: smax_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -234,14 +234,14 @@ define void @smax_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %res = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %op1, <8 x i32> %op2) - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @smax_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @smax_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: smax_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -264,14 +264,14 @@ define void @smax_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: smax z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %res = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %op1, <16 x i32> %op2) - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @smax_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @smax_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: smax_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -280,14 +280,14 @@ define void @smax_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %res = call <32 x i32> @llvm.smax.v32i32(<32 x i32> %op1, <32 x i32> %op2) - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @smax_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @smax_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: smax_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -296,10 +296,10 @@ define void @smax_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %res = call <64 x i32> @llvm.smax.v64i32(<64 x i32> %op1, <64 x i32> %op2) - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -331,7 +331,7 @@ define <2 x i64> @smax_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) # ret <2 x i64> %res } -define void @smax_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @smax_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: smax_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -340,14 +340,14 @@ define void @smax_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %res = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %op1, <4 x i64> %op2) - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @smax_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @smax_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: smax_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -370,14 +370,14 @@ define void @smax_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: smax z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %res = call <8 x i64> @llvm.smax.v8i64(<8 x i64> %op1, <8 x i64> %op2) - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @smax_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @smax_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: smax_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -386,14 +386,14 @@ define void @smax_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %res = call <16 x i64> @llvm.smax.v16i64(<16 x i64> %op1, <16 x i64> %op2) - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @smax_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @smax_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: smax_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -402,10 +402,10 @@ define void @smax_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %res = call <32 x i64> @llvm.smax.v32i64(<32 x i64> %op1, <32 x i64> %op2) - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } @@ -433,7 +433,7 @@ define <16 x i8> @smin_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) # ret <16 x i8> %res } -define void @smin_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @smin_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: smin_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -442,14 +442,14 @@ define void @smin_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: smin z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %res = call <32 x i8> @llvm.smin.v32i8(<32 x i8> %op1, <32 x i8> %op2) - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @smin_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @smin_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: smin_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -472,14 +472,14 @@ define void @smin_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: smin z0.b, p0/m, z0.b, z1.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = call <64 x i8> @llvm.smin.v64i8(<64 x i8> %op1, <64 x i8> %op2) - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @smin_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @smin_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: smin_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -488,14 +488,14 @@ define void @smin_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: smin z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %res = call <128 x i8> @llvm.smin.v128i8(<128 x i8> %op1, <128 x i8> %op2) - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @smin_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @smin_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: smin_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -504,10 +504,10 @@ define void @smin_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: smin z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %res = call <256 x i8> @llvm.smin.v256i8(<256 x i8> %op1, <256 x i8> %op2) - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -531,7 +531,7 @@ define <8 x i16> @smin_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) # ret <8 x i16> %res } -define void @smin_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @smin_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: smin_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -540,14 +540,14 @@ define void @smin_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %res = call <16 x i16> @llvm.smin.v16i16(<16 x i16> %op1, <16 x i16> %op2) - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @smin_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @smin_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: smin_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -570,14 +570,14 @@ define void @smin_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: smin z0.h, p0/m, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = call <32 x i16> @llvm.smin.v32i16(<32 x i16> %op1, <32 x i16> %op2) - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @smin_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @smin_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: smin_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -586,14 +586,14 @@ define void @smin_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %res = call <64 x i16> @llvm.smin.v64i16(<64 x i16> %op1, <64 x i16> %op2) - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @smin_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @smin_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: smin_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -602,10 +602,10 @@ define void @smin_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) # ; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %res = call <128 x i16> @llvm.smin.v128i16(<128 x i16> %op1, <128 x i16> %op2) - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -629,7 +629,7 @@ define <4 x i32> @smin_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) # ret <4 x i32> %res } -define void @smin_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @smin_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: smin_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -638,14 +638,14 @@ define void @smin_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %res = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %op1, <8 x i32> %op2) - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @smin_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @smin_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: smin_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -668,14 +668,14 @@ define void @smin_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: smin z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %res = call <16 x i32> @llvm.smin.v16i32(<16 x i32> %op1, <16 x i32> %op2) - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @smin_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @smin_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: smin_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -684,14 +684,14 @@ define void @smin_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %res = call <32 x i32> @llvm.smin.v32i32(<32 x i32> %op1, <32 x i32> %op2) - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @smin_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @smin_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: smin_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -700,10 +700,10 @@ define void @smin_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %res = call <64 x i32> @llvm.smin.v64i32(<64 x i32> %op1, <64 x i32> %op2) - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -735,7 +735,7 @@ define <2 x i64> @smin_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) # ret <2 x i64> %res } -define void @smin_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @smin_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: smin_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -744,14 +744,14 @@ define void @smin_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %res = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %op1, <4 x i64> %op2) - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @smin_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @smin_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: smin_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -774,14 +774,14 @@ define void @smin_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: smin z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %res = call <8 x i64> @llvm.smin.v8i64(<8 x i64> %op1, <8 x i64> %op2) - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @smin_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @smin_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: smin_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -790,14 +790,14 @@ define void @smin_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %res = call <16 x i64> @llvm.smin.v16i64(<16 x i64> %op1, <16 x i64> %op2) - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @smin_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @smin_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: smin_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -806,10 +806,10 @@ define void @smin_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %res = call <32 x i64> @llvm.smin.v32i64(<32 x i64> %op1, <32 x i64> %op2) - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } @@ -837,7 +837,7 @@ define <16 x i8> @umax_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) # ret <16 x i8> %res } -define void @umax_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @umax_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: umax_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -846,14 +846,14 @@ define void @umax_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: umax z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %res = call <32 x i8> @llvm.umax.v32i8(<32 x i8> %op1, <32 x i8> %op2) - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @umax_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @umax_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: umax_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -876,14 +876,14 @@ define void @umax_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: umax z0.b, p0/m, z0.b, z1.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = call <64 x i8> @llvm.umax.v64i8(<64 x i8> %op1, <64 x i8> %op2) - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @umax_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @umax_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: umax_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -892,14 +892,14 @@ define void @umax_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: umax z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %res = call <128 x i8> @llvm.umax.v128i8(<128 x i8> %op1, <128 x i8> %op2) - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @umax_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @umax_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: umax_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -908,10 +908,10 @@ define void @umax_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: umax z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %res = call <256 x i8> @llvm.umax.v256i8(<256 x i8> %op1, <256 x i8> %op2) - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -935,7 +935,7 @@ define <8 x i16> @umax_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) # ret <8 x i16> %res } -define void @umax_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @umax_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: umax_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -944,14 +944,14 @@ define void @umax_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %res = call <16 x i16> @llvm.umax.v16i16(<16 x i16> %op1, <16 x i16> %op2) - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @umax_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @umax_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: umax_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -974,14 +974,14 @@ define void @umax_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: umax z0.h, p0/m, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = call <32 x i16> @llvm.umax.v32i16(<32 x i16> %op1, <32 x i16> %op2) - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @umax_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @umax_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: umax_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -990,14 +990,14 @@ define void @umax_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %res = call <64 x i16> @llvm.umax.v64i16(<64 x i16> %op1, <64 x i16> %op2) - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @umax_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @umax_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: umax_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1006,10 +1006,10 @@ define void @umax_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) # ; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %res = call <128 x i16> @llvm.umax.v128i16(<128 x i16> %op1, <128 x i16> %op2) - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -1033,7 +1033,7 @@ define <4 x i32> @umax_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) # ret <4 x i32> %res } -define void @umax_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @umax_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: umax_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1042,14 +1042,14 @@ define void @umax_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %res = call <8 x i32> @llvm.umax.v8i32(<8 x i32> %op1, <8 x i32> %op2) - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @umax_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @umax_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: umax_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1072,14 +1072,14 @@ define void @umax_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: umax z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %res = call <16 x i32> @llvm.umax.v16i32(<16 x i32> %op1, <16 x i32> %op2) - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @umax_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @umax_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: umax_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1088,14 +1088,14 @@ define void @umax_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %res = call <32 x i32> @llvm.umax.v32i32(<32 x i32> %op1, <32 x i32> %op2) - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @umax_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @umax_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: umax_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1104,10 +1104,10 @@ define void @umax_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %res = call <64 x i32> @llvm.umax.v64i32(<64 x i32> %op1, <64 x i32> %op2) - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -1139,7 +1139,7 @@ define <2 x i64> @umax_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) # ret <2 x i64> %res } -define void @umax_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @umax_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: umax_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1148,14 +1148,14 @@ define void @umax_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %res = call <4 x i64> @llvm.umax.v4i64(<4 x i64> %op1, <4 x i64> %op2) - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @umax_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @umax_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: umax_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1178,14 +1178,14 @@ define void @umax_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: umax z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %res = call <8 x i64> @llvm.umax.v8i64(<8 x i64> %op1, <8 x i64> %op2) - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @umax_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @umax_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: umax_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1194,14 +1194,14 @@ define void @umax_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %res = call <16 x i64> @llvm.umax.v16i64(<16 x i64> %op1, <16 x i64> %op2) - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @umax_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @umax_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: umax_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1210,10 +1210,10 @@ define void @umax_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %res = call <32 x i64> @llvm.umax.v32i64(<32 x i64> %op1, <32 x i64> %op2) - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } @@ -1241,7 +1241,7 @@ define <16 x i8> @umin_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) # ret <16 x i8> %res } -define void @umin_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @umin_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: umin_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -1250,14 +1250,14 @@ define void @umin_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: umin z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %res = call <32 x i8> @llvm.umin.v32i8(<32 x i8> %op1, <32 x i8> %op2) - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @umin_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @umin_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: umin_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -1280,14 +1280,14 @@ define void @umin_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: umin z0.b, p0/m, z0.b, z1.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = call <64 x i8> @llvm.umin.v64i8(<64 x i8> %op1, <64 x i8> %op2) - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @umin_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @umin_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: umin_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -1296,14 +1296,14 @@ define void @umin_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: umin z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %res = call <128 x i8> @llvm.umin.v128i8(<128 x i8> %op1, <128 x i8> %op2) - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @umin_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @umin_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: umin_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -1312,10 +1312,10 @@ define void @umin_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: umin z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %res = call <256 x i8> @llvm.umin.v256i8(<256 x i8> %op1, <256 x i8> %op2) - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -1339,7 +1339,7 @@ define <8 x i16> @umin_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) # ret <8 x i16> %res } -define void @umin_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @umin_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: umin_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -1348,14 +1348,14 @@ define void @umin_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %res = call <16 x i16> @llvm.umin.v16i16(<16 x i16> %op1, <16 x i16> %op2) - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @umin_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @umin_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: umin_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -1378,14 +1378,14 @@ define void @umin_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: umin z0.h, p0/m, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = call <32 x i16> @llvm.umin.v32i16(<32 x i16> %op1, <32 x i16> %op2) - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @umin_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @umin_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: umin_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -1394,14 +1394,14 @@ define void @umin_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %res = call <64 x i16> @llvm.umin.v64i16(<64 x i16> %op1, <64 x i16> %op2) - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @umin_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @umin_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: umin_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1410,10 +1410,10 @@ define void @umin_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) # ; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %res = call <128 x i16> @llvm.umin.v128i16(<128 x i16> %op1, <128 x i16> %op2) - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -1437,7 +1437,7 @@ define <4 x i32> @umin_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) # ret <4 x i32> %res } -define void @umin_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @umin_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: umin_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1446,14 +1446,14 @@ define void @umin_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %res = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %op1, <8 x i32> %op2) - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @umin_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @umin_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: umin_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1476,14 +1476,14 @@ define void @umin_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: umin z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %res = call <16 x i32> @llvm.umin.v16i32(<16 x i32> %op1, <16 x i32> %op2) - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @umin_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @umin_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: umin_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1492,14 +1492,14 @@ define void @umin_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %res = call <32 x i32> @llvm.umin.v32i32(<32 x i32> %op1, <32 x i32> %op2) - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @umin_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @umin_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: umin_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1508,10 +1508,10 @@ define void @umin_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %res = call <64 x i32> @llvm.umin.v64i32(<64 x i32> %op1, <64 x i32> %op2) - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -1543,7 +1543,7 @@ define <2 x i64> @umin_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) # ret <2 x i64> %res } -define void @umin_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @umin_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: umin_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1552,14 +1552,14 @@ define void @umin_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %res = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %op1, <4 x i64> %op2) - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @umin_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @umin_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: umin_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1582,14 +1582,14 @@ define void @umin_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: umin z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %res = call <8 x i64> @llvm.umin.v8i64(<8 x i64> %op1, <8 x i64> %op2) - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @umin_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @umin_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: umin_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1598,14 +1598,14 @@ define void @umin_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %res = call <16 x i64> @llvm.umin.v16i64(<16 x i64> %op1, <16 x i64> %op2) - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @umin_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @umin_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: umin_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1614,10 +1614,10 @@ define void @umin_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %res = call <32 x i64> @llvm.umin.v32i64(<32 x i64> %op1, <32 x i64> %op2) - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll index b050a4d..bf9a477 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll @@ -63,7 +63,7 @@ define <16 x i8> @smulh_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) ret <16 x i8> %res } -define void @smulh_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @smulh_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: smulh_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -72,18 +72,18 @@ define void @smulh_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: smulh z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %1 = sext <32 x i8> %op1 to <32 x i16> %2 = sext <32 x i8> %op2 to <32 x i16> %mul = mul <32 x i16> %1, %2 %shr = lshr <32 x i16> %mul, %res = trunc <32 x i16> %shr to <32 x i8> - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @smulh_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @smulh_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: smulh_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -134,8 +134,8 @@ define void @smulh_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: smulh z0.b, p0/m, z0.b, z1.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %insert = insertelement <64 x i16> undef, i16 8, i64 0 %splat = shufflevector <64 x i16> %insert, <64 x i16> undef, <64 x i32> zeroinitializer %1 = sext <64 x i8> %op1 to <64 x i16> @@ -143,11 +143,11 @@ define void @smulh_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { %mul = mul <64 x i16> %1, %2 %shr = lshr <64 x i16> %mul, %res = trunc <64 x i16> %shr to <64 x i8> - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @smulh_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @smulh_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: smulh_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -156,18 +156,18 @@ define void @smulh_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: smulh z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %1 = sext <128 x i8> %op1 to <128 x i16> %2 = sext <128 x i8> %op2 to <128 x i16> %mul = mul <128 x i16> %1, %2 %shr = lshr <128 x i16> %mul, %res = trunc <128 x i16> %shr to <128 x i8> - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @smulh_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @smulh_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: smulh_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -176,14 +176,14 @@ define void @smulh_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 ; CHECK-NEXT: smulh z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %1 = sext <256 x i8> %op1 to <256 x i16> %2 = sext <256 x i8> %op2 to <256 x i16> %mul = mul <256 x i16> %1, %2 %shr = lshr <256 x i16> %mul, %res = trunc <256 x i16> %shr to <256 x i8> - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -227,7 +227,7 @@ define <8 x i16> @smulh_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) ret <8 x i16> %res } -define void @smulh_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @smulh_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: smulh_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -236,18 +236,18 @@ define void @smulh_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: smulh z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %1 = sext <16 x i16> %op1 to <16 x i32> %2 = sext <16 x i16> %op2 to <16 x i32> %mul = mul <16 x i32> %1, %2 %shr = lshr <16 x i32> %mul, %res = trunc <16 x i32> %shr to <16 x i16> - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @smulh_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @smulh_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: smulh_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -289,18 +289,18 @@ define void @smulh_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: smulh z0.h, p0/m, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %1 = sext <32 x i16> %op1 to <32 x i32> %2 = sext <32 x i16> %op2 to <32 x i32> %mul = mul <32 x i32> %1, %2 %shr = lshr <32 x i32> %mul, %res = trunc <32 x i32> %shr to <32 x i16> - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @smulh_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @smulh_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: smulh_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -309,18 +309,18 @@ define void @smulh_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: smulh z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %1 = sext <64 x i16> %op1 to <64 x i32> %2 = sext <64 x i16> %op2 to <64 x i32> %mul = mul <64 x i32> %1, %2 %shr = lshr <64 x i32> %mul, %res = trunc <64 x i32> %shr to <64 x i16> - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @smulh_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @smulh_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: smulh_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -329,14 +329,14 @@ define void @smulh_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) ; CHECK-NEXT: smulh z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %1 = sext <128 x i16> %op1 to <128 x i32> %2 = sext <128 x i16> %op2 to <128 x i32> %mul = mul <128 x i32> %1, %2 %shr = lshr <128 x i32> %mul, %res = trunc <128 x i32> %shr to <128 x i16> - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -374,7 +374,7 @@ define <4 x i32> @smulh_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) ret <4 x i32> %res } -define void @smulh_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @smulh_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: smulh_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -383,18 +383,18 @@ define void @smulh_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: smulh z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %1 = sext <8 x i32> %op1 to <8 x i64> %2 = sext <8 x i32> %op2 to <8 x i64> %mul = mul <8 x i64> %1, %2 %shr = lshr <8 x i64> %mul, %res = trunc <8 x i64> %shr to <8 x i32> - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @smulh_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @smulh_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: smulh_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -436,18 +436,18 @@ define void @smulh_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: smulh z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %1 = sext <16 x i32> %op1 to <16 x i64> %2 = sext <16 x i32> %op2 to <16 x i64> %mul = mul <16 x i64> %1, %2 %shr = lshr <16 x i64> %mul, %res = trunc <16 x i64> %shr to <16 x i32> - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @smulh_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @smulh_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: smulh_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -456,18 +456,18 @@ define void @smulh_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: smulh z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %1 = sext <32 x i32> %op1 to <32 x i64> %2 = sext <32 x i32> %op2 to <32 x i64> %mul = mul <32 x i64> %1, %2 %shr = lshr <32 x i64> %mul, %res = trunc <32 x i64> %shr to <32 x i32> - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @smulh_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @smulh_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: smulh_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -476,14 +476,14 @@ define void @smulh_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 ; CHECK-NEXT: smulh z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %1 = sext <64 x i32> %op1 to <64 x i64> %2 = sext <64 x i32> %op2 to <64 x i64> %mul = mul <64 x i64> %1, %2 %shr = lshr <64 x i64> %mul, %res = trunc <64 x i64> %shr to <64 x i32> - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -525,7 +525,7 @@ define <2 x i64> @smulh_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) ret <2 x i64> %res } -define void @smulh_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @smulh_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: smulh_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -534,18 +534,18 @@ define void @smulh_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: smulh z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %1 = sext <4 x i64> %op1 to <4 x i128> %2 = sext <4 x i64> %op2 to <4 x i128> %mul = mul <4 x i128> %1, %2 %shr = lshr <4 x i128> %mul, %res = trunc <4 x i128> %shr to <4 x i64> - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @smulh_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @smulh_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: smulh_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -609,18 +609,18 @@ define void @smulh_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: smulh z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %1 = sext <8 x i64> %op1 to <8 x i128> %2 = sext <8 x i64> %op2 to <8 x i128> %mul = mul <8 x i128> %1, %2 %shr = lshr <8 x i128> %mul, %res = trunc <8 x i128> %shr to <8 x i64> - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @smulh_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @smulh_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: smulh_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -629,18 +629,18 @@ define void @smulh_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: smulh z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %1 = sext <16 x i64> %op1 to <16 x i128> %2 = sext <16 x i64> %op2 to <16 x i128> %mul = mul <16 x i128> %1, %2 %shr = lshr <16 x i128> %mul, %res = trunc <16 x i128> %shr to <16 x i64> - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @smulh_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @smulh_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: smulh_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -649,14 +649,14 @@ define void @smulh_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 ; CHECK-NEXT: smulh z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %1 = sext <32 x i64> %op1 to <32 x i128> %2 = sext <32 x i64> %op2 to <32 x i128> %mul = mul <32 x i128> %1, %2 %shr = lshr <32 x i128> %mul, %res = trunc <32 x i128> %shr to <32 x i64> - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } @@ -713,7 +713,7 @@ define <16 x i8> @umulh_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) ret <16 x i8> %res } -define void @umulh_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @umulh_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: umulh_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -722,18 +722,18 @@ define void @umulh_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: umulh z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %1 = zext <32 x i8> %op1 to <32 x i16> %2 = zext <32 x i8> %op2 to <32 x i16> %mul = mul <32 x i16> %1, %2 %shr = lshr <32 x i16> %mul, %res = trunc <32 x i16> %shr to <32 x i8> - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @umulh_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @umulh_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: umulh_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -784,18 +784,18 @@ define void @umulh_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: umulh z0.b, p0/m, z0.b, z1.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %1 = zext <64 x i8> %op1 to <64 x i16> %2 = zext <64 x i8> %op2 to <64 x i16> %mul = mul <64 x i16> %1, %2 %shr = lshr <64 x i16> %mul, %res = trunc <64 x i16> %shr to <64 x i8> - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @umulh_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @umulh_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: umulh_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -804,8 +804,8 @@ define void @umulh_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: umulh z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %insert = insertelement <128 x i16> undef, i16 8, i64 0 %splat = shufflevector <128 x i16> %insert, <128 x i16> undef, <128 x i32> zeroinitializer %1 = zext <128 x i8> %op1 to <128 x i16> @@ -813,11 +813,11 @@ define void @umulh_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { %mul = mul <128 x i16> %1, %2 %shr = lshr <128 x i16> %mul, %res = trunc <128 x i16> %shr to <128 x i8> - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @umulh_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @umulh_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: umulh_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -826,14 +826,14 @@ define void @umulh_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 ; CHECK-NEXT: umulh z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %1 = zext <256 x i8> %op1 to <256 x i16> %2 = zext <256 x i8> %op2 to <256 x i16> %mul = mul <256 x i16> %1, %2 %shr = lshr <256 x i16> %mul, %res = trunc <256 x i16> %shr to <256 x i8> - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -877,7 +877,7 @@ define <8 x i16> @umulh_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) ret <8 x i16> %res } -define void @umulh_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @umulh_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: umulh_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -886,18 +886,18 @@ define void @umulh_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: umulh z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %1 = zext <16 x i16> %op1 to <16 x i32> %2 = zext <16 x i16> %op2 to <16 x i32> %mul = mul <16 x i32> %1, %2 %shr = lshr <16 x i32> %mul, %res = trunc <16 x i32> %shr to <16 x i16> - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @umulh_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @umulh_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: umulh_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -939,18 +939,18 @@ define void @umulh_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: umulh z0.h, p0/m, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %1 = zext <32 x i16> %op1 to <32 x i32> %2 = zext <32 x i16> %op2 to <32 x i32> %mul = mul <32 x i32> %1, %2 %shr = lshr <32 x i32> %mul, %res = trunc <32 x i32> %shr to <32 x i16> - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @umulh_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @umulh_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: umulh_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -959,18 +959,18 @@ define void @umulh_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: umulh z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %1 = zext <64 x i16> %op1 to <64 x i32> %2 = zext <64 x i16> %op2 to <64 x i32> %mul = mul <64 x i32> %1, %2 %shr = lshr <64 x i32> %mul, %res = trunc <64 x i32> %shr to <64 x i16> - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @umulh_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @umulh_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: umulh_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -979,14 +979,14 @@ define void @umulh_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) ; CHECK-NEXT: umulh z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %1 = zext <128 x i16> %op1 to <128 x i32> %2 = zext <128 x i16> %op2 to <128 x i32> %mul = mul <128 x i32> %1, %2 %shr = lshr <128 x i32> %mul, %res = trunc <128 x i32> %shr to <128 x i16> - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -1024,7 +1024,7 @@ define <4 x i32> @umulh_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) ret <4 x i32> %res } -define void @umulh_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @umulh_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: umulh_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1033,8 +1033,8 @@ define void @umulh_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: umulh z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %insert = insertelement <8 x i64> undef, i64 32, i64 0 %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer %1 = zext <8 x i32> %op1 to <8 x i64> @@ -1042,11 +1042,11 @@ define void @umulh_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { %mul = mul <8 x i64> %1, %2 %shr = lshr <8 x i64> %mul, %res = trunc <8 x i64> %shr to <8 x i32> - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @umulh_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @umulh_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: umulh_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1088,18 +1088,18 @@ define void @umulh_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: umulh z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %1 = zext <16 x i32> %op1 to <16 x i64> %2 = zext <16 x i32> %op2 to <16 x i64> %mul = mul <16 x i64> %1, %2 %shr = lshr <16 x i64> %mul, %res = trunc <16 x i64> %shr to <16 x i32> - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @umulh_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @umulh_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: umulh_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1108,18 +1108,18 @@ define void @umulh_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: umulh z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %1 = zext <32 x i32> %op1 to <32 x i64> %2 = zext <32 x i32> %op2 to <32 x i64> %mul = mul <32 x i64> %1, %2 %shr = lshr <32 x i64> %mul, %res = trunc <32 x i64> %shr to <32 x i32> - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @umulh_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @umulh_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: umulh_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1128,14 +1128,14 @@ define void @umulh_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 ; CHECK-NEXT: umulh z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %1 = zext <64 x i32> %op1 to <64 x i64> %2 = zext <64 x i32> %op2 to <64 x i64> %mul = mul <64 x i64> %1, %2 %shr = lshr <64 x i64> %mul, %res = trunc <64 x i64> %shr to <64 x i32> - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -1175,7 +1175,7 @@ define <2 x i64> @umulh_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) ret <2 x i64> %res } -define void @umulh_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @umulh_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: umulh_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1184,18 +1184,18 @@ define void @umulh_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: umulh z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %1 = zext <4 x i64> %op1 to <4 x i128> %2 = zext <4 x i64> %op2 to <4 x i128> %mul = mul <4 x i128> %1, %2 %shr = lshr <4 x i128> %mul, %res = trunc <4 x i128> %shr to <4 x i64> - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @umulh_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @umulh_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: umulh_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1259,18 +1259,18 @@ define void @umulh_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: umulh z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %1 = zext <8 x i64> %op1 to <8 x i128> %2 = zext <8 x i64> %op2 to <8 x i128> %mul = mul <8 x i128> %1, %2 %shr = lshr <8 x i128> %mul, %res = trunc <8 x i128> %shr to <8 x i64> - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @umulh_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @umulh_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: umulh_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1279,18 +1279,18 @@ define void @umulh_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: umulh z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %1 = zext <16 x i64> %op1 to <16 x i128> %2 = zext <16 x i64> %op2 to <16 x i128> %mul = mul <16 x i128> %1, %2 %shr = lshr <16 x i128> %mul, %res = trunc <16 x i128> %shr to <16 x i64> - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @umulh_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @umulh_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: umulh_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1299,14 +1299,14 @@ define void @umulh_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 ; CHECK-NEXT: umulh z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %1 = zext <32 x i64> %op1 to <32 x i128> %2 = zext <32 x i64> %op2 to <32 x i128> %mul = mul <32 x i128> %1, %2 %shr = lshr <32 x i128> %mul, %res = trunc <32 x i128> %shr to <32 x i64> - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } attributes #0 = { "target-features"="+sve" } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll index 1e6684b..942faba 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll @@ -31,7 +31,7 @@ define i8 @uaddv_v16i8(<16 x i8> %a) vscale_range(2,0) #0 { ret i8 %res } -define i8 @uaddv_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { +define i8 @uaddv_v32i8(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: uaddv_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -40,12 +40,12 @@ define i8 @uaddv_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret - %op = load <32 x i8>, <32 x i8>* %a + %op = load <32 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %op) ret i8 %res } -define i8 @uaddv_v64i8(<64 x i8>* %a) #0 { +define i8 @uaddv_v64i8(ptr %a) #0 { ; VBITS_GE_256-LABEL: uaddv_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -66,12 +66,12 @@ define i8 @uaddv_v64i8(<64 x i8>* %a) #0 { ; VBITS_GE_512-NEXT: fmov x0, d0 ; VBITS_GE_512-NEXT: // kill: def $w0 killed $w0 killed $x0 ; VBITS_GE_512-NEXT: ret - %op = load <64 x i8>, <64 x i8>* %a + %op = load <64 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> %op) ret i8 %res } -define i8 @uaddv_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { +define i8 @uaddv_v128i8(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: uaddv_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -80,12 +80,12 @@ define i8 @uaddv_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret - %op = load <128 x i8>, <128 x i8>* %a + %op = load <128 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> %op) ret i8 %res } -define i8 @uaddv_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { +define i8 @uaddv_v256i8(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: uaddv_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -94,7 +94,7 @@ define i8 @uaddv_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret - %op = load <256 x i8>, <256 x i8>* %a + %op = load <256 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.add.v256i8(<256 x i8> %op) ret i8 %res } @@ -121,7 +121,7 @@ define i16 @uaddv_v8i16(<8 x i16> %a) vscale_range(2,0) #0 { ret i16 %res } -define i16 @uaddv_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { +define i16 @uaddv_v16i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: uaddv_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -130,12 +130,12 @@ define i16 @uaddv_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret - %op = load <16 x i16>, <16 x i16>* %a + %op = load <16 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %op) ret i16 %res } -define i16 @uaddv_v32i16(<32 x i16>* %a) #0 { +define i16 @uaddv_v32i16(ptr %a) #0 { ; VBITS_GE_256-LABEL: uaddv_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -156,12 +156,12 @@ define i16 @uaddv_v32i16(<32 x i16>* %a) #0 { ; VBITS_GE_512-NEXT: fmov x0, d0 ; VBITS_GE_512-NEXT: // kill: def $w0 killed $w0 killed $x0 ; VBITS_GE_512-NEXT: ret - %op = load <32 x i16>, <32 x i16>* %a + %op = load <32 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> %op) ret i16 %res } -define i16 @uaddv_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { +define i16 @uaddv_v64i16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: uaddv_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -170,12 +170,12 @@ define i16 @uaddv_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret - %op = load <64 x i16>, <64 x i16>* %a + %op = load <64 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> %op) ret i16 %res } -define i16 @uaddv_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { +define i16 @uaddv_v128i16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: uaddv_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -184,7 +184,7 @@ define i16 @uaddv_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret - %op = load <128 x i16>, <128 x i16>* %a + %op = load <128 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.add.v128i16(<128 x i16> %op) ret i16 %res } @@ -211,7 +211,7 @@ define i32 @uaddv_v4i32(<4 x i32> %a) vscale_range(2,0) #0 { ret i32 %res } -define i32 @uaddv_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { +define i32 @uaddv_v8i32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: uaddv_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -220,12 +220,12 @@ define i32 @uaddv_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret - %op = load <8 x i32>, <8 x i32>* %a + %op = load <8 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %op) ret i32 %res } -define i32 @uaddv_v16i32(<16 x i32>* %a) #0 { +define i32 @uaddv_v16i32(ptr %a) #0 { ; VBITS_GE_256-LABEL: uaddv_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -246,12 +246,12 @@ define i32 @uaddv_v16i32(<16 x i32>* %a) #0 { ; VBITS_GE_512-NEXT: fmov x0, d0 ; VBITS_GE_512-NEXT: // kill: def $w0 killed $w0 killed $x0 ; VBITS_GE_512-NEXT: ret - %op = load <16 x i32>, <16 x i32>* %a + %op = load <16 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %op) ret i32 %res } -define i32 @uaddv_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { +define i32 @uaddv_v32i32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: uaddv_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -260,12 +260,12 @@ define i32 @uaddv_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret - %op = load <32 x i32>, <32 x i32>* %a + %op = load <32 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %op) ret i32 %res } -define i32 @uaddv_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { +define i32 @uaddv_v64i32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: uaddv_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -274,7 +274,7 @@ define i32 @uaddv_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret - %op = load <64 x i32>, <64 x i32>* %a + %op = load <64 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.add.v64i32(<64 x i32> %op) ret i32 %res } @@ -301,7 +301,7 @@ define i64 @uaddv_v2i64(<2 x i64> %a) vscale_range(2,0) #0 { ret i64 %res } -define i64 @uaddv_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { +define i64 @uaddv_v4i64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: uaddv_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -309,12 +309,12 @@ define i64 @uaddv_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: uaddv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <4 x i64>, <4 x i64>* %a + %op = load <4 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %op) ret i64 %res } -define i64 @uaddv_v8i64(<8 x i64>* %a) #0 { +define i64 @uaddv_v8i64(ptr %a) #0 { ; VBITS_GE_256-LABEL: uaddv_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -333,12 +333,12 @@ define i64 @uaddv_v8i64(<8 x i64>* %a) #0 { ; VBITS_GE_512-NEXT: uaddv d0, p0, z0.d ; VBITS_GE_512-NEXT: fmov x0, d0 ; VBITS_GE_512-NEXT: ret - %op = load <8 x i64>, <8 x i64>* %a + %op = load <8 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %op) ret i64 %res } -define i64 @uaddv_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { +define i64 @uaddv_v16i64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: uaddv_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -346,12 +346,12 @@ define i64 @uaddv_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: uaddv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <16 x i64>, <16 x i64>* %a + %op = load <16 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %op) ret i64 %res } -define i64 @uaddv_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { +define i64 @uaddv_v32i64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: uaddv_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -359,7 +359,7 @@ define i64 @uaddv_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: uaddv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <32 x i64>, <32 x i64>* %a + %op = load <32 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.add.v32i64(<32 x i64> %op) ret i64 %res } @@ -390,7 +390,7 @@ define i8 @smaxv_v16i8(<16 x i8> %a) vscale_range(2,0) #0 { ret i8 %res } -define i8 @smaxv_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { +define i8 @smaxv_v32i8(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: smaxv_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -398,12 +398,12 @@ define i8 @smaxv_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: smaxv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <32 x i8>, <32 x i8>* %a + %op = load <32 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> %op) ret i8 %res } -define i8 @smaxv_v64i8(<64 x i8>* %a) #0 { +define i8 @smaxv_v64i8(ptr %a) #0 { ; VBITS_GE_256-LABEL: smaxv_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -422,12 +422,12 @@ define i8 @smaxv_v64i8(<64 x i8>* %a) #0 { ; VBITS_GE_512-NEXT: smaxv b0, p0, z0.b ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <64 x i8>, <64 x i8>* %a + %op = load <64 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> %op) ret i8 %res } -define i8 @smaxv_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { +define i8 @smaxv_v128i8(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: smaxv_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -435,12 +435,12 @@ define i8 @smaxv_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: smaxv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <128 x i8>, <128 x i8>* %a + %op = load <128 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> %op) ret i8 %res } -define i8 @smaxv_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { +define i8 @smaxv_v256i8(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: smaxv_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -448,7 +448,7 @@ define i8 @smaxv_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: smaxv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <256 x i8>, <256 x i8>* %a + %op = load <256 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.smax.v256i8(<256 x i8> %op) ret i8 %res } @@ -475,7 +475,7 @@ define i16 @smaxv_v8i16(<8 x i16> %a) vscale_range(2,0) #0 { ret i16 %res } -define i16 @smaxv_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { +define i16 @smaxv_v16i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: smaxv_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -483,12 +483,12 @@ define i16 @smaxv_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: smaxv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <16 x i16>, <16 x i16>* %a + %op = load <16 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> %op) ret i16 %res } -define i16 @smaxv_v32i16(<32 x i16>* %a) #0 { +define i16 @smaxv_v32i16(ptr %a) #0 { ; VBITS_GE_256-LABEL: smaxv_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -507,12 +507,12 @@ define i16 @smaxv_v32i16(<32 x i16>* %a) #0 { ; VBITS_GE_512-NEXT: smaxv h0, p0, z0.h ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <32 x i16>, <32 x i16>* %a + %op = load <32 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> %op) ret i16 %res } -define i16 @smaxv_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { +define i16 @smaxv_v64i16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: smaxv_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -520,12 +520,12 @@ define i16 @smaxv_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: smaxv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <64 x i16>, <64 x i16>* %a + %op = load <64 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> %op) ret i16 %res } -define i16 @smaxv_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { +define i16 @smaxv_v128i16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: smaxv_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -533,7 +533,7 @@ define i16 @smaxv_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: smaxv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <128 x i16>, <128 x i16>* %a + %op = load <128 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.smax.v128i16(<128 x i16> %op) ret i16 %res } @@ -560,7 +560,7 @@ define i32 @smaxv_v4i32(<4 x i32> %a) vscale_range(2,0) #0 { ret i32 %res } -define i32 @smaxv_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { +define i32 @smaxv_v8i32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: smaxv_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -568,12 +568,12 @@ define i32 @smaxv_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: smaxv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <8 x i32>, <8 x i32>* %a + %op = load <8 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> %op) ret i32 %res } -define i32 @smaxv_v16i32(<16 x i32>* %a) #0 { +define i32 @smaxv_v16i32(ptr %a) #0 { ; VBITS_GE_256-LABEL: smaxv_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -592,12 +592,12 @@ define i32 @smaxv_v16i32(<16 x i32>* %a) #0 { ; VBITS_GE_512-NEXT: smaxv s0, p0, z0.s ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <16 x i32>, <16 x i32>* %a + %op = load <16 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> %op) ret i32 %res } -define i32 @smaxv_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { +define i32 @smaxv_v32i32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: smaxv_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -605,12 +605,12 @@ define i32 @smaxv_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: smaxv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <32 x i32>, <32 x i32>* %a + %op = load <32 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> %op) ret i32 %res } -define i32 @smaxv_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { +define i32 @smaxv_v64i32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: smaxv_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -618,7 +618,7 @@ define i32 @smaxv_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: smaxv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <64 x i32>, <64 x i32>* %a + %op = load <64 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.smax.v64i32(<64 x i32> %op) ret i32 %res } @@ -647,7 +647,7 @@ define i64 @smaxv_v2i64(<2 x i64> %a) vscale_range(2,0) #0 { ret i64 %res } -define i64 @smaxv_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { +define i64 @smaxv_v4i64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: smaxv_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -655,12 +655,12 @@ define i64 @smaxv_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: smaxv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <4 x i64>, <4 x i64>* %a + %op = load <4 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %op) ret i64 %res } -define i64 @smaxv_v8i64(<8 x i64>* %a) #0 { +define i64 @smaxv_v8i64(ptr %a) #0 { ; VBITS_GE_256-LABEL: smaxv_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -679,12 +679,12 @@ define i64 @smaxv_v8i64(<8 x i64>* %a) #0 { ; VBITS_GE_512-NEXT: smaxv d0, p0, z0.d ; VBITS_GE_512-NEXT: fmov x0, d0 ; VBITS_GE_512-NEXT: ret - %op = load <8 x i64>, <8 x i64>* %a + %op = load <8 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> %op) ret i64 %res } -define i64 @smaxv_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { +define i64 @smaxv_v16i64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: smaxv_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -692,12 +692,12 @@ define i64 @smaxv_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: smaxv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <16 x i64>, <16 x i64>* %a + %op = load <16 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> %op) ret i64 %res } -define i64 @smaxv_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { +define i64 @smaxv_v32i64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: smaxv_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -705,7 +705,7 @@ define i64 @smaxv_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: smaxv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <32 x i64>, <32 x i64>* %a + %op = load <32 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.smax.v32i64(<32 x i64> %op) ret i64 %res } @@ -736,7 +736,7 @@ define i8 @sminv_v16i8(<16 x i8> %a) vscale_range(2,0) #0 { ret i8 %res } -define i8 @sminv_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { +define i8 @sminv_v32i8(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: sminv_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -744,12 +744,12 @@ define i8 @sminv_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: sminv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <32 x i8>, <32 x i8>* %a + %op = load <32 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> %op) ret i8 %res } -define i8 @sminv_v64i8(<64 x i8>* %a) #0 { +define i8 @sminv_v64i8(ptr %a) #0 { ; VBITS_GE_256-LABEL: sminv_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -768,12 +768,12 @@ define i8 @sminv_v64i8(<64 x i8>* %a) #0 { ; VBITS_GE_512-NEXT: sminv b0, p0, z0.b ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <64 x i8>, <64 x i8>* %a + %op = load <64 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> %op) ret i8 %res } -define i8 @sminv_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { +define i8 @sminv_v128i8(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: sminv_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -781,12 +781,12 @@ define i8 @sminv_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: sminv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <128 x i8>, <128 x i8>* %a + %op = load <128 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> %op) ret i8 %res } -define i8 @sminv_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { +define i8 @sminv_v256i8(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: sminv_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -794,7 +794,7 @@ define i8 @sminv_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: sminv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <256 x i8>, <256 x i8>* %a + %op = load <256 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.smin.v256i8(<256 x i8> %op) ret i8 %res } @@ -821,7 +821,7 @@ define i16 @sminv_v8i16(<8 x i16> %a) vscale_range(2,0) #0 { ret i16 %res } -define i16 @sminv_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { +define i16 @sminv_v16i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: sminv_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -829,12 +829,12 @@ define i16 @sminv_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: sminv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <16 x i16>, <16 x i16>* %a + %op = load <16 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %op) ret i16 %res } -define i16 @sminv_v32i16(<32 x i16>* %a) #0 { +define i16 @sminv_v32i16(ptr %a) #0 { ; VBITS_GE_256-LABEL: sminv_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -853,12 +853,12 @@ define i16 @sminv_v32i16(<32 x i16>* %a) #0 { ; VBITS_GE_512-NEXT: sminv h0, p0, z0.h ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <32 x i16>, <32 x i16>* %a + %op = load <32 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> %op) ret i16 %res } -define i16 @sminv_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { +define i16 @sminv_v64i16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: sminv_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -866,12 +866,12 @@ define i16 @sminv_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: sminv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <64 x i16>, <64 x i16>* %a + %op = load <64 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> %op) ret i16 %res } -define i16 @sminv_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { +define i16 @sminv_v128i16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: sminv_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -879,7 +879,7 @@ define i16 @sminv_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: sminv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <128 x i16>, <128 x i16>* %a + %op = load <128 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.smin.v128i16(<128 x i16> %op) ret i16 %res } @@ -906,7 +906,7 @@ define i32 @sminv_v4i32(<4 x i32> %a) vscale_range(2,0) #0 { ret i32 %res } -define i32 @sminv_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { +define i32 @sminv_v8i32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: sminv_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -914,12 +914,12 @@ define i32 @sminv_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: sminv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <8 x i32>, <8 x i32>* %a + %op = load <8 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> %op) ret i32 %res } -define i32 @sminv_v16i32(<16 x i32>* %a) #0 { +define i32 @sminv_v16i32(ptr %a) #0 { ; VBITS_GE_256-LABEL: sminv_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -938,12 +938,12 @@ define i32 @sminv_v16i32(<16 x i32>* %a) #0 { ; VBITS_GE_512-NEXT: sminv s0, p0, z0.s ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <16 x i32>, <16 x i32>* %a + %op = load <16 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> %op) ret i32 %res } -define i32 @sminv_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { +define i32 @sminv_v32i32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: sminv_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -951,12 +951,12 @@ define i32 @sminv_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: sminv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <32 x i32>, <32 x i32>* %a + %op = load <32 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> %op) ret i32 %res } -define i32 @sminv_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { +define i32 @sminv_v64i32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: sminv_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -964,7 +964,7 @@ define i32 @sminv_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: sminv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <64 x i32>, <64 x i32>* %a + %op = load <64 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.smin.v64i32(<64 x i32> %op) ret i32 %res } @@ -993,7 +993,7 @@ define i64 @sminv_v2i64(<2 x i64> %a) vscale_range(2,0) #0 { ret i64 %res } -define i64 @sminv_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { +define i64 @sminv_v4i64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: sminv_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1001,12 +1001,12 @@ define i64 @sminv_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: sminv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <4 x i64>, <4 x i64>* %a + %op = load <4 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %op) ret i64 %res } -define i64 @sminv_v8i64(<8 x i64>* %a) #0 { +define i64 @sminv_v8i64(ptr %a) #0 { ; VBITS_GE_256-LABEL: sminv_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1025,12 +1025,12 @@ define i64 @sminv_v8i64(<8 x i64>* %a) #0 { ; VBITS_GE_512-NEXT: sminv d0, p0, z0.d ; VBITS_GE_512-NEXT: fmov x0, d0 ; VBITS_GE_512-NEXT: ret - %op = load <8 x i64>, <8 x i64>* %a + %op = load <8 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> %op) ret i64 %res } -define i64 @sminv_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { +define i64 @sminv_v16i64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: sminv_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1038,12 +1038,12 @@ define i64 @sminv_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: sminv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <16 x i64>, <16 x i64>* %a + %op = load <16 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> %op) ret i64 %res } -define i64 @sminv_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { +define i64 @sminv_v32i64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: sminv_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1051,7 +1051,7 @@ define i64 @sminv_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: sminv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <32 x i64>, <32 x i64>* %a + %op = load <32 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.smin.v32i64(<32 x i64> %op) ret i64 %res } @@ -1082,7 +1082,7 @@ define i8 @umaxv_v16i8(<16 x i8> %a) vscale_range(2,0) #0 { ret i8 %res } -define i8 @umaxv_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { +define i8 @umaxv_v32i8(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: umaxv_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -1090,12 +1090,12 @@ define i8 @umaxv_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: umaxv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <32 x i8>, <32 x i8>* %a + %op = load <32 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> %op) ret i8 %res } -define i8 @umaxv_v64i8(<64 x i8>* %a) #0 { +define i8 @umaxv_v64i8(ptr %a) #0 { ; VBITS_GE_256-LABEL: umaxv_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -1114,12 +1114,12 @@ define i8 @umaxv_v64i8(<64 x i8>* %a) #0 { ; VBITS_GE_512-NEXT: umaxv b0, p0, z0.b ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <64 x i8>, <64 x i8>* %a + %op = load <64 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> %op) ret i8 %res } -define i8 @umaxv_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { +define i8 @umaxv_v128i8(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: umaxv_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -1127,12 +1127,12 @@ define i8 @umaxv_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: umaxv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <128 x i8>, <128 x i8>* %a + %op = load <128 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> %op) ret i8 %res } -define i8 @umaxv_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { +define i8 @umaxv_v256i8(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: umaxv_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -1140,7 +1140,7 @@ define i8 @umaxv_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: umaxv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <256 x i8>, <256 x i8>* %a + %op = load <256 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.umax.v256i8(<256 x i8> %op) ret i8 %res } @@ -1167,7 +1167,7 @@ define i16 @umaxv_v8i16(<8 x i16> %a) vscale_range(2,0) #0 { ret i16 %res } -define i16 @umaxv_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { +define i16 @umaxv_v16i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: umaxv_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -1175,12 +1175,12 @@ define i16 @umaxv_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: umaxv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <16 x i16>, <16 x i16>* %a + %op = load <16 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> %op) ret i16 %res } -define i16 @umaxv_v32i16(<32 x i16>* %a) #0 { +define i16 @umaxv_v32i16(ptr %a) #0 { ; VBITS_GE_256-LABEL: umaxv_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -1199,12 +1199,12 @@ define i16 @umaxv_v32i16(<32 x i16>* %a) #0 { ; VBITS_GE_512-NEXT: umaxv h0, p0, z0.h ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <32 x i16>, <32 x i16>* %a + %op = load <32 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> %op) ret i16 %res } -define i16 @umaxv_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { +define i16 @umaxv_v64i16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: umaxv_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -1212,12 +1212,12 @@ define i16 @umaxv_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: umaxv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <64 x i16>, <64 x i16>* %a + %op = load <64 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> %op) ret i16 %res } -define i16 @umaxv_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { +define i16 @umaxv_v128i16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: umaxv_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1225,7 +1225,7 @@ define i16 @umaxv_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: umaxv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <128 x i16>, <128 x i16>* %a + %op = load <128 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.umax.v128i16(<128 x i16> %op) ret i16 %res } @@ -1252,7 +1252,7 @@ define i32 @umaxv_v4i32(<4 x i32> %a) vscale_range(2,0) #0 { ret i32 %res } -define i32 @umaxv_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { +define i32 @umaxv_v8i32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: umaxv_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1260,12 +1260,12 @@ define i32 @umaxv_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: umaxv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <8 x i32>, <8 x i32>* %a + %op = load <8 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %op) ret i32 %res } -define i32 @umaxv_v16i32(<16 x i32>* %a) #0 { +define i32 @umaxv_v16i32(ptr %a) #0 { ; VBITS_GE_256-LABEL: umaxv_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1284,12 +1284,12 @@ define i32 @umaxv_v16i32(<16 x i32>* %a) #0 { ; VBITS_GE_512-NEXT: umaxv s0, p0, z0.s ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <16 x i32>, <16 x i32>* %a + %op = load <16 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %op) ret i32 %res } -define i32 @umaxv_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { +define i32 @umaxv_v32i32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: umaxv_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1297,12 +1297,12 @@ define i32 @umaxv_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: umaxv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <32 x i32>, <32 x i32>* %a + %op = load <32 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> %op) ret i32 %res } -define i32 @umaxv_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { +define i32 @umaxv_v64i32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: umaxv_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1310,7 +1310,7 @@ define i32 @umaxv_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: umaxv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <64 x i32>, <64 x i32>* %a + %op = load <64 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.umax.v64i32(<64 x i32> %op) ret i32 %res } @@ -1339,7 +1339,7 @@ define i64 @umaxv_v2i64(<2 x i64> %a) vscale_range(2,0) #0 { ret i64 %res } -define i64 @umaxv_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { +define i64 @umaxv_v4i64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: umaxv_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1347,12 +1347,12 @@ define i64 @umaxv_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: umaxv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <4 x i64>, <4 x i64>* %a + %op = load <4 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %op) ret i64 %res } -define i64 @umaxv_v8i64(<8 x i64>* %a) #0 { +define i64 @umaxv_v8i64(ptr %a) #0 { ; VBITS_GE_256-LABEL: umaxv_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1371,12 +1371,12 @@ define i64 @umaxv_v8i64(<8 x i64>* %a) #0 { ; VBITS_GE_512-NEXT: umaxv d0, p0, z0.d ; VBITS_GE_512-NEXT: fmov x0, d0 ; VBITS_GE_512-NEXT: ret - %op = load <8 x i64>, <8 x i64>* %a + %op = load <8 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> %op) ret i64 %res } -define i64 @umaxv_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { +define i64 @umaxv_v16i64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: umaxv_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1384,12 +1384,12 @@ define i64 @umaxv_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: umaxv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <16 x i64>, <16 x i64>* %a + %op = load <16 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> %op) ret i64 %res } -define i64 @umaxv_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { +define i64 @umaxv_v32i64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: umaxv_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1397,7 +1397,7 @@ define i64 @umaxv_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: umaxv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <32 x i64>, <32 x i64>* %a + %op = load <32 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.umax.v32i64(<32 x i64> %op) ret i64 %res } @@ -1428,7 +1428,7 @@ define i8 @uminv_v16i8(<16 x i8> %a) vscale_range(2,0) #0 { ret i8 %res } -define i8 @uminv_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { +define i8 @uminv_v32i8(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: uminv_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -1436,12 +1436,12 @@ define i8 @uminv_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: uminv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <32 x i8>, <32 x i8>* %a + %op = load <32 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> %op) ret i8 %res } -define i8 @uminv_v64i8(<64 x i8>* %a) #0 { +define i8 @uminv_v64i8(ptr %a) #0 { ; VBITS_GE_256-LABEL: uminv_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -1460,12 +1460,12 @@ define i8 @uminv_v64i8(<64 x i8>* %a) #0 { ; VBITS_GE_512-NEXT: uminv b0, p0, z0.b ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <64 x i8>, <64 x i8>* %a + %op = load <64 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> %op) ret i8 %res } -define i8 @uminv_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { +define i8 @uminv_v128i8(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: uminv_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -1473,12 +1473,12 @@ define i8 @uminv_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: uminv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <128 x i8>, <128 x i8>* %a + %op = load <128 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> %op) ret i8 %res } -define i8 @uminv_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { +define i8 @uminv_v256i8(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: uminv_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -1486,7 +1486,7 @@ define i8 @uminv_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: uminv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <256 x i8>, <256 x i8>* %a + %op = load <256 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.umin.v256i8(<256 x i8> %op) ret i8 %res } @@ -1513,7 +1513,7 @@ define i16 @uminv_v8i16(<8 x i16> %a) vscale_range(2,0) #0 { ret i16 %res } -define i16 @uminv_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { +define i16 @uminv_v16i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: uminv_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -1521,12 +1521,12 @@ define i16 @uminv_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: uminv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <16 x i16>, <16 x i16>* %a + %op = load <16 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %op) ret i16 %res } -define i16 @uminv_v32i16(<32 x i16>* %a) #0 { +define i16 @uminv_v32i16(ptr %a) #0 { ; VBITS_GE_256-LABEL: uminv_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -1545,12 +1545,12 @@ define i16 @uminv_v32i16(<32 x i16>* %a) #0 { ; VBITS_GE_512-NEXT: uminv h0, p0, z0.h ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <32 x i16>, <32 x i16>* %a + %op = load <32 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> %op) ret i16 %res } -define i16 @uminv_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { +define i16 @uminv_v64i16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: uminv_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -1558,12 +1558,12 @@ define i16 @uminv_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: uminv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <64 x i16>, <64 x i16>* %a + %op = load <64 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> %op) ret i16 %res } -define i16 @uminv_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { +define i16 @uminv_v128i16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: uminv_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1571,7 +1571,7 @@ define i16 @uminv_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: uminv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <128 x i16>, <128 x i16>* %a + %op = load <128 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.umin.v128i16(<128 x i16> %op) ret i16 %res } @@ -1598,7 +1598,7 @@ define i32 @uminv_v4i32(<4 x i32> %a) vscale_range(2,0) #0 { ret i32 %res } -define i32 @uminv_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { +define i32 @uminv_v8i32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: uminv_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1606,12 +1606,12 @@ define i32 @uminv_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: uminv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <8 x i32>, <8 x i32>* %a + %op = load <8 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> %op) ret i32 %res } -define i32 @uminv_v16i32(<16 x i32>* %a) #0 { +define i32 @uminv_v16i32(ptr %a) #0 { ; VBITS_GE_256-LABEL: uminv_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1630,12 +1630,12 @@ define i32 @uminv_v16i32(<16 x i32>* %a) #0 { ; VBITS_GE_512-NEXT: uminv s0, p0, z0.s ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <16 x i32>, <16 x i32>* %a + %op = load <16 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> %op) ret i32 %res } -define i32 @uminv_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { +define i32 @uminv_v32i32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: uminv_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1643,12 +1643,12 @@ define i32 @uminv_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: uminv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <32 x i32>, <32 x i32>* %a + %op = load <32 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> %op) ret i32 %res } -define i32 @uminv_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { +define i32 @uminv_v64i32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: uminv_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1656,7 +1656,7 @@ define i32 @uminv_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: uminv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <64 x i32>, <64 x i32>* %a + %op = load <64 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.umin.v64i32(<64 x i32> %op) ret i32 %res } @@ -1685,7 +1685,7 @@ define i64 @uminv_v2i64(<2 x i64> %a) vscale_range(2,0) #0 { ret i64 %res } -define i64 @uminv_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { +define i64 @uminv_v4i64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: uminv_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1693,12 +1693,12 @@ define i64 @uminv_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: uminv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <4 x i64>, <4 x i64>* %a + %op = load <4 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %op) ret i64 %res } -define i64 @uminv_v8i64(<8 x i64>* %a) #0 { +define i64 @uminv_v8i64(ptr %a) #0 { ; VBITS_GE_256-LABEL: uminv_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1717,12 +1717,12 @@ define i64 @uminv_v8i64(<8 x i64>* %a) #0 { ; VBITS_GE_512-NEXT: uminv d0, p0, z0.d ; VBITS_GE_512-NEXT: fmov x0, d0 ; VBITS_GE_512-NEXT: ret - %op = load <8 x i64>, <8 x i64>* %a + %op = load <8 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> %op) ret i64 %res } -define i64 @uminv_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { +define i64 @uminv_v16i64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: uminv_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1730,12 +1730,12 @@ define i64 @uminv_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: uminv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <16 x i64>, <16 x i64>* %a + %op = load <16 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> %op) ret i64 %res } -define i64 @uminv_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { +define i64 @uminv_v32i64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: uminv_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1743,7 +1743,7 @@ define i64 @uminv_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: uminv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <32 x i64>, <32 x i64>* %a + %op = load <32 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.umin.v32i64(<32 x i64> %op) ret i64 %res } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll index e0dea9c..9312711 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll @@ -161,7 +161,7 @@ define <16 x i8> @srem_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 { ret <16 x i8> %res } -define void @srem_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(8,0) #0 { +define void @srem_v32i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: srem_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -178,14 +178,14 @@ define void @srem_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %res = srem <32 x i8> %op1, %op2 - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @srem_v64i8(<64 x i8>* %a, <64 x i8>* %b) vscale_range(16,0) #0 { +define void @srem_v64i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: srem_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -202,14 +202,14 @@ define void @srem_v64i8(<64 x i8>* %a, <64 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = srem <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @srem_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(16,0) #0 { +define void @srem_v128i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: srem_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -229,14 +229,14 @@ define void @srem_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %res = srem <128 x i8> %op1, %op2 - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @srem_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @srem_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: srem_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -265,10 +265,10 @@ define void @srem_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %res = srem <256 x i8> %op1, %op2 - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -367,7 +367,7 @@ define <8 x i16> @srem_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 { ret <8 x i16> %res } -define void @srem_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { +define void @srem_v16i16(ptr %a, ptr %b) #0 { ; VBITS_GE_128-LABEL: srem_v16i16: ; VBITS_GE_128: // %bb.0: ; VBITS_GE_128-NEXT: ldp q2, q0, [x0] @@ -423,14 +423,14 @@ define void @srem_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: mls z0.h, p0/m, z2.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %res = srem <16 x i16> %op1, %op2 - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @srem_v32i16(<32 x i16>* %a, <32 x i16>* %b) vscale_range(8,0) #0 { +define void @srem_v32i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: srem_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -444,14 +444,14 @@ define void @srem_v32i16(<32 x i16>* %a, <32 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = srem <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @srem_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(16,0) #0 { +define void @srem_v64i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: srem_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -465,14 +465,14 @@ define void @srem_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %res = srem <64 x i16> %op1, %op2 - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @srem_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @srem_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: srem_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -490,10 +490,10 @@ define void @srem_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) # ; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %res = srem <128 x i16> %op1, %op2 - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -529,7 +529,7 @@ define <4 x i32> @srem_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(1,0) # ret <4 x i32> %res } -define void @srem_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @srem_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: srem_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -540,14 +540,14 @@ define void @srem_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %res = srem <8 x i32> %op1, %op2 - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @srem_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @srem_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_128-LABEL: srem_v16i32: ; VBITS_GE_128: // %bb.0: ; VBITS_GE_128-NEXT: ldp q0, q1, [x0, #32] @@ -599,14 +599,14 @@ define void @srem_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: mls z0.s, p0/m, z2.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %res = srem <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @srem_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @srem_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: srem_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -617,14 +617,14 @@ define void @srem_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %res = srem <32 x i32> %op1, %op2 - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @srem_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @srem_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: srem_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -635,10 +635,10 @@ define void @srem_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %res = srem <64 x i32> %op1, %op2 - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -676,7 +676,7 @@ define <2 x i64> @srem_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(1,0) # ret <2 x i64> %res } -define void @srem_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @srem_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: srem_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -687,14 +687,14 @@ define void @srem_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %res = srem <4 x i64> %op1, %op2 - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @srem_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @srem_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_128-LABEL: srem_v8i64: ; VBITS_GE_128: // %bb.0: ; VBITS_GE_128-NEXT: ldp q4, q5, [x1] @@ -750,14 +750,14 @@ define void @srem_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: mls z0.d, p0/m, z2.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %res = srem <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @srem_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @srem_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: srem_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -768,14 +768,14 @@ define void @srem_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %res = srem <16 x i64> %op1, %op2 - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @srem_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @srem_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: srem_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -786,10 +786,10 @@ define void @srem_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %res = srem <32 x i64> %op1, %op2 - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } @@ -948,7 +948,7 @@ define <16 x i8> @urem_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 { ret <16 x i8> %res } -define void @urem_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(8,0) #0 { +define void @urem_v32i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: urem_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -965,14 +965,14 @@ define void @urem_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %res = urem <32 x i8> %op1, %op2 - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @urem_v64i8(<64 x i8>* %a, <64 x i8>* %b) vscale_range(16,0) #0 { +define void @urem_v64i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: urem_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl64 @@ -989,14 +989,14 @@ define void @urem_v64i8(<64 x i8>* %a, <64 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = urem <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @urem_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(16,0) #0 { +define void @urem_v128i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: urem_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -1016,14 +1016,14 @@ define void @urem_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %res = urem <128 x i8> %op1, %op2 - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @urem_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @urem_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: urem_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -1052,10 +1052,10 @@ define void @urem_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %res = urem <256 x i8> %op1, %op2 - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -1154,7 +1154,7 @@ define <8 x i16> @urem_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 { ret <8 x i16> %res } -define void @urem_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { +define void @urem_v16i16(ptr %a, ptr %b) #0 { ; VBITS_GE_128-LABEL: urem_v16i16: ; VBITS_GE_128: // %bb.0: ; VBITS_GE_128-NEXT: ldp q2, q0, [x0] @@ -1210,14 +1210,14 @@ define void @urem_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: mls z0.h, p0/m, z2.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %res = urem <16 x i16> %op1, %op2 - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @urem_v32i16(<32 x i16>* %a, <32 x i16>* %b) vscale_range(8,0) #0 { +define void @urem_v32i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: urem_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -1231,14 +1231,14 @@ define void @urem_v32i16(<32 x i16>* %a, <32 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = urem <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @urem_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(16,0) #0 { +define void @urem_v64i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: urem_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -1252,14 +1252,14 @@ define void @urem_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %res = urem <64 x i16> %op1, %op2 - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @urem_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @urem_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: urem_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1277,10 +1277,10 @@ define void @urem_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) # ; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %res = urem <128 x i16> %op1, %op2 - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -1316,7 +1316,7 @@ define <4 x i32> @urem_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(1,0) # ret <4 x i32> %res } -define void @urem_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @urem_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: urem_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1327,14 +1327,14 @@ define void @urem_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %res = urem <8 x i32> %op1, %op2 - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @urem_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @urem_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_128-LABEL: urem_v16i32: ; VBITS_GE_128: // %bb.0: ; VBITS_GE_128-NEXT: ldp q0, q1, [x0, #32] @@ -1386,14 +1386,14 @@ define void @urem_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: mls z0.s, p0/m, z2.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %res = urem <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @urem_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @urem_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: urem_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1404,14 +1404,14 @@ define void @urem_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %res = urem <32 x i32> %op1, %op2 - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @urem_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @urem_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: urem_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1422,10 +1422,10 @@ define void @urem_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %res = urem <64 x i32> %op1, %op2 - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -1463,7 +1463,7 @@ define <2 x i64> @urem_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(1,0) # ret <2 x i64> %res } -define void @urem_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @urem_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: urem_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1474,14 +1474,14 @@ define void @urem_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %res = urem <4 x i64> %op1, %op2 - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @urem_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @urem_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_128-LABEL: urem_v8i64: ; VBITS_GE_128: // %bb.0: ; VBITS_GE_128-NEXT: ldp q4, q5, [x1] @@ -1537,14 +1537,14 @@ define void @urem_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: mls z0.d, p0/m, z2.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %res = urem <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @urem_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @urem_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: urem_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1555,14 +1555,14 @@ define void @urem_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %res = urem <16 x i64> %op1, %op2 - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @urem_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @urem_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: urem_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1573,10 +1573,10 @@ define void @urem_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %res = urem <32 x i64> %op1, %op2 - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll index 0194c9f..e10a353 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll @@ -31,7 +31,7 @@ define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, i1 %mask) vscale_ ret <16 x i8> %sel } -define void @select_v32i8(<32 x i8>* %a, <32 x i8>* %b, i1 %mask) vscale_range(2,0) #0 { +define void @select_v32i8(ptr %a, ptr %b, i1 %mask) vscale_range(2,0) #0 { ; CHECK-LABEL: select_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -45,14 +45,14 @@ define void @select_v32i8(<32 x i8>* %a, <32 x i8>* %b, i1 %mask) vscale_range(2 ; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <32 x i8>, <32 x i8>* %a - %op2 = load volatile <32 x i8>, <32 x i8>* %b + %op1 = load volatile <32 x i8>, ptr %a + %op2 = load volatile <32 x i8>, ptr %b %sel = select i1 %mask, <32 x i8> %op1, <32 x i8> %op2 - store <32 x i8> %sel, <32 x i8>* %a + store <32 x i8> %sel, ptr %a ret void } -define void @select_v64i8(<64 x i8>* %a, <64 x i8>* %b, i1 %mask) #0 { +define void @select_v64i8(ptr %a, ptr %b, i1 %mask) #0 { ; VBITS_GE_256-LABEL: select_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -85,14 +85,14 @@ define void @select_v64i8(<64 x i8>* %a, <64 x i8>* %b, i1 %mask) #0 { ; VBITS_GE_512-NEXT: sel z0.b, p1, z0.b, z1.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load volatile <64 x i8>, <64 x i8>* %a - %op2 = load volatile <64 x i8>, <64 x i8>* %b + %op1 = load volatile <64 x i8>, ptr %a + %op2 = load volatile <64 x i8>, ptr %b %sel = select i1 %mask, <64 x i8> %op1, <64 x i8> %op2 - store <64 x i8> %sel, <64 x i8>* %a + store <64 x i8> %sel, ptr %a ret void } -define void @select_v128i8(<128 x i8>* %a, <128 x i8>* %b, i1 %mask) vscale_range(8,0) #0 { +define void @select_v128i8(ptr %a, ptr %b, i1 %mask) vscale_range(8,0) #0 { ; CHECK-LABEL: select_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -106,14 +106,14 @@ define void @select_v128i8(<128 x i8>* %a, <128 x i8>* %b, i1 %mask) vscale_rang ; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <128 x i8>, <128 x i8>* %a - %op2 = load volatile <128 x i8>, <128 x i8>* %b + %op1 = load volatile <128 x i8>, ptr %a + %op2 = load volatile <128 x i8>, ptr %b %sel = select i1 %mask, <128 x i8> %op1, <128 x i8> %op2 - store <128 x i8> %sel, <128 x i8>* %a + store <128 x i8> %sel, ptr %a ret void } -define void @select_v256i8(<256 x i8>* %a, <256 x i8>* %b, i1 %mask) vscale_range(16,0) #0 { +define void @select_v256i8(ptr %a, ptr %b, i1 %mask) vscale_range(16,0) #0 { ; CHECK-LABEL: select_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -127,10 +127,10 @@ define void @select_v256i8(<256 x i8>* %a, <256 x i8>* %b, i1 %mask) vscale_rang ; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <256 x i8>, <256 x i8>* %a - %op2 = load volatile <256 x i8>, <256 x i8>* %b + %op1 = load volatile <256 x i8>, ptr %a + %op2 = load volatile <256 x i8>, ptr %b %sel = select i1 %mask, <256 x i8> %op1, <256 x i8> %op2 - store <256 x i8> %sel, <256 x i8>* %a + store <256 x i8> %sel, ptr %a ret void } @@ -160,7 +160,7 @@ define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, i1 %mask) vscale_ ret <8 x i16> %sel } -define void @select_v16i16(<16 x i16>* %a, <16 x i16>* %b, i1 %mask) vscale_range(2,0) #0 { +define void @select_v16i16(ptr %a, ptr %b, i1 %mask) vscale_range(2,0) #0 { ; CHECK-LABEL: select_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -174,14 +174,14 @@ define void @select_v16i16(<16 x i16>* %a, <16 x i16>* %b, i1 %mask) vscale_rang ; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <16 x i16>, <16 x i16>* %a - %op2 = load volatile <16 x i16>, <16 x i16>* %b + %op1 = load volatile <16 x i16>, ptr %a + %op2 = load volatile <16 x i16>, ptr %b %sel = select i1 %mask, <16 x i16> %op1, <16 x i16> %op2 - store <16 x i16> %sel, <16 x i16>* %a + store <16 x i16> %sel, ptr %a ret void } -define void @select_v32i16(<32 x i16>* %a, <32 x i16>* %b, i1 %mask) #0 { +define void @select_v32i16(ptr %a, ptr %b, i1 %mask) #0 { ; VBITS_GE_256-LABEL: select_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -214,14 +214,14 @@ define void @select_v32i16(<32 x i16>* %a, <32 x i16>* %b, i1 %mask) #0 { ; VBITS_GE_512-NEXT: sel z0.h, p1, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load volatile <32 x i16>, <32 x i16>* %a - %op2 = load volatile <32 x i16>, <32 x i16>* %b + %op1 = load volatile <32 x i16>, ptr %a + %op2 = load volatile <32 x i16>, ptr %b %sel = select i1 %mask, <32 x i16> %op1, <32 x i16> %op2 - store <32 x i16> %sel, <32 x i16>* %a + store <32 x i16> %sel, ptr %a ret void } -define void @select_v64i16(<64 x i16>* %a, <64 x i16>* %b, i1 %mask) vscale_range(8,0) #0 { +define void @select_v64i16(ptr %a, ptr %b, i1 %mask) vscale_range(8,0) #0 { ; CHECK-LABEL: select_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -235,14 +235,14 @@ define void @select_v64i16(<64 x i16>* %a, <64 x i16>* %b, i1 %mask) vscale_rang ; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <64 x i16>, <64 x i16>* %a - %op2 = load volatile <64 x i16>, <64 x i16>* %b + %op1 = load volatile <64 x i16>, ptr %a + %op2 = load volatile <64 x i16>, ptr %b %sel = select i1 %mask, <64 x i16> %op1, <64 x i16> %op2 - store <64 x i16> %sel, <64 x i16>* %a + store <64 x i16> %sel, ptr %a ret void } -define void @select_v128i16(<128 x i16>* %a, <128 x i16>* %b, i1 %mask) vscale_range(16,0) #0 { +define void @select_v128i16(ptr %a, ptr %b, i1 %mask) vscale_range(16,0) #0 { ; CHECK-LABEL: select_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -256,10 +256,10 @@ define void @select_v128i16(<128 x i16>* %a, <128 x i16>* %b, i1 %mask) vscale_r ; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <128 x i16>, <128 x i16>* %a - %op2 = load volatile <128 x i16>, <128 x i16>* %b + %op1 = load volatile <128 x i16>, ptr %a + %op2 = load volatile <128 x i16>, ptr %b %sel = select i1 %mask, <128 x i16> %op1, <128 x i16> %op2 - store <128 x i16> %sel, <128 x i16>* %a + store <128 x i16> %sel, ptr %a ret void } @@ -289,7 +289,7 @@ define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, i1 %mask) vscale_ ret <4 x i32> %sel } -define void @select_v8i32(<8 x i32>* %a, <8 x i32>* %b, i1 %mask) vscale_range(2,0) #0 { +define void @select_v8i32(ptr %a, ptr %b, i1 %mask) vscale_range(2,0) #0 { ; CHECK-LABEL: select_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -302,14 +302,14 @@ define void @select_v8i32(<8 x i32>* %a, <8 x i32>* %b, i1 %mask) vscale_range(2 ; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <8 x i32>, <8 x i32>* %a - %op2 = load volatile <8 x i32>, <8 x i32>* %b + %op1 = load volatile <8 x i32>, ptr %a + %op2 = load volatile <8 x i32>, ptr %b %sel = select i1 %mask, <8 x i32> %op1, <8 x i32> %op2 - store <8 x i32> %sel, <8 x i32>* %a + store <8 x i32> %sel, ptr %a ret void } -define void @select_v16i32(<16 x i32>* %a, <16 x i32>* %b, i1 %mask) #0 { +define void @select_v16i32(ptr %a, ptr %b, i1 %mask) #0 { ; VBITS_GE_256-LABEL: select_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -340,14 +340,14 @@ define void @select_v16i32(<16 x i32>* %a, <16 x i32>* %b, i1 %mask) #0 { ; VBITS_GE_512-NEXT: sel z0.s, p1, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load volatile <16 x i32>, <16 x i32>* %a - %op2 = load volatile <16 x i32>, <16 x i32>* %b + %op1 = load volatile <16 x i32>, ptr %a + %op2 = load volatile <16 x i32>, ptr %b %sel = select i1 %mask, <16 x i32> %op1, <16 x i32> %op2 - store <16 x i32> %sel, <16 x i32>* %a + store <16 x i32> %sel, ptr %a ret void } -define void @select_v32i32(<32 x i32>* %a, <32 x i32>* %b, i1 %mask) vscale_range(8,0) #0 { +define void @select_v32i32(ptr %a, ptr %b, i1 %mask) vscale_range(8,0) #0 { ; CHECK-LABEL: select_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -360,14 +360,14 @@ define void @select_v32i32(<32 x i32>* %a, <32 x i32>* %b, i1 %mask) vscale_rang ; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <32 x i32>, <32 x i32>* %a - %op2 = load volatile <32 x i32>, <32 x i32>* %b + %op1 = load volatile <32 x i32>, ptr %a + %op2 = load volatile <32 x i32>, ptr %b %sel = select i1 %mask, <32 x i32> %op1, <32 x i32> %op2 - store <32 x i32> %sel, <32 x i32>* %a + store <32 x i32> %sel, ptr %a ret void } -define void @select_v64i32(<64 x i32>* %a, <64 x i32>* %b, i1 %mask) vscale_range(16,0) #0 { +define void @select_v64i32(ptr %a, ptr %b, i1 %mask) vscale_range(16,0) #0 { ; CHECK-LABEL: select_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -380,10 +380,10 @@ define void @select_v64i32(<64 x i32>* %a, <64 x i32>* %b, i1 %mask) vscale_rang ; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <64 x i32>, <64 x i32>* %a - %op2 = load volatile <64 x i32>, <64 x i32>* %b + %op1 = load volatile <64 x i32>, ptr %a + %op2 = load volatile <64 x i32>, ptr %b %sel = select i1 %mask, <64 x i32> %op1, <64 x i32> %op2 - store <64 x i32> %sel, <64 x i32>* %a + store <64 x i32> %sel, ptr %a ret void } @@ -413,7 +413,7 @@ define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, i1 %mask) vscale_ ret <2 x i64> %sel } -define void @select_v4i64(<4 x i64>* %a, <4 x i64>* %b, i1 %mask) vscale_range(2,0) #0 { +define void @select_v4i64(ptr %a, ptr %b, i1 %mask) vscale_range(2,0) #0 { ; CHECK-LABEL: select_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -426,14 +426,14 @@ define void @select_v4i64(<4 x i64>* %a, <4 x i64>* %b, i1 %mask) vscale_range(2 ; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <4 x i64>, <4 x i64>* %a - %op2 = load volatile <4 x i64>, <4 x i64>* %b + %op1 = load volatile <4 x i64>, ptr %a + %op2 = load volatile <4 x i64>, ptr %b %sel = select i1 %mask, <4 x i64> %op1, <4 x i64> %op2 - store <4 x i64> %sel, <4 x i64>* %a + store <4 x i64> %sel, ptr %a ret void } -define void @select_v8i64(<8 x i64>* %a, <8 x i64>* %b, i1 %mask) #0 { +define void @select_v8i64(ptr %a, ptr %b, i1 %mask) #0 { ; VBITS_GE_256-LABEL: select_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -464,14 +464,14 @@ define void @select_v8i64(<8 x i64>* %a, <8 x i64>* %b, i1 %mask) #0 { ; VBITS_GE_512-NEXT: sel z0.d, p1, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load volatile <8 x i64>, <8 x i64>* %a - %op2 = load volatile <8 x i64>, <8 x i64>* %b + %op1 = load volatile <8 x i64>, ptr %a + %op2 = load volatile <8 x i64>, ptr %b %sel = select i1 %mask, <8 x i64> %op1, <8 x i64> %op2 - store <8 x i64> %sel, <8 x i64>* %a + store <8 x i64> %sel, ptr %a ret void } -define void @select_v16i64(<16 x i64>* %a, <16 x i64>* %b, i1 %mask) vscale_range(8,0) #0 { +define void @select_v16i64(ptr %a, ptr %b, i1 %mask) vscale_range(8,0) #0 { ; CHECK-LABEL: select_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -484,14 +484,14 @@ define void @select_v16i64(<16 x i64>* %a, <16 x i64>* %b, i1 %mask) vscale_rang ; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <16 x i64>, <16 x i64>* %a - %op2 = load volatile <16 x i64>, <16 x i64>* %b + %op1 = load volatile <16 x i64>, ptr %a + %op2 = load volatile <16 x i64>, ptr %b %sel = select i1 %mask, <16 x i64> %op1, <16 x i64> %op2 - store <16 x i64> %sel, <16 x i64>* %a + store <16 x i64> %sel, ptr %a ret void } -define void @select_v32i64(<32 x i64>* %a, <32 x i64>* %b, i1 %mask) vscale_range(16,0) #0 { +define void @select_v32i64(ptr %a, ptr %b, i1 %mask) vscale_range(16,0) #0 { ; CHECK-LABEL: select_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w2, #0x1 @@ -504,10 +504,10 @@ define void @select_v32i64(<32 x i64>* %a, <32 x i64>* %b, i1 %mask) vscale_rang ; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load volatile <32 x i64>, <32 x i64>* %a - %op2 = load volatile <32 x i64>, <32 x i64>* %b + %op1 = load volatile <32 x i64>, ptr %a + %op2 = load volatile <32 x i64>, ptr %b %sel = select i1 %mask, <32 x i64> %op1, <32 x i64> %op2 - store <32 x i64> %sel, <32 x i64>* %a + store <32 x i64> %sel, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll index 23e37d3..24439ef 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll @@ -31,7 +31,7 @@ define <16 x i8> @ashr_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) # ret <16 x i8> %res } -define void @ashr_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @ashr_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: ashr_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -40,14 +40,14 @@ define void @ashr_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %res = ashr <32 x i8> %op1, %op2 - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @ashr_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @ashr_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: ashr_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -70,14 +70,14 @@ define void @ashr_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: asr z0.b, p0/m, z0.b, z1.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = ashr <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @ashr_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @ashr_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: ashr_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -86,14 +86,14 @@ define void @ashr_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %res = ashr <128 x i8> %op1, %op2 - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @ashr_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @ashr_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: ashr_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -102,10 +102,10 @@ define void @ashr_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %res = ashr <256 x i8> %op1, %op2 - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -131,7 +131,7 @@ define <8 x i16> @ashr_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) # ret <8 x i16> %res } -define void @ashr_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @ashr_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: ashr_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -140,14 +140,14 @@ define void @ashr_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %res = ashr <16 x i16> %op1, %op2 - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @ashr_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @ashr_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: ashr_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -170,14 +170,14 @@ define void @ashr_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: asr z0.h, p0/m, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = ashr <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @ashr_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @ashr_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: ashr_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -186,14 +186,14 @@ define void @ashr_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %res = ashr <64 x i16> %op1, %op2 - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @ashr_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @ashr_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: ashr_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -202,10 +202,10 @@ define void @ashr_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) # ; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %res = ashr <128 x i16> %op1, %op2 - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -231,7 +231,7 @@ define <4 x i32> @ashr_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) # ret <4 x i32> %res } -define void @ashr_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @ashr_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: ashr_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -240,14 +240,14 @@ define void @ashr_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %res = ashr <8 x i32> %op1, %op2 - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @ashr_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @ashr_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: ashr_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -270,14 +270,14 @@ define void @ashr_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: asr z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %res = ashr <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @ashr_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @ashr_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: ashr_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -286,14 +286,14 @@ define void @ashr_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %res = ashr <32 x i32> %op1, %op2 - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @ashr_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @ashr_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: ashr_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -302,10 +302,10 @@ define void @ashr_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %res = ashr <64 x i32> %op1, %op2 - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -331,7 +331,7 @@ define <2 x i64> @ashr_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) # ret <2 x i64> %res } -define void @ashr_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @ashr_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: ashr_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -340,14 +340,14 @@ define void @ashr_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %res = ashr <4 x i64> %op1, %op2 - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @ashr_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @ashr_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: ashr_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -370,14 +370,14 @@ define void @ashr_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: asr z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %res = ashr <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @ashr_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @ashr_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: ashr_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -386,14 +386,14 @@ define void @ashr_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %res = ashr <16 x i64> %op1, %op2 - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @ashr_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @ashr_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: ashr_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -402,10 +402,10 @@ define void @ashr_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %res = ashr <32 x i64> %op1, %op2 - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } @@ -435,7 +435,7 @@ define <16 x i8> @lshr_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) # ret <16 x i8> %res } -define void @lshr_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @lshr_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: lshr_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -444,14 +444,14 @@ define void @lshr_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %res = lshr <32 x i8> %op1, %op2 - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @lshr_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @lshr_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: lshr_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -474,14 +474,14 @@ define void @lshr_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: lsr z0.b, p0/m, z0.b, z1.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = lshr <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @lshr_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @lshr_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: lshr_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -490,14 +490,14 @@ define void @lshr_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %res = lshr <128 x i8> %op1, %op2 - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @lshr_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @lshr_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: lshr_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -506,10 +506,10 @@ define void @lshr_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %res = lshr <256 x i8> %op1, %op2 - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -535,7 +535,7 @@ define <8 x i16> @lshr_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) # ret <8 x i16> %res } -define void @lshr_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @lshr_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: lshr_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -544,14 +544,14 @@ define void @lshr_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %res = lshr <16 x i16> %op1, %op2 - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @lshr_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @lshr_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: lshr_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -574,14 +574,14 @@ define void @lshr_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: lsr z0.h, p0/m, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = lshr <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @lshr_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @lshr_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: lshr_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -590,14 +590,14 @@ define void @lshr_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %res = lshr <64 x i16> %op1, %op2 - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @lshr_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @lshr_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: lshr_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -606,10 +606,10 @@ define void @lshr_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) # ; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %res = lshr <128 x i16> %op1, %op2 - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -635,7 +635,7 @@ define <4 x i32> @lshr_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) # ret <4 x i32> %res } -define void @lshr_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @lshr_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: lshr_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -644,14 +644,14 @@ define void @lshr_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %res = lshr <8 x i32> %op1, %op2 - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @lshr_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @lshr_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: lshr_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -674,14 +674,14 @@ define void @lshr_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: lsr z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %res = lshr <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @lshr_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @lshr_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: lshr_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -690,14 +690,14 @@ define void @lshr_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %res = lshr <32 x i32> %op1, %op2 - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @lshr_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @lshr_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: lshr_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -706,10 +706,10 @@ define void @lshr_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %res = lshr <64 x i32> %op1, %op2 - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -735,7 +735,7 @@ define <2 x i64> @lshr_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) # ret <2 x i64> %res } -define void @lshr_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @lshr_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: lshr_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -744,14 +744,14 @@ define void @lshr_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %res = lshr <4 x i64> %op1, %op2 - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @lshr_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @lshr_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: lshr_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -774,14 +774,14 @@ define void @lshr_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: lsr z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %res = lshr <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @lshr_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @lshr_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: lshr_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -790,14 +790,14 @@ define void @lshr_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %res = lshr <16 x i64> %op1, %op2 - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @lshr_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @lshr_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: lshr_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -806,10 +806,10 @@ define void @lshr_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %res = lshr <32 x i64> %op1, %op2 - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } @@ -837,7 +837,7 @@ define <16 x i8> @shl_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) #0 ret <16 x i8> %res } -define void @shl_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @shl_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: shl_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -846,14 +846,14 @@ define void @shl_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %res = shl <32 x i8> %op1, %op2 - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @shl_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @shl_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: shl_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -876,14 +876,14 @@ define void @shl_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: lsl z0.b, p0/m, z0.b, z1.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = shl <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @shl_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @shl_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: shl_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -892,14 +892,14 @@ define void @shl_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %res = shl <128 x i8> %op1, %op2 - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @shl_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @shl_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: shl_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -908,10 +908,10 @@ define void @shl_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %res = shl <256 x i8> %op1, %op2 - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -935,7 +935,7 @@ define <8 x i16> @shl_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) #0 ret <8 x i16> %res } -define void @shl_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @shl_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: shl_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -944,14 +944,14 @@ define void @shl_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %res = shl <16 x i16> %op1, %op2 - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @shl_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @shl_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: shl_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -974,14 +974,14 @@ define void @shl_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: lsl z0.h, p0/m, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = shl <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @shl_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @shl_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: shl_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -990,14 +990,14 @@ define void @shl_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %res = shl <64 x i16> %op1, %op2 - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @shl_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @shl_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: shl_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1006,10 +1006,10 @@ define void @shl_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 ; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %res = shl <128 x i16> %op1, %op2 - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -1033,7 +1033,7 @@ define <4 x i32> @shl_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) #0 ret <4 x i32> %res } -define void @shl_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @shl_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: shl_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1042,14 +1042,14 @@ define void @shl_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %res = shl <8 x i32> %op1, %op2 - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @shl_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @shl_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: shl_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1072,14 +1072,14 @@ define void @shl_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: lsl z0.s, p0/m, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %res = shl <16 x i32> %op1, %op2 - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @shl_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @shl_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: shl_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1088,14 +1088,14 @@ define void @shl_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %res = shl <32 x i32> %op1, %op2 - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @shl_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @shl_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: shl_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1104,10 +1104,10 @@ define void @shl_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %res = shl <64 x i32> %op1, %op2 - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -1131,7 +1131,7 @@ define <2 x i64> @shl_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) #0 ret <2 x i64> %res } -define void @shl_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @shl_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: shl_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1140,14 +1140,14 @@ define void @shl_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %res = shl <4 x i64> %op1, %op2 - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @shl_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @shl_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: shl_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1170,14 +1170,14 @@ define void @shl_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: lsl z0.d, p0/m, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %res = shl <8 x i64> %op1, %op2 - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @shl_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @shl_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: shl_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1186,14 +1186,14 @@ define void @shl_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %res = shl <16 x i64> %op1, %op2 - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @shl_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @shl_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: shl_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1202,10 +1202,10 @@ define void @shl_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %res = shl <32 x i64> %op1, %op2 - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll index f4e1a82..4ca8ef8c 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll @@ -20,20 +20,20 @@ define <4 x half> @ucvtf_v4i16_v4f16(<4 x i16> %op1) vscale_range(2,0) #0 { } ; Don't use SVE for 128-bit vectors. -define void @ucvtf_v8i16_v8f16(<8 x i16>* %a, <8 x half>* %b) vscale_range(2,0) #0 { +define void @ucvtf_v8i16_v8f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: ucvtf_v8i16_v8f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ucvtf v0.8h, v0.8h ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %op1 = load <8 x i16>, <8 x i16>* %a + %op1 = load <8 x i16>, ptr %a %res = uitofp <8 x i16> %op1 to <8 x half> - store <8 x half> %res, <8 x half>* %b + store <8 x half> %res, ptr %b ret void } -define void @ucvtf_v16i16_v16f16(<16 x i16>* %a, <16 x half>* %b) vscale_range(2,0) #0 { +define void @ucvtf_v16i16_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: ucvtf_v16i16_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -41,13 +41,13 @@ define void @ucvtf_v16i16_v16f16(<16 x i16>* %a, <16 x half>* %b) vscale_range(2 ; CHECK-NEXT: ucvtf z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a + %op1 = load <16 x i16>, ptr %a %res = uitofp <16 x i16> %op1 to <16 x half> - store <16 x half> %res, <16 x half>* %b + store <16 x half> %res, ptr %b ret void } -define void @ucvtf_v32i16_v32f16(<32 x i16>* %a, <32 x half>* %b) #0 { +define void @ucvtf_v32i16_v32f16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: ucvtf_v32i16_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -67,13 +67,13 @@ define void @ucvtf_v32i16_v32f16(<32 x i16>* %a, <32 x half>* %b) #0 { ; VBITS_GE_512-NEXT: ucvtf z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %res = uitofp <32 x i16> %op1 to <32 x half> - store <32 x half> %res, <32 x half>* %b + store <32 x half> %res, ptr %b ret void } -define void @ucvtf_v64i16_v64f16(<64 x i16>* %a, <64 x half>* %b) vscale_range(8,0) #0 { +define void @ucvtf_v64i16_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: ucvtf_v64i16_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -81,13 +81,13 @@ define void @ucvtf_v64i16_v64f16(<64 x i16>* %a, <64 x half>* %b) vscale_range(8 ; CHECK-NEXT: ucvtf z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a + %op1 = load <64 x i16>, ptr %a %res = uitofp <64 x i16> %op1 to <64 x half> - store <64 x half> %res, <64 x half>* %b + store <64 x half> %res, ptr %b ret void } -define void @ucvtf_v128i16_v128f16(<128 x i16>* %a, <128 x half>* %b) vscale_range(16,0) #0 { +define void @ucvtf_v128i16_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: ucvtf_v128i16_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -95,9 +95,9 @@ define void @ucvtf_v128i16_v128f16(<128 x i16>* %a, <128 x half>* %b) vscale_ran ; CHECK-NEXT: ucvtf z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a + %op1 = load <128 x i16>, ptr %a %res = uitofp <128 x i16> %op1 to <128 x half> - store <128 x half> %res, <128 x half>* %b + store <128 x half> %res, ptr %b ret void } @@ -128,7 +128,7 @@ define <4 x float> @ucvtf_v4i16_v4f32(<4 x i16> %op1) vscale_range(2,0) #0 { ret <4 x float> %res } -define void @ucvtf_v8i16_v8f32(<8 x i16>* %a, <8 x float>* %b) vscale_range(2,0) #0 { +define void @ucvtf_v8i16_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: ucvtf_v8i16_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -137,13 +137,13 @@ define void @ucvtf_v8i16_v8f32(<8 x i16>* %a, <8 x float>* %b) vscale_range(2,0) ; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <8 x i16>, <8 x i16>* %a + %op1 = load <8 x i16>, ptr %a %res = uitofp <8 x i16> %op1 to <8 x float> - store <8 x float> %res, <8 x float>* %b + store <8 x float> %res, ptr %b ret void } -define void @ucvtf_v16i16_v16f32(<16 x i16>* %a, <16 x float>* %b) #0 { +define void @ucvtf_v16i16_v16f32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: ucvtf_v16i16_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.h, vl16 @@ -166,13 +166,13 @@ define void @ucvtf_v16i16_v16f32(<16 x i16>* %a, <16 x float>* %b) #0 { ; VBITS_GE_512-NEXT: ucvtf z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a + %op1 = load <16 x i16>, ptr %a %res = uitofp <16 x i16> %op1 to <16 x float> - store <16 x float> %res, <16 x float>* %b + store <16 x float> %res, ptr %b ret void } -define void @ucvtf_v32i16_v32f32(<32 x i16>* %a, <32 x float>* %b) vscale_range(8,0) #0 { +define void @ucvtf_v32i16_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: ucvtf_v32i16_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -180,13 +180,13 @@ define void @ucvtf_v32i16_v32f32(<32 x i16>* %a, <32 x float>* %b) vscale_range( ; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %res = uitofp <32 x i16> %op1 to <32 x float> - store <32 x float> %res, <32 x float>* %b + store <32 x float> %res, ptr %b ret void } -define void @ucvtf_v64i16_v64f32(<64 x i16>* %a, <64 x float>* %b) vscale_range(16,0) #0 { +define void @ucvtf_v64i16_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: ucvtf_v64i16_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -194,9 +194,9 @@ define void @ucvtf_v64i16_v64f32(<64 x i16>* %a, <64 x float>* %b) vscale_range( ; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a + %op1 = load <64 x i16>, ptr %a %res = uitofp <64 x i16> %op1 to <64 x float> - store <64 x float> %res, <64 x float>* %b + store <64 x float> %res, ptr %b ret void } @@ -232,7 +232,7 @@ define <2 x double> @ucvtf_v2i16_v2f64(<2 x i16> %op1) vscale_range(2,0) #0 { ret <2 x double> %res } -define void @ucvtf_v4i16_v4f64(<4 x i16>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @ucvtf_v4i16_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: ucvtf_v4i16_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -242,13 +242,13 @@ define void @ucvtf_v4i16_v4f64(<4 x i16>* %a, <4 x double>* %b) vscale_range(2,0 ; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x i16>, <4 x i16>* %a + %op1 = load <4 x i16>, ptr %a %res = uitofp <4 x i16> %op1 to <4 x double> - store <4 x double> %res, <4 x double>* %b + store <4 x double> %res, ptr %b ret void } -define void @ucvtf_v8i16_v8f64(<8 x i16>* %a, <8 x double>* %b) #0 { +define void @ucvtf_v8i16_v8f64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: ucvtf_v8i16_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ldr q0, [x0] @@ -274,13 +274,13 @@ define void @ucvtf_v8i16_v8f64(<8 x i16>* %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: ucvtf z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i16>, <8 x i16>* %a + %op1 = load <8 x i16>, ptr %a %res = uitofp <8 x i16> %op1 to <8 x double> - store <8 x double> %res, <8 x double>* %b + store <8 x double> %res, ptr %b ret void } -define void @ucvtf_v16i16_v16f64(<16 x i16>* %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @ucvtf_v16i16_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: ucvtf_v16i16_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -288,13 +288,13 @@ define void @ucvtf_v16i16_v16f64(<16 x i16>* %a, <16 x double>* %b) vscale_range ; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a + %op1 = load <16 x i16>, ptr %a %res = uitofp <16 x i16> %op1 to <16 x double> - store <16 x double> %res, <16 x double>* %b + store <16 x double> %res, ptr %b ret void } -define void @ucvtf_v32i16_v32f64(<32 x i16>* %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @ucvtf_v32i16_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: ucvtf_v32i16_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -302,9 +302,9 @@ define void @ucvtf_v32i16_v32f64(<32 x i16>* %a, <32 x double>* %b) vscale_range ; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %res = uitofp <32 x i16> %op1 to <32 x double> - store <32 x double> %res, <32 x double>* %b + store <32 x double> %res, ptr %b ret void } @@ -335,7 +335,7 @@ define <4 x half> @ucvtf_v4i32_v4f16(<4 x i32> %op1) vscale_range(2,0) #0 { ret <4 x half> %res } -define <8 x half> @ucvtf_v8i32_v8f16(<8 x i32>* %a) vscale_range(2,0) #0 { +define <8 x half> @ucvtf_v8i32_v8f16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: ucvtf_v8i32_v8f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -345,12 +345,12 @@ define <8 x half> @ucvtf_v8i32_v8f16(<8 x i32>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a + %op1 = load <8 x i32>, ptr %a %res = uitofp <8 x i32> %op1 to <8 x half> ret <8 x half> %res } -define void @ucvtf_v16i32_v16f16(<16 x i32>* %a, <16 x half>* %b) #0 { +define void @ucvtf_v16i32_v16f16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: ucvtf_v16i32_v16f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -378,13 +378,13 @@ define void @ucvtf_v16i32_v16f16(<16 x i32>* %a, <16 x half>* %b) #0 { ; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %res = uitofp <16 x i32> %op1 to <16 x half> - store <16 x half> %res, <16 x half>* %b + store <16 x half> %res, ptr %b ret void } -define void @ucvtf_v32i32_v32f16(<32 x i32>* %a, <32 x half>* %b) vscale_range(8,0) #0 { +define void @ucvtf_v32i32_v32f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: ucvtf_v32i32_v32f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -395,13 +395,13 @@ define void @ucvtf_v32i32_v32f16(<32 x i32>* %a, <32 x half>* %b) vscale_range(8 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a + %op1 = load <32 x i32>, ptr %a %res = uitofp <32 x i32> %op1 to <32 x half> - store <32 x half> %res, <32 x half>* %b + store <32 x half> %res, ptr %b ret void } -define void @ucvtf_v64i32_v64f16(<64 x i32>* %a, <64 x half>* %b) vscale_range(16,0) #0 { +define void @ucvtf_v64i32_v64f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: ucvtf_v64i32_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -412,9 +412,9 @@ define void @ucvtf_v64i32_v64f16(<64 x i32>* %a, <64 x half>* %b) vscale_range(1 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a + %op1 = load <64 x i32>, ptr %a %res = uitofp <64 x i32> %op1 to <64 x half> - store <64 x half> %res, <64 x half>* %b + store <64 x half> %res, ptr %b ret void } @@ -442,7 +442,7 @@ define <4 x float> @ucvtf_v4i32_v4f32(<4 x i32> %op1) vscale_range(2,0) #0 { ret <4 x float> %res } -define void @ucvtf_v8i32_v8f32(<8 x i32>* %a, <8 x float>* %b) vscale_range(2,0) #0 { +define void @ucvtf_v8i32_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: ucvtf_v8i32_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -450,13 +450,13 @@ define void @ucvtf_v8i32_v8f32(<8 x i32>* %a, <8 x float>* %b) vscale_range(2,0) ; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a + %op1 = load <8 x i32>, ptr %a %res = uitofp <8 x i32> %op1 to <8 x float> - store <8 x float> %res, <8 x float>* %b + store <8 x float> %res, ptr %b ret void } -define void @ucvtf_v16i32_v16f32(<16 x i32>* %a, <16 x float>* %b) #0 { +define void @ucvtf_v16i32_v16f32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: ucvtf_v16i32_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -476,13 +476,13 @@ define void @ucvtf_v16i32_v16f32(<16 x i32>* %a, <16 x float>* %b) #0 { ; VBITS_GE_512-NEXT: ucvtf z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %res = uitofp <16 x i32> %op1 to <16 x float> - store <16 x float> %res, <16 x float>* %b + store <16 x float> %res, ptr %b ret void } -define void @ucvtf_v32i32_v32f32(<32 x i32>* %a, <32 x float>* %b) vscale_range(8,0) #0 { +define void @ucvtf_v32i32_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: ucvtf_v32i32_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -490,13 +490,13 @@ define void @ucvtf_v32i32_v32f32(<32 x i32>* %a, <32 x float>* %b) vscale_range( ; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a + %op1 = load <32 x i32>, ptr %a %res = uitofp <32 x i32> %op1 to <32 x float> - store <32 x float> %res, <32 x float>* %b + store <32 x float> %res, ptr %b ret void } -define void @ucvtf_v64i32_v64f32(<64 x i32>* %a, <64 x float>* %b) vscale_range(16,0) #0 { +define void @ucvtf_v64i32_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: ucvtf_v64i32_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -504,9 +504,9 @@ define void @ucvtf_v64i32_v64f32(<64 x i32>* %a, <64 x float>* %b) vscale_range( ; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a + %op1 = load <64 x i32>, ptr %a %res = uitofp <64 x i32> %op1 to <64 x float> - store <64 x float> %res, <64 x float>* %b + store <64 x float> %res, ptr %b ret void } @@ -537,7 +537,7 @@ define <2 x double> @ucvtf_v2i32_v2f64(<2 x i32> %op1) vscale_range(2,0) #0 { ret <2 x double> %res } -define void @ucvtf_v4i32_v4f64(<4 x i32>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @ucvtf_v4i32_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: ucvtf_v4i32_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -546,13 +546,13 @@ define void @ucvtf_v4i32_v4f64(<4 x i32>* %a, <4 x double>* %b) vscale_range(2,0 ; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x i32>, <4 x i32>* %a + %op1 = load <4 x i32>, ptr %a %res = uitofp <4 x i32> %op1 to <4 x double> - store <4 x double> %res, <4 x double>* %b + store <4 x double> %res, ptr %b ret void } -define void @ucvtf_v8i32_v8f64(<8 x i32>* %a, <8 x double>* %b) #0 { +define void @ucvtf_v8i32_v8f64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: ucvtf_v8i32_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.s, vl8 @@ -575,13 +575,13 @@ define void @ucvtf_v8i32_v8f64(<8 x i32>* %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: ucvtf z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a + %op1 = load <8 x i32>, ptr %a %res = uitofp <8 x i32> %op1 to <8 x double> - store <8 x double> %res, <8 x double>* %b + store <8 x double> %res, ptr %b ret void } -define void @ucvtf_v16i32_v16f64(<16 x i32>* %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @ucvtf_v16i32_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: ucvtf_v16i32_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -589,13 +589,13 @@ define void @ucvtf_v16i32_v16f64(<16 x i32>* %a, <16 x double>* %b) vscale_range ; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %res = uitofp <16 x i32> %op1 to <16 x double> - store <16 x double> %res, <16 x double>* %b + store <16 x double> %res, ptr %b ret void } -define void @ucvtf_v32i32_v32f64(<32 x i32>* %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @ucvtf_v32i32_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: ucvtf_v32i32_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -603,9 +603,9 @@ define void @ucvtf_v32i32_v32f64(<32 x i32>* %a, <32 x double>* %b) vscale_range ; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a + %op1 = load <32 x i32>, ptr %a %res = uitofp <32 x i32> %op1 to <32 x double> - store <32 x double> %res, <32 x double>* %b + store <32 x double> %res, ptr %b ret void } @@ -640,7 +640,7 @@ define <2 x half> @ucvtf_v2i64_v2f16(<2 x i64> %op1) vscale_range(2,0) #0 { ret <2 x half> %res } -define <4 x half> @ucvtf_v4i64_v4f16(<4 x i64>* %a) vscale_range(2,0) #0 { +define <4 x half> @ucvtf_v4i64_v4f16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: ucvtf_v4i64_v4f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -651,12 +651,12 @@ define <4 x half> @ucvtf_v4i64_v4f16(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a + %op1 = load <4 x i64>, ptr %a %res = uitofp <4 x i64> %op1 to <4 x half> ret <4 x half> %res } -define <8 x half> @ucvtf_v8i64_v8f16(<8 x i64>* %a) #0 { +define <8 x half> @ucvtf_v8i64_v8f16(ptr %a) #0 { ; VBITS_GE_256-LABEL: ucvtf_v8i64_v8f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -684,12 +684,12 @@ define <8 x half> @ucvtf_v8i64_v8f16(<8 x i64>* %a) #0 { ; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h ; VBITS_GE_512-NEXT: // kill: def $q0 killed $q0 killed $z0 ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %res = uitofp <8 x i64> %op1 to <8 x half> ret <8 x half> %res } -define void @ucvtf_v16i64_v16f16(<16 x i64>* %a, <16 x half>* %b) vscale_range(8,0) #0 { +define void @ucvtf_v16i64_v16f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: ucvtf_v16i64_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -700,13 +700,13 @@ define void @ucvtf_v16i64_v16f16(<16 x i64>* %a, <16 x half>* %b) vscale_range(8 ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: st1h { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a + %op1 = load <16 x i64>, ptr %a %res = uitofp <16 x i64> %op1 to <16 x half> - store <16 x half> %res, <16 x half>* %b + store <16 x half> %res, ptr %b ret void } -define void @ucvtf_v32i64_v32f16(<32 x i64>* %a, <32 x half>* %b) vscale_range(16,0) #0 { +define void @ucvtf_v32i64_v32f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: ucvtf_v32i64_v32f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -717,9 +717,9 @@ define void @ucvtf_v32i64_v32f16(<32 x i64>* %a, <32 x half>* %b) vscale_range(1 ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: st1h { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a + %op1 = load <32 x i64>, ptr %a %res = uitofp <32 x i64> %op1 to <32 x half> - store <32 x half> %res, <32 x half>* %b + store <32 x half> %res, ptr %b ret void } @@ -750,7 +750,7 @@ define <2 x float> @ucvtf_v2i64_v2f32(<2 x i64> %op1) vscale_range(2,0) #0 { ret <2 x float> %res } -define <4 x float> @ucvtf_v4i64_v4f32(<4 x i64>* %a) vscale_range(2,0) #0 { +define <4 x float> @ucvtf_v4i64_v4f32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: ucvtf_v4i64_v4f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -760,12 +760,12 @@ define <4 x float> @ucvtf_v4i64_v4f32(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a + %op1 = load <4 x i64>, ptr %a %res = uitofp <4 x i64> %op1 to <4 x float> ret <4 x float> %res } -define void @ucvtf_v8i64_v8f32(<8 x i64>* %a, <8 x float>* %b) #0 { +define void @ucvtf_v8i64_v8f32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: ucvtf_v8i64_v8f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -793,13 +793,13 @@ define void @ucvtf_v8i64_v8f32(<8 x i64>* %a, <8 x float>* %b) #0 { ; VBITS_GE_512-NEXT: uzp1 z0.s, z0.s, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %res = uitofp <8 x i64> %op1 to <8 x float> - store <8 x float> %res, <8 x float>* %b + store <8 x float> %res, ptr %b ret void } -define void @ucvtf_v16i64_v16f32(<16 x i64>* %a, <16 x float>* %b) vscale_range(8,0) #0 { +define void @ucvtf_v16i64_v16f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: ucvtf_v16i64_v16f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -810,13 +810,13 @@ define void @ucvtf_v16i64_v16f32(<16 x i64>* %a, <16 x float>* %b) vscale_range( ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a + %op1 = load <16 x i64>, ptr %a %res = uitofp <16 x i64> %op1 to <16 x float> - store <16 x float> %res, <16 x float>* %b + store <16 x float> %res, ptr %b ret void } -define void @ucvtf_v32i64_v32f32(<32 x i64>* %a, <32 x float>* %b) vscale_range(16,0) #0 { +define void @ucvtf_v32i64_v32f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: ucvtf_v32i64_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -827,9 +827,9 @@ define void @ucvtf_v32i64_v32f32(<32 x i64>* %a, <32 x float>* %b) vscale_range( ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a + %op1 = load <32 x i64>, ptr %a %res = uitofp <32 x i64> %op1 to <32 x float> - store <32 x float> %res, <32 x float>* %b + store <32 x float> %res, ptr %b ret void } @@ -859,7 +859,7 @@ define <2 x double> @ucvtf_v2i64_v2f64(<2 x i64> %op1) vscale_range(2,0) #0 { ret <2 x double> %res } -define void @ucvtf_v4i64_v4f64(<4 x i64>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @ucvtf_v4i64_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: ucvtf_v4i64_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -867,13 +867,13 @@ define void @ucvtf_v4i64_v4f64(<4 x i64>* %a, <4 x double>* %b) vscale_range(2,0 ; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a + %op1 = load <4 x i64>, ptr %a %res = uitofp <4 x i64> %op1 to <4 x double> - store <4 x double> %res, <4 x double>* %b + store <4 x double> %res, ptr %b ret void } -define void @ucvtf_v8i64_v8f64(<8 x i64>* %a, <8 x double>* %b) #0 { +define void @ucvtf_v8i64_v8f64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: ucvtf_v8i64_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -893,13 +893,13 @@ define void @ucvtf_v8i64_v8f64(<8 x i64>* %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: ucvtf z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %res = uitofp <8 x i64> %op1 to <8 x double> - store <8 x double> %res, <8 x double>* %b + store <8 x double> %res, ptr %b ret void } -define void @ucvtf_v16i64_v16f64(<16 x i64>* %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @ucvtf_v16i64_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: ucvtf_v16i64_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -907,13 +907,13 @@ define void @ucvtf_v16i64_v16f64(<16 x i64>* %a, <16 x double>* %b) vscale_range ; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a + %op1 = load <16 x i64>, ptr %a %res = uitofp <16 x i64> %op1 to <16 x double> - store <16 x double> %res, <16 x double>* %b + store <16 x double> %res, ptr %b ret void } -define void @ucvtf_v32i64_v32f64(<32 x i64>* %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @ucvtf_v32i64_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: ucvtf_v32i64_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -921,9 +921,9 @@ define void @ucvtf_v32i64_v32f64(<32 x i64>* %a, <32 x double>* %b) vscale_range ; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a + %op1 = load <32 x i64>, ptr %a %res = uitofp <32 x i64> %op1 to <32 x double> - store <32 x double> %res, <32 x double>* %b + store <32 x double> %res, ptr %b ret void } @@ -942,20 +942,20 @@ define <4 x half> @scvtf_v4i16_v4f16(<4 x i16> %op1) vscale_range(2,0) #0 { } ; Don't use SVE for 128-bit vectors. -define void @scvtf_v8i16_v8f16(<8 x i16>* %a, <8 x half>* %b) vscale_range(2,0) #0 { +define void @scvtf_v8i16_v8f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: scvtf_v8i16_v8f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: scvtf v0.8h, v0.8h ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %op1 = load <8 x i16>, <8 x i16>* %a + %op1 = load <8 x i16>, ptr %a %res = sitofp <8 x i16> %op1 to <8 x half> - store <8 x half> %res, <8 x half>* %b + store <8 x half> %res, ptr %b ret void } -define void @scvtf_v16i16_v16f16(<16 x i16>* %a, <16 x half>* %b) vscale_range(2,0) #0 { +define void @scvtf_v16i16_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: scvtf_v16i16_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -963,13 +963,13 @@ define void @scvtf_v16i16_v16f16(<16 x i16>* %a, <16 x half>* %b) vscale_range(2 ; CHECK-NEXT: scvtf z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a + %op1 = load <16 x i16>, ptr %a %res = sitofp <16 x i16> %op1 to <16 x half> - store <16 x half> %res, <16 x half>* %b + store <16 x half> %res, ptr %b ret void } -define void @scvtf_v32i16_v32f16(<32 x i16>* %a, <32 x half>* %b) #0 { +define void @scvtf_v32i16_v32f16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: scvtf_v32i16_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -989,13 +989,13 @@ define void @scvtf_v32i16_v32f16(<32 x i16>* %a, <32 x half>* %b) #0 { ; VBITS_GE_512-NEXT: scvtf z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %res = sitofp <32 x i16> %op1 to <32 x half> - store <32 x half> %res, <32 x half>* %b + store <32 x half> %res, ptr %b ret void } -define void @scvtf_v64i16_v64f16(<64 x i16>* %a, <64 x half>* %b) vscale_range(8,0) #0 { +define void @scvtf_v64i16_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: scvtf_v64i16_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -1003,13 +1003,13 @@ define void @scvtf_v64i16_v64f16(<64 x i16>* %a, <64 x half>* %b) vscale_range(8 ; CHECK-NEXT: scvtf z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a + %op1 = load <64 x i16>, ptr %a %res = sitofp <64 x i16> %op1 to <64 x half> - store <64 x half> %res, <64 x half>* %b + store <64 x half> %res, ptr %b ret void } -define void @scvtf_v128i16_v128f16(<128 x i16>* %a, <128 x half>* %b) vscale_range(16,0) #0 { +define void @scvtf_v128i16_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: scvtf_v128i16_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1017,9 +1017,9 @@ define void @scvtf_v128i16_v128f16(<128 x i16>* %a, <128 x half>* %b) vscale_ran ; CHECK-NEXT: scvtf z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a + %op1 = load <128 x i16>, ptr %a %res = sitofp <128 x i16> %op1 to <128 x half> - store <128 x half> %res, <128 x half>* %b + store <128 x half> %res, ptr %b ret void } @@ -1050,7 +1050,7 @@ define <4 x float> @scvtf_v4i16_v4f32(<4 x i16> %op1) vscale_range(2,0) #0 { ret <4 x float> %res } -define void @scvtf_v8i16_v8f32(<8 x i16>* %a, <8 x float>* %b) vscale_range(2,0) #0 { +define void @scvtf_v8i16_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: scvtf_v8i16_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -1059,13 +1059,13 @@ define void @scvtf_v8i16_v8f32(<8 x i16>* %a, <8 x float>* %b) vscale_range(2,0) ; CHECK-NEXT: scvtf z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <8 x i16>, <8 x i16>* %a + %op1 = load <8 x i16>, ptr %a %res = sitofp <8 x i16> %op1 to <8 x float> - store <8 x float> %res, <8 x float>* %b + store <8 x float> %res, ptr %b ret void } -define void @scvtf_v16i16_v16f32(<16 x i16>* %a, <16 x float>* %b) #0 { +define void @scvtf_v16i16_v16f32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: scvtf_v16i16_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.h, vl16 @@ -1090,13 +1090,13 @@ define void @scvtf_v16i16_v16f32(<16 x i16>* %a, <16 x float>* %b) #0 { ; VBITS_GE_512-NEXT: scvtf z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a + %op1 = load <16 x i16>, ptr %a %res = sitofp <16 x i16> %op1 to <16 x float> - store <16 x float> %res, <16 x float>* %b + store <16 x float> %res, ptr %b ret void } -define void @scvtf_v32i16_v32f32(<32 x i16>* %a, <32 x float>* %b) vscale_range(8,0) #0 { +define void @scvtf_v32i16_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: scvtf_v32i16_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -1106,13 +1106,13 @@ define void @scvtf_v32i16_v32f32(<32 x i16>* %a, <32 x float>* %b) vscale_range( ; CHECK-NEXT: scvtf z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %res = sitofp <32 x i16> %op1 to <32 x float> - store <32 x float> %res, <32 x float>* %b + store <32 x float> %res, ptr %b ret void } -define void @scvtf_v64i16_v64f32(<64 x i16>* %a, <64 x float>* %b) vscale_range(16,0) #0 { +define void @scvtf_v64i16_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: scvtf_v64i16_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -1122,9 +1122,9 @@ define void @scvtf_v64i16_v64f32(<64 x i16>* %a, <64 x float>* %b) vscale_range( ; CHECK-NEXT: scvtf z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a + %op1 = load <64 x i16>, ptr %a %res = sitofp <64 x i16> %op1 to <64 x float> - store <64 x float> %res, <64 x float>* %b + store <64 x float> %res, ptr %b ret void } @@ -1160,7 +1160,7 @@ define <2 x double> @scvtf_v2i16_v2f64(<2 x i16> %op1) vscale_range(2,0) #0 { ret <2 x double> %res } -define void @scvtf_v4i16_v4f64(<4 x i16>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @scvtf_v4i16_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: scvtf_v4i16_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -1170,13 +1170,13 @@ define void @scvtf_v4i16_v4f64(<4 x i16>* %a, <4 x double>* %b) vscale_range(2,0 ; CHECK-NEXT: scvtf z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x i16>, <4 x i16>* %a + %op1 = load <4 x i16>, ptr %a %res = sitofp <4 x i16> %op1 to <4 x double> - store <4 x double> %res, <4 x double>* %b + store <4 x double> %res, ptr %b ret void } -define void @scvtf_v8i16_v8f64(<8 x i16>* %a, <8 x double>* %b) #0 { +define void @scvtf_v8i16_v8f64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: scvtf_v8i16_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ldr q0, [x0] @@ -1202,13 +1202,13 @@ define void @scvtf_v8i16_v8f64(<8 x i16>* %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: scvtf z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i16>, <8 x i16>* %a + %op1 = load <8 x i16>, ptr %a %res = sitofp <8 x i16> %op1 to <8 x double> - store <8 x double> %res, <8 x double>* %b + store <8 x double> %res, ptr %b ret void } -define void @scvtf_v16i16_v16f64(<16 x i16>* %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @scvtf_v16i16_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: scvtf_v16i16_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -1219,13 +1219,13 @@ define void @scvtf_v16i16_v16f64(<16 x i16>* %a, <16 x double>* %b) vscale_range ; CHECK-NEXT: scvtf z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a + %op1 = load <16 x i16>, ptr %a %res = sitofp <16 x i16> %op1 to <16 x double> - store <16 x double> %res, <16 x double>* %b + store <16 x double> %res, ptr %b ret void } -define void @scvtf_v32i16_v32f64(<32 x i16>* %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @scvtf_v32i16_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: scvtf_v32i16_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -1236,9 +1236,9 @@ define void @scvtf_v32i16_v32f64(<32 x i16>* %a, <32 x double>* %b) vscale_range ; CHECK-NEXT: scvtf z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %res = sitofp <32 x i16> %op1 to <32 x double> - store <32 x double> %res, <32 x double>* %b + store <32 x double> %res, ptr %b ret void } @@ -1269,7 +1269,7 @@ define <4 x half> @scvtf_v4i32_v4f16(<4 x i32> %op1) vscale_range(2,0) #0 { ret <4 x half> %res } -define <8 x half> @scvtf_v8i32_v8f16(<8 x i32>* %a) vscale_range(2,0) #0 { +define <8 x half> @scvtf_v8i32_v8f16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: scvtf_v8i32_v8f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1279,12 +1279,12 @@ define <8 x half> @scvtf_v8i32_v8f16(<8 x i32>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a + %op1 = load <8 x i32>, ptr %a %res = sitofp <8 x i32> %op1 to <8 x half> ret <8 x half> %res } -define void @scvtf_v16i32_v16f16(<16 x i32>* %a, <16 x half>* %b) #0 { +define void @scvtf_v16i32_v16f16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: scvtf_v16i32_v16f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1312,13 +1312,13 @@ define void @scvtf_v16i32_v16f16(<16 x i32>* %a, <16 x half>* %b) #0 { ; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %res = sitofp <16 x i32> %op1 to <16 x half> - store <16 x half> %res, <16 x half>* %b + store <16 x half> %res, ptr %b ret void } -define void @scvtf_v32i32_v32f16(<32 x i32>* %a, <32 x half>* %b) vscale_range(8,0) #0 { +define void @scvtf_v32i32_v32f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: scvtf_v32i32_v32f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1329,13 +1329,13 @@ define void @scvtf_v32i32_v32f16(<32 x i32>* %a, <32 x half>* %b) vscale_range(8 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a + %op1 = load <32 x i32>, ptr %a %res = sitofp <32 x i32> %op1 to <32 x half> - store <32 x half> %res, <32 x half>* %b + store <32 x half> %res, ptr %b ret void } -define void @scvtf_v64i32_v64f16(<64 x i32>* %a, <64 x half>* %b) vscale_range(16,0) #0 { +define void @scvtf_v64i32_v64f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: scvtf_v64i32_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1346,9 +1346,9 @@ define void @scvtf_v64i32_v64f16(<64 x i32>* %a, <64 x half>* %b) vscale_range(1 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a + %op1 = load <64 x i32>, ptr %a %res = sitofp <64 x i32> %op1 to <64 x half> - store <64 x half> %res, <64 x half>* %b + store <64 x half> %res, ptr %b ret void } @@ -1376,7 +1376,7 @@ define <4 x float> @scvtf_v4i32_v4f32(<4 x i32> %op1) vscale_range(2,0) #0 { ret <4 x float> %res } -define void @scvtf_v8i32_v8f32(<8 x i32>* %a, <8 x float>* %b) vscale_range(2,0) #0 { +define void @scvtf_v8i32_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: scvtf_v8i32_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -1384,13 +1384,13 @@ define void @scvtf_v8i32_v8f32(<8 x i32>* %a, <8 x float>* %b) vscale_range(2,0) ; CHECK-NEXT: scvtf z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a + %op1 = load <8 x i32>, ptr %a %res = sitofp <8 x i32> %op1 to <8 x float> - store <8 x float> %res, <8 x float>* %b + store <8 x float> %res, ptr %b ret void } -define void @scvtf_v16i32_v16f32(<16 x i32>* %a, <16 x float>* %b) #0 { +define void @scvtf_v16i32_v16f32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: scvtf_v16i32_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -1410,13 +1410,13 @@ define void @scvtf_v16i32_v16f32(<16 x i32>* %a, <16 x float>* %b) #0 { ; VBITS_GE_512-NEXT: scvtf z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %res = sitofp <16 x i32> %op1 to <16 x float> - store <16 x float> %res, <16 x float>* %b + store <16 x float> %res, ptr %b ret void } -define void @scvtf_v32i32_v32f32(<32 x i32>* %a, <32 x float>* %b) vscale_range(8,0) #0 { +define void @scvtf_v32i32_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: scvtf_v32i32_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1424,13 +1424,13 @@ define void @scvtf_v32i32_v32f32(<32 x i32>* %a, <32 x float>* %b) vscale_range( ; CHECK-NEXT: scvtf z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a + %op1 = load <32 x i32>, ptr %a %res = sitofp <32 x i32> %op1 to <32 x float> - store <32 x float> %res, <32 x float>* %b + store <32 x float> %res, ptr %b ret void } -define void @scvtf_v64i32_v64f32(<64 x i32>* %a, <64 x float>* %b) vscale_range(16,0) #0 { +define void @scvtf_v64i32_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: scvtf_v64i32_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1438,9 +1438,9 @@ define void @scvtf_v64i32_v64f32(<64 x i32>* %a, <64 x float>* %b) vscale_range( ; CHECK-NEXT: scvtf z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a + %op1 = load <64 x i32>, ptr %a %res = sitofp <64 x i32> %op1 to <64 x float> - store <64 x float> %res, <64 x float>* %b + store <64 x float> %res, ptr %b ret void } @@ -1471,7 +1471,7 @@ define <2 x double> @scvtf_v2i32_v2f64(<2 x i32> %op1) vscale_range(2,0) #0 { ret <2 x double> %res } -define void @scvtf_v4i32_v4f64(<4 x i32>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @scvtf_v4i32_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: scvtf_v4i32_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -1480,13 +1480,13 @@ define void @scvtf_v4i32_v4f64(<4 x i32>* %a, <4 x double>* %b) vscale_range(2,0 ; CHECK-NEXT: scvtf z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x i32>, <4 x i32>* %a + %op1 = load <4 x i32>, ptr %a %res = sitofp <4 x i32> %op1 to <4 x double> - store <4 x double> %res, <4 x double>* %b + store <4 x double> %res, ptr %b ret void } -define void @scvtf_v8i32_v8f64(<8 x i32>* %a, <8 x double>* %b) #0 { +define void @scvtf_v8i32_v8f64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: scvtf_v8i32_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.s, vl8 @@ -1511,13 +1511,13 @@ define void @scvtf_v8i32_v8f64(<8 x i32>* %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: scvtf z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a + %op1 = load <8 x i32>, ptr %a %res = sitofp <8 x i32> %op1 to <8 x double> - store <8 x double> %res, <8 x double>* %b + store <8 x double> %res, ptr %b ret void } -define void @scvtf_v16i32_v16f64(<16 x i32>* %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @scvtf_v16i32_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: scvtf_v16i32_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -1527,13 +1527,13 @@ define void @scvtf_v16i32_v16f64(<16 x i32>* %a, <16 x double>* %b) vscale_range ; CHECK-NEXT: scvtf z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %res = sitofp <16 x i32> %op1 to <16 x double> - store <16 x double> %res, <16 x double>* %b + store <16 x double> %res, ptr %b ret void } -define void @scvtf_v32i32_v32f64(<32 x i32>* %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @scvtf_v32i32_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: scvtf_v32i32_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1543,9 +1543,9 @@ define void @scvtf_v32i32_v32f64(<32 x i32>* %a, <32 x double>* %b) vscale_range ; CHECK-NEXT: scvtf z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a + %op1 = load <32 x i32>, ptr %a %res = sitofp <32 x i32> %op1 to <32 x double> - store <32 x double> %res, <32 x double>* %b + store <32 x double> %res, ptr %b ret void } @@ -1580,7 +1580,7 @@ define <2 x half> @scvtf_v2i64_v2f16(<2 x i64> %op1) vscale_range(2,0) #0 { ret <2 x half> %res } -define <4 x half> @scvtf_v4i64_v4f16(<4 x i64>* %a) vscale_range(2,0) #0 { +define <4 x half> @scvtf_v4i64_v4f16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: scvtf_v4i64_v4f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1591,12 +1591,12 @@ define <4 x half> @scvtf_v4i64_v4f16(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a + %op1 = load <4 x i64>, ptr %a %res = sitofp <4 x i64> %op1 to <4 x half> ret <4 x half> %res } -define <8 x half> @scvtf_v8i64_v8f16(<8 x i64>* %a) #0 { +define <8 x half> @scvtf_v8i64_v8f16(ptr %a) #0 { ; VBITS_GE_256-LABEL: scvtf_v8i64_v8f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1624,12 +1624,12 @@ define <8 x half> @scvtf_v8i64_v8f16(<8 x i64>* %a) #0 { ; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h ; VBITS_GE_512-NEXT: // kill: def $q0 killed $q0 killed $z0 ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %res = sitofp <8 x i64> %op1 to <8 x half> ret <8 x half> %res } -define void @scvtf_v16i64_v16f16(<16 x i64>* %a, <16 x half>* %b) vscale_range(8,0) #0 { +define void @scvtf_v16i64_v16f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: scvtf_v16i64_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1640,13 +1640,13 @@ define void @scvtf_v16i64_v16f16(<16 x i64>* %a, <16 x half>* %b) vscale_range(8 ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: st1h { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a + %op1 = load <16 x i64>, ptr %a %res = sitofp <16 x i64> %op1 to <16 x half> - store <16 x half> %res, <16 x half>* %b + store <16 x half> %res, ptr %b ret void } -define void @scvtf_v32i64_v32f16(<32 x i64>* %a, <32 x half>* %b) vscale_range(16,0) #0 { +define void @scvtf_v32i64_v32f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: scvtf_v32i64_v32f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1657,9 +1657,9 @@ define void @scvtf_v32i64_v32f16(<32 x i64>* %a, <32 x half>* %b) vscale_range(1 ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: st1h { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a + %op1 = load <32 x i64>, ptr %a %res = sitofp <32 x i64> %op1 to <32 x half> - store <32 x half> %res, <32 x half>* %b + store <32 x half> %res, ptr %b ret void } @@ -1690,7 +1690,7 @@ define <2 x float> @scvtf_v2i64_v2f32(<2 x i64> %op1) vscale_range(2,0) #0 { ret <2 x float> %res } -define <4 x float> @scvtf_v4i64_v4f32(<4 x i64>* %a) vscale_range(2,0) #0 { +define <4 x float> @scvtf_v4i64_v4f32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: scvtf_v4i64_v4f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1700,12 +1700,12 @@ define <4 x float> @scvtf_v4i64_v4f32(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a + %op1 = load <4 x i64>, ptr %a %res = sitofp <4 x i64> %op1 to <4 x float> ret <4 x float> %res } -define void @scvtf_v8i64_v8f32(<8 x i64>* %a, <8 x float>* %b) #0 { +define void @scvtf_v8i64_v8f32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: scvtf_v8i64_v8f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1733,13 +1733,13 @@ define void @scvtf_v8i64_v8f32(<8 x i64>* %a, <8 x float>* %b) #0 { ; VBITS_GE_512-NEXT: uzp1 z0.s, z0.s, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %res = sitofp <8 x i64> %op1 to <8 x float> - store <8 x float> %res, <8 x float>* %b + store <8 x float> %res, ptr %b ret void } -define void @scvtf_v16i64_v16f32(<16 x i64>* %a, <16 x float>* %b) vscale_range(8,0) #0 { +define void @scvtf_v16i64_v16f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: scvtf_v16i64_v16f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1750,13 +1750,13 @@ define void @scvtf_v16i64_v16f32(<16 x i64>* %a, <16 x float>* %b) vscale_range( ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a + %op1 = load <16 x i64>, ptr %a %res = sitofp <16 x i64> %op1 to <16 x float> - store <16 x float> %res, <16 x float>* %b + store <16 x float> %res, ptr %b ret void } -define void @scvtf_v32i64_v32f32(<32 x i64>* %a, <32 x float>* %b) vscale_range(16,0) #0 { +define void @scvtf_v32i64_v32f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: scvtf_v32i64_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1767,9 +1767,9 @@ define void @scvtf_v32i64_v32f32(<32 x i64>* %a, <32 x float>* %b) vscale_range( ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a + %op1 = load <32 x i64>, ptr %a %res = sitofp <32 x i64> %op1 to <32 x float> - store <32 x float> %res, <32 x float>* %b + store <32 x float> %res, ptr %b ret void } @@ -1799,7 +1799,7 @@ define <2 x double> @scvtf_v2i64_v2f64(<2 x i64> %op1) vscale_range(2,0) #0 { ret <2 x double> %res } -define void @scvtf_v4i64_v4f64(<4 x i64>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @scvtf_v4i64_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: scvtf_v4i64_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1807,13 +1807,13 @@ define void @scvtf_v4i64_v4f64(<4 x i64>* %a, <4 x double>* %b) vscale_range(2,0 ; CHECK-NEXT: scvtf z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a + %op1 = load <4 x i64>, ptr %a %res = sitofp <4 x i64> %op1 to <4 x double> - store <4 x double> %res, <4 x double>* %b + store <4 x double> %res, ptr %b ret void } -define void @scvtf_v8i64_v8f64(<8 x i64>* %a, <8 x double>* %b) #0 { +define void @scvtf_v8i64_v8f64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: scvtf_v8i64_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1833,13 +1833,13 @@ define void @scvtf_v8i64_v8f64(<8 x i64>* %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: scvtf z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %res = sitofp <8 x i64> %op1 to <8 x double> - store <8 x double> %res, <8 x double>* %b + store <8 x double> %res, ptr %b ret void } -define void @scvtf_v16i64_v16f64(<16 x i64>* %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @scvtf_v16i64_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: scvtf_v16i64_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1847,13 +1847,13 @@ define void @scvtf_v16i64_v16f64(<16 x i64>* %a, <16 x double>* %b) vscale_range ; CHECK-NEXT: scvtf z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a + %op1 = load <16 x i64>, ptr %a %res = sitofp <16 x i64> %op1 to <16 x double> - store <16 x double> %res, <16 x double>* %b + store <16 x double> %res, ptr %b ret void } -define void @scvtf_v32i64_v32f64(<32 x i64>* %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @scvtf_v32i64_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: scvtf_v32i64_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1861,9 +1861,9 @@ define void @scvtf_v32i64_v32f64(<32 x i64>* %a, <32 x double>* %b) vscale_range ; CHECK-NEXT: scvtf z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a + %op1 = load <32 x i64>, ptr %a %res = sitofp <32 x i64> %op1 to <32 x double> - store <32 x double> %res, <32 x double>* %b + store <32 x double> %res, ptr %b ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll index a5b725a..bfd917f 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll @@ -29,7 +29,7 @@ define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, <16 x i1> %mask) ret <16 x i8> %sel } -define void @select_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @select_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: select_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -39,15 +39,15 @@ define void @select_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %mask = icmp eq <32 x i8> %op1, %op2 %sel = select <32 x i1> %mask, <32 x i8> %op1, <32 x i8> %op2 - store <32 x i8> %sel, <32 x i8>* %a + store <32 x i8> %sel, ptr %a ret void } -define void @select_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @select_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: select_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -73,15 +73,15 @@ define void @select_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: sel z0.b, p1, z0.b, z1.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %mask = icmp eq <64 x i8> %op1, %op2 %sel = select <64 x i1> %mask, <64 x i8> %op1, <64 x i8> %op2 - store <64 x i8> %sel, <64 x i8>* %a + store <64 x i8> %sel, ptr %a ret void } -define void @select_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @select_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: select_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -91,15 +91,15 @@ define void @select_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 ; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %mask = icmp eq <128 x i8> %op1, %op2 %sel = select <128 x i1> %mask, <128 x i8> %op1, <128 x i8> %op2 - store <128 x i8> %sel, <128 x i8>* %a + store <128 x i8> %sel, ptr %a ret void } -define void @select_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @select_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: select_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -109,11 +109,11 @@ define void @select_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 ; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %mask = icmp eq <256 x i8> %op1, %op2 %sel = select <256 x i1> %mask, <256 x i8> %op1, <256 x i8> %op2 - store <256 x i8> %sel, <256 x i8>* %a + store <256 x i8> %sel, ptr %a ret void } @@ -142,7 +142,7 @@ define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, <8 x i1> %mask) v ret <8 x i16> %sel } -define void @select_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @select_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: select_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -152,15 +152,15 @@ define void @select_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 ; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %mask = icmp eq <16 x i16> %op1, %op2 %sel = select <16 x i1> %mask, <16 x i16> %op1, <16 x i16> %op2 - store <16 x i16> %sel, <16 x i16>* %a + store <16 x i16> %sel, ptr %a ret void } -define void @select_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @select_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: select_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -186,15 +186,15 @@ define void @select_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: sel z0.h, p1, z0.h, z1.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %mask = icmp eq <32 x i16> %op1, %op2 %sel = select <32 x i1> %mask, <32 x i16> %op1, <32 x i16> %op2 - store <32 x i16> %sel, <32 x i16>* %a + store <32 x i16> %sel, ptr %a ret void } -define void @select_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @select_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: select_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -204,15 +204,15 @@ define void @select_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 ; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %mask = icmp eq <64 x i16> %op1, %op2 %sel = select <64 x i1> %mask, <64 x i16> %op1, <64 x i16> %op2 - store <64 x i16> %sel, <64 x i16>* %a + store <64 x i16> %sel, ptr %a ret void } -define void @select_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @select_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: select_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -222,11 +222,11 @@ define void @select_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) ; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %mask = icmp eq <128 x i16> %op1, %op2 %sel = select <128 x i1> %mask, <128 x i16> %op1, <128 x i16> %op2 - store <128 x i16> %sel, <128 x i16>* %a + store <128 x i16> %sel, ptr %a ret void } @@ -255,7 +255,7 @@ define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask) v ret <4 x i32> %sel } -define void @select_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @select_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: select_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -265,15 +265,15 @@ define void @select_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %mask = icmp eq <8 x i32> %op1, %op2 %sel = select <8 x i1> %mask, <8 x i32> %op1, <8 x i32> %op2 - store <8 x i32> %sel, <8 x i32>* %a + store <8 x i32> %sel, ptr %a ret void } -define void @select_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @select_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: select_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -299,15 +299,15 @@ define void @select_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: sel z0.s, p1, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %mask = icmp eq <16 x i32> %op1, %op2 %sel = select <16 x i1> %mask, <16 x i32> %op1, <16 x i32> %op2 - store <16 x i32> %sel, <16 x i32>* %a + store <16 x i32> %sel, ptr %a ret void } -define void @select_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @select_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: select_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -317,15 +317,15 @@ define void @select_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 ; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %mask = icmp eq <32 x i32> %op1, %op2 %sel = select <32 x i1> %mask, <32 x i32> %op1, <32 x i32> %op2 - store <32 x i32> %sel, <32 x i32>* %a + store <32 x i32> %sel, ptr %a ret void } -define void @select_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @select_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: select_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -335,11 +335,11 @@ define void @select_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 ; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %mask = icmp eq <64 x i32> %op1, %op2 %sel = select <64 x i1> %mask, <64 x i32> %op1, <64 x i32> %op2 - store <64 x i32> %sel, <64 x i32>* %a + store <64 x i32> %sel, ptr %a ret void } @@ -369,7 +369,7 @@ define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask) v ret <2 x i64> %sel } -define void @select_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @select_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: select_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -379,15 +379,15 @@ define void @select_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %mask = icmp eq <4 x i64> %op1, %op2 %sel = select <4 x i1> %mask, <4 x i64> %op1, <4 x i64> %op2 - store <4 x i64> %sel, <4 x i64>* %a + store <4 x i64> %sel, ptr %a ret void } -define void @select_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @select_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: select_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -413,15 +413,15 @@ define void @select_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: sel z0.d, p1, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %mask = icmp eq <8 x i64> %op1, %op2 %sel = select <8 x i1> %mask, <8 x i64> %op1, <8 x i64> %op2 - store <8 x i64> %sel, <8 x i64>* %a + store <8 x i64> %sel, ptr %a ret void } -define void @select_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @select_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: select_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -431,15 +431,15 @@ define void @select_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 ; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %mask = icmp eq <16 x i64> %op1, %op2 %sel = select <16 x i1> %mask, <16 x i64> %op1, <16 x i64> %op2 - store <16 x i64> %sel, <16 x i64>* %a + store <16 x i64> %sel, ptr %a ret void } -define void @select_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @select_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: select_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -449,11 +449,11 @@ define void @select_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 ; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %mask = icmp eq <32 x i64> %op1, %op2 %sel = select <32 x i1> %mask, <32 x i64> %op1, <32 x i64> %op2 - store <32 x i64> %sel, <32 x i64>* %a + store <32 x i64> %sel, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-limit-duplane.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-limit-duplane.ll index 38bf194..88a0b06 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-limit-duplane.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-limit-duplane.ll @@ -3,7 +3,7 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64-unknown-linux-gnu" -define <4 x i32> @test(<16 x i32>* %arg1, <16 x i32>* %arg2) { +define <4 x i32> @test(ptr %arg1, ptr %arg2) { ; CHECK-LABEL: test: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: mov x8, #8 @@ -19,15 +19,15 @@ define <4 x i32> @test(<16 x i32>* %arg1, <16 x i32>* %arg2) { ; CHECK-NEXT: st1w { z2.s }, p0, [x0] ; CHECK-NEXT: ret entry: - %0 = load <16 x i32>, <16 x i32>* %arg1, align 256 - %1 = load <16 x i32>, <16 x i32>* %arg2, align 256 + %0 = load <16 x i32>, ptr %arg1, align 256 + %1 = load <16 x i32>, ptr %arg2, align 256 %shvec = shufflevector <16 x i32> %0, <16 x i32> %1, <4 x i32> %2 = add <16 x i32> %0, %0 - store <16 x i32> %2, <16 x i32>* %arg1, align 256 + store <16 x i32> %2, ptr %arg1, align 256 ret <4 x i32> %shvec } -define <2 x i32> @test2(<16 x i32>* %arg1, <16 x i32>* %arg2) { +define <2 x i32> @test2(ptr %arg1, ptr %arg2) { ; CHECK-LABEL: test2: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: mov x8, #8 @@ -43,10 +43,10 @@ define <2 x i32> @test2(<16 x i32>* %arg1, <16 x i32>* %arg2) { ; CHECK-NEXT: st1w { z2.s }, p0, [x0] ; CHECK-NEXT: ret entry: - %0 = load <16 x i32>, <16 x i32>* %arg1, align 256 - %1 = load <16 x i32>, <16 x i32>* %arg2, align 256 + %0 = load <16 x i32>, ptr %arg1, align 256 + %1 = load <16 x i32>, ptr %arg2, align 256 %shvec = shufflevector <16 x i32> %0, <16 x i32> %1, <2 x i32> %2 = add <16 x i32> %0, %0 - store <16 x i32> %2, <16 x i32>* %arg1, align 256 + store <16 x i32> %2, ptr %arg1, align 256 ret <2 x i32> %shvec } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-loads.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-loads.ll index 485df06..9771bdf 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-loads.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-loads.ll @@ -19,37 +19,37 @@ target triple = "aarch64-unknown-linux-gnu" ; Don't use SVE for 64-bit vectors. -define <2 x float> @load_v2f32(<2 x float>* %a) #0 { +define <2 x float> @load_v2f32(ptr %a) #0 { ; CHECK-LABEL: load_v2f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ret - %load = load <2 x float>, <2 x float>* %a + %load = load <2 x float>, ptr %a ret <2 x float> %load } ; Don't use SVE for 128-bit vectors. -define <4 x float> @load_v4f32(<4 x float>* %a) #0 { +define <4 x float> @load_v4f32(ptr %a) #0 { ; CHECK-LABEL: load_v4f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ret - %load = load <4 x float>, <4 x float>* %a + %load = load <4 x float>, ptr %a ret <4 x float> %load } -define <8 x float> @load_v8f32(<8 x float>* %a) #0 { +define <8 x float> @load_v8f32(ptr %a) #0 { ; CHECK-LABEL: load_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x8] ; CHECK-NEXT: ret - %load = load <8 x float>, <8 x float>* %a + %load = load <8 x float>, ptr %a ret <8 x float> %load } -define <16 x float> @load_v16f32(<16 x float>* %a) #0 { +define <16 x float> @load_v16f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: load_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #8 @@ -80,11 +80,11 @@ define <16 x float> @load_v16f32(<16 x float>* %a) #0 { ; VBITS_GE_2048-NEXT: ld1w { z0.s }, p0/z, [x0] ; VBITS_GE_2048-NEXT: st1w { z0.s }, p0, [x8] ; VBITS_GE_2048-NEXT: ret - %load = load <16 x float>, <16 x float>* %a + %load = load <16 x float>, ptr %a ret <16 x float> %load } -define <32 x float> @load_v32f32(<32 x float>* %a) #0 { +define <32 x float> @load_v32f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: load_v32f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #16 @@ -124,11 +124,11 @@ define <32 x float> @load_v32f32(<32 x float>* %a) #0 { ; VBITS_GE_2048-NEXT: ld1w { z0.s }, p0/z, [x0] ; VBITS_GE_2048-NEXT: st1w { z0.s }, p0, [x8] ; VBITS_GE_2048-NEXT: ret - %load = load <32 x float>, <32 x float>* %a + %load = load <32 x float>, ptr %a ret <32 x float> %load } -define <64 x float> @load_v64f32(<64 x float>* %a) #0 { +define <64 x float> @load_v64f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: load_v64f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #8 @@ -189,7 +189,7 @@ define <64 x float> @load_v64f32(<64 x float>* %a) #0 { ; VBITS_GE_2048-NEXT: ld1w { z0.s }, p0/z, [x0] ; VBITS_GE_2048-NEXT: st1w { z0.s }, p0, [x8] ; VBITS_GE_2048-NEXT: ret - %load = load <64 x float>, <64 x float>* %a + %load = load <64 x float>, ptr %a ret <64 x float> %load } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll index 743aa29..ed9b73c 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll @@ -35,7 +35,7 @@ define i8 @andv_v16i8(<16 x i8> %a) vscale_range(2,0) #0 { ret i8 %res } -define i8 @andv_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { +define i8 @andv_v32i8(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: andv_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -43,12 +43,12 @@ define i8 @andv_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: andv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <32 x i8>, <32 x i8>* %a + %op = load <32 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %op) ret i8 %res } -define i8 @andv_v64i8(<64 x i8>* %a) #0 { +define i8 @andv_v64i8(ptr %a) #0 { ; VBITS_GE_256-LABEL: andv_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -67,12 +67,12 @@ define i8 @andv_v64i8(<64 x i8>* %a) #0 { ; VBITS_GE_512-NEXT: andv b0, p0, z0.b ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <64 x i8>, <64 x i8>* %a + %op = load <64 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.and.v64i8(<64 x i8> %op) ret i8 %res } -define i8 @andv_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { +define i8 @andv_v128i8(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: andv_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -80,12 +80,12 @@ define i8 @andv_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: andv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <128 x i8>, <128 x i8>* %a + %op = load <128 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.and.v128i8(<128 x i8> %op) ret i8 %res } -define i8 @andv_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { +define i8 @andv_v256i8(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: andv_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -93,7 +93,7 @@ define i8 @andv_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: andv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <256 x i8>, <256 x i8>* %a + %op = load <256 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.and.v256i8(<256 x i8> %op) ret i8 %res } @@ -124,7 +124,7 @@ define i16 @andv_v8i16(<8 x i16> %a) vscale_range(2,0) #0 { ret i16 %res } -define i16 @andv_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { +define i16 @andv_v16i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: andv_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -132,12 +132,12 @@ define i16 @andv_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: andv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <16 x i16>, <16 x i16>* %a + %op = load <16 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %op) ret i16 %res } -define i16 @andv_v32i16(<32 x i16>* %a) #0 { +define i16 @andv_v32i16(ptr %a) #0 { ; VBITS_GE_256-LABEL: andv_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -156,12 +156,12 @@ define i16 @andv_v32i16(<32 x i16>* %a) #0 { ; VBITS_GE_512-NEXT: andv h0, p0, z0.h ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <32 x i16>, <32 x i16>* %a + %op = load <32 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.and.v32i16(<32 x i16> %op) ret i16 %res } -define i16 @andv_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { +define i16 @andv_v64i16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: andv_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -169,12 +169,12 @@ define i16 @andv_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: andv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <64 x i16>, <64 x i16>* %a + %op = load <64 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.and.v64i16(<64 x i16> %op) ret i16 %res } -define i16 @andv_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { +define i16 @andv_v128i16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: andv_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -182,7 +182,7 @@ define i16 @andv_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: andv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <128 x i16>, <128 x i16>* %a + %op = load <128 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.and.v128i16(<128 x i16> %op) ret i16 %res } @@ -213,7 +213,7 @@ define i32 @andv_v4i32(<4 x i32> %a) vscale_range(2,0) #0 { ret i32 %res } -define i32 @andv_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { +define i32 @andv_v8i32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: andv_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -221,12 +221,12 @@ define i32 @andv_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: andv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <8 x i32>, <8 x i32>* %a + %op = load <8 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %op) ret i32 %res } -define i32 @andv_v16i32(<16 x i32>* %a) #0 { +define i32 @andv_v16i32(ptr %a) #0 { ; VBITS_GE_256-LABEL: andv_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -245,12 +245,12 @@ define i32 @andv_v16i32(<16 x i32>* %a) #0 { ; VBITS_GE_512-NEXT: andv s0, p0, z0.s ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <16 x i32>, <16 x i32>* %a + %op = load <16 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %op) ret i32 %res } -define i32 @andv_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { +define i32 @andv_v32i32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: andv_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -258,12 +258,12 @@ define i32 @andv_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: andv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <32 x i32>, <32 x i32>* %a + %op = load <32 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.and.v32i32(<32 x i32> %op) ret i32 %res } -define i32 @andv_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { +define i32 @andv_v64i32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: andv_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -271,7 +271,7 @@ define i32 @andv_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: andv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <64 x i32>, <64 x i32>* %a + %op = load <64 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.and.v64i32(<64 x i32> %op) ret i32 %res } @@ -300,7 +300,7 @@ define i64 @andv_v2i64(<2 x i64> %a) vscale_range(2,0) #0 { ret i64 %res } -define i64 @andv_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { +define i64 @andv_v4i64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: andv_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -308,12 +308,12 @@ define i64 @andv_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: andv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <4 x i64>, <4 x i64>* %a + %op = load <4 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %op) ret i64 %res } -define i64 @andv_v8i64(<8 x i64>* %a) #0 { +define i64 @andv_v8i64(ptr %a) #0 { ; VBITS_GE_256-LABEL: andv_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -332,12 +332,12 @@ define i64 @andv_v8i64(<8 x i64>* %a) #0 { ; VBITS_GE_512-NEXT: andv d0, p0, z0.d ; VBITS_GE_512-NEXT: fmov x0, d0 ; VBITS_GE_512-NEXT: ret - %op = load <8 x i64>, <8 x i64>* %a + %op = load <8 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %op) ret i64 %res } -define i64 @andv_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { +define i64 @andv_v16i64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: andv_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -345,12 +345,12 @@ define i64 @andv_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: andv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <16 x i64>, <16 x i64>* %a + %op = load <16 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.and.v16i64(<16 x i64> %op) ret i64 %res } -define i64 @andv_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { +define i64 @andv_v32i64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: andv_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -358,7 +358,7 @@ define i64 @andv_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: andv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <32 x i64>, <32 x i64>* %a + %op = load <32 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.and.v32i64(<32 x i64> %op) ret i64 %res } @@ -393,7 +393,7 @@ define i8 @eorv_v16i8(<16 x i8> %a) vscale_range(2,0) #0 { ret i8 %res } -define i8 @eorv_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { +define i8 @eorv_v32i8(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: eorv_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -401,12 +401,12 @@ define i8 @eorv_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: eorv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <32 x i8>, <32 x i8>* %a + %op = load <32 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %op) ret i8 %res } -define i8 @eorv_v64i8(<64 x i8>* %a) #0 { +define i8 @eorv_v64i8(ptr %a) #0 { ; VBITS_GE_256-LABEL: eorv_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -425,12 +425,12 @@ define i8 @eorv_v64i8(<64 x i8>* %a) #0 { ; VBITS_GE_512-NEXT: eorv b0, p0, z0.b ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <64 x i8>, <64 x i8>* %a + %op = load <64 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.xor.v64i8(<64 x i8> %op) ret i8 %res } -define i8 @eorv_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { +define i8 @eorv_v128i8(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: eorv_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -438,12 +438,12 @@ define i8 @eorv_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: eorv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <128 x i8>, <128 x i8>* %a + %op = load <128 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> %op) ret i8 %res } -define i8 @eorv_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { +define i8 @eorv_v256i8(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: eorv_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -451,7 +451,7 @@ define i8 @eorv_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: eorv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <256 x i8>, <256 x i8>* %a + %op = load <256 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.xor.v256i8(<256 x i8> %op) ret i8 %res } @@ -482,7 +482,7 @@ define i16 @eorv_v8i16(<8 x i16> %a) vscale_range(2,0) #0 { ret i16 %res } -define i16 @eorv_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { +define i16 @eorv_v16i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: eorv_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -490,12 +490,12 @@ define i16 @eorv_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: eorv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <16 x i16>, <16 x i16>* %a + %op = load <16 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %op) ret i16 %res } -define i16 @eorv_v32i16(<32 x i16>* %a) #0 { +define i16 @eorv_v32i16(ptr %a) #0 { ; VBITS_GE_256-LABEL: eorv_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -514,12 +514,12 @@ define i16 @eorv_v32i16(<32 x i16>* %a) #0 { ; VBITS_GE_512-NEXT: eorv h0, p0, z0.h ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <32 x i16>, <32 x i16>* %a + %op = load <32 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.xor.v32i16(<32 x i16> %op) ret i16 %res } -define i16 @eorv_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { +define i16 @eorv_v64i16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: eorv_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -527,12 +527,12 @@ define i16 @eorv_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: eorv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <64 x i16>, <64 x i16>* %a + %op = load <64 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.xor.v64i16(<64 x i16> %op) ret i16 %res } -define i16 @eorv_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { +define i16 @eorv_v128i16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: eorv_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -540,7 +540,7 @@ define i16 @eorv_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: eorv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <128 x i16>, <128 x i16>* %a + %op = load <128 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.xor.v128i16(<128 x i16> %op) ret i16 %res } @@ -571,7 +571,7 @@ define i32 @eorv_v4i32(<4 x i32> %a) vscale_range(2,0) #0 { ret i32 %res } -define i32 @eorv_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { +define i32 @eorv_v8i32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: eorv_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -579,12 +579,12 @@ define i32 @eorv_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: eorv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <8 x i32>, <8 x i32>* %a + %op = load <8 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %op) ret i32 %res } -define i32 @eorv_v16i32(<16 x i32>* %a) #0 { +define i32 @eorv_v16i32(ptr %a) #0 { ; VBITS_GE_256-LABEL: eorv_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -603,12 +603,12 @@ define i32 @eorv_v16i32(<16 x i32>* %a) #0 { ; VBITS_GE_512-NEXT: eorv s0, p0, z0.s ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <16 x i32>, <16 x i32>* %a + %op = load <16 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> %op) ret i32 %res } -define i32 @eorv_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { +define i32 @eorv_v32i32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: eorv_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -616,12 +616,12 @@ define i32 @eorv_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: eorv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <32 x i32>, <32 x i32>* %a + %op = load <32 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.xor.v32i32(<32 x i32> %op) ret i32 %res } -define i32 @eorv_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { +define i32 @eorv_v64i32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: eorv_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -629,7 +629,7 @@ define i32 @eorv_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: eorv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <64 x i32>, <64 x i32>* %a + %op = load <64 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.xor.v64i32(<64 x i32> %op) ret i32 %res } @@ -658,7 +658,7 @@ define i64 @eorv_v2i64(<2 x i64> %a) vscale_range(2,0) #0 { ret i64 %res } -define i64 @eorv_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { +define i64 @eorv_v4i64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: eorv_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -666,12 +666,12 @@ define i64 @eorv_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: eorv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <4 x i64>, <4 x i64>* %a + %op = load <4 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %op) ret i64 %res } -define i64 @eorv_v8i64(<8 x i64>* %a) #0 { +define i64 @eorv_v8i64(ptr %a) #0 { ; VBITS_GE_256-LABEL: eorv_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -690,12 +690,12 @@ define i64 @eorv_v8i64(<8 x i64>* %a) #0 { ; VBITS_GE_512-NEXT: eorv d0, p0, z0.d ; VBITS_GE_512-NEXT: fmov x0, d0 ; VBITS_GE_512-NEXT: ret - %op = load <8 x i64>, <8 x i64>* %a + %op = load <8 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %op) ret i64 %res } -define i64 @eorv_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { +define i64 @eorv_v16i64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: eorv_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -703,12 +703,12 @@ define i64 @eorv_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: eorv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <16 x i64>, <16 x i64>* %a + %op = load <16 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.xor.v16i64(<16 x i64> %op) ret i64 %res } -define i64 @eorv_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { +define i64 @eorv_v32i64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: eorv_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -716,7 +716,7 @@ define i64 @eorv_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: eorv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <32 x i64>, <32 x i64>* %a + %op = load <32 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.xor.v32i64(<32 x i64> %op) ret i64 %res } @@ -751,7 +751,7 @@ define i8 @orv_v16i8(<16 x i8> %a) vscale_range(2,0) #0 { ret i8 %res } -define i8 @orv_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { +define i8 @orv_v32i8(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: orv_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -759,12 +759,12 @@ define i8 @orv_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: orv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <32 x i8>, <32 x i8>* %a + %op = load <32 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %op) ret i8 %res } -define i8 @orv_v64i8(<64 x i8>* %a) #0 { +define i8 @orv_v64i8(ptr %a) #0 { ; VBITS_GE_256-LABEL: orv_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -783,12 +783,12 @@ define i8 @orv_v64i8(<64 x i8>* %a) #0 { ; VBITS_GE_512-NEXT: orv b0, p0, z0.b ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <64 x i8>, <64 x i8>* %a + %op = load <64 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.or.v64i8(<64 x i8> %op) ret i8 %res } -define i8 @orv_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { +define i8 @orv_v128i8(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: orv_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -796,12 +796,12 @@ define i8 @orv_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: orv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <128 x i8>, <128 x i8>* %a + %op = load <128 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.or.v128i8(<128 x i8> %op) ret i8 %res } -define i8 @orv_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { +define i8 @orv_v256i8(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: orv_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -809,7 +809,7 @@ define i8 @orv_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: orv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <256 x i8>, <256 x i8>* %a + %op = load <256 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.or.v256i8(<256 x i8> %op) ret i8 %res } @@ -840,7 +840,7 @@ define i16 @orv_v8i16(<8 x i16> %a) vscale_range(2,0) #0 { ret i16 %res } -define i16 @orv_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { +define i16 @orv_v16i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: orv_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -848,12 +848,12 @@ define i16 @orv_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: orv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <16 x i16>, <16 x i16>* %a + %op = load <16 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %op) ret i16 %res } -define i16 @orv_v32i16(<32 x i16>* %a) #0 { +define i16 @orv_v32i16(ptr %a) #0 { ; VBITS_GE_256-LABEL: orv_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -872,12 +872,12 @@ define i16 @orv_v32i16(<32 x i16>* %a) #0 { ; VBITS_GE_512-NEXT: orv h0, p0, z0.h ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <32 x i16>, <32 x i16>* %a + %op = load <32 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.or.v32i16(<32 x i16> %op) ret i16 %res } -define i16 @orv_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { +define i16 @orv_v64i16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: orv_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -885,12 +885,12 @@ define i16 @orv_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: orv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <64 x i16>, <64 x i16>* %a + %op = load <64 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.or.v64i16(<64 x i16> %op) ret i16 %res } -define i16 @orv_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { +define i16 @orv_v128i16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: orv_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -898,7 +898,7 @@ define i16 @orv_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: orv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <128 x i16>, <128 x i16>* %a + %op = load <128 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.or.v128i16(<128 x i16> %op) ret i16 %res } @@ -929,7 +929,7 @@ define i32 @orv_v4i32(<4 x i32> %a) vscale_range(2,0) #0 { ret i32 %res } -define i32 @orv_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { +define i32 @orv_v8i32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: orv_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -937,12 +937,12 @@ define i32 @orv_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: orv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <8 x i32>, <8 x i32>* %a + %op = load <8 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %op) ret i32 %res } -define i32 @orv_v16i32(<16 x i32>* %a) #0 { +define i32 @orv_v16i32(ptr %a) #0 { ; VBITS_GE_256-LABEL: orv_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -961,12 +961,12 @@ define i32 @orv_v16i32(<16 x i32>* %a) #0 { ; VBITS_GE_512-NEXT: orv s0, p0, z0.s ; VBITS_GE_512-NEXT: fmov w0, s0 ; VBITS_GE_512-NEXT: ret - %op = load <16 x i32>, <16 x i32>* %a + %op = load <16 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %op) ret i32 %res } -define i32 @orv_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { +define i32 @orv_v32i32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: orv_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -974,12 +974,12 @@ define i32 @orv_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: orv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <32 x i32>, <32 x i32>* %a + %op = load <32 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.or.v32i32(<32 x i32> %op) ret i32 %res } -define i32 @orv_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { +define i32 @orv_v64i32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: orv_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -987,7 +987,7 @@ define i32 @orv_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: orv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %op = load <64 x i32>, <64 x i32>* %a + %op = load <64 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.or.v64i32(<64 x i32> %op) ret i32 %res } @@ -1016,7 +1016,7 @@ define i64 @orv_v2i64(<2 x i64> %a) vscale_range(2,0) #0 { ret i64 %res } -define i64 @orv_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { +define i64 @orv_v4i64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: orv_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -1024,12 +1024,12 @@ define i64 @orv_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: orv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <4 x i64>, <4 x i64>* %a + %op = load <4 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %op) ret i64 %res } -define i64 @orv_v8i64(<8 x i64>* %a) #0 { +define i64 @orv_v8i64(ptr %a) #0 { ; VBITS_GE_256-LABEL: orv_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -1048,12 +1048,12 @@ define i64 @orv_v8i64(<8 x i64>* %a) #0 { ; VBITS_GE_512-NEXT: orv d0, p0, z0.d ; VBITS_GE_512-NEXT: fmov x0, d0 ; VBITS_GE_512-NEXT: ret - %op = load <8 x i64>, <8 x i64>* %a + %op = load <8 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %op) ret i64 %res } -define i64 @orv_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { +define i64 @orv_v16i64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: orv_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -1061,12 +1061,12 @@ define i64 @orv_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: orv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <16 x i64>, <16 x i64>* %a + %op = load <16 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> %op) ret i64 %res } -define i64 @orv_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { +define i64 @orv_v32i64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: orv_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1074,7 +1074,7 @@ define i64 @orv_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: orv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %op = load <32 x i64>, <32 x i64>* %a + %op = load <32 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.or.v32i64(<32 x i64> %op) ret i64 %res } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-mask-opt.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-mask-opt.ll index 6007ccf..deafa73 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-mask-opt.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-mask-opt.ll @@ -9,7 +9,7 @@ target triple = "aarch64-unknown-linux-gnu" ; LD1B ; -define void @masked_gather_v2i8(<2 x i8>* %a, <2 x i8*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v2i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v2i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x1] @@ -19,13 +19,13 @@ define void @masked_gather_v2i8(<2 x i8>* %a, <2 x i8*>* %b) vscale_range(2,0) # ; CHECK-NEXT: xtn v0.2s, v0.2d ; CHECK-NEXT: st1b { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %ptrs = load <2 x i8*>, <2 x i8*>* %b - %vals = call <2 x i8> @llvm.masked.gather.v2i8(<2 x i8*> %ptrs, i32 8, <2 x i1> , <2 x i8> undef) - store <2 x i8> %vals, <2 x i8>* %a + %ptrs = load <2 x ptr>, ptr %b + %vals = call <2 x i8> @llvm.masked.gather.v2i8(<2 x ptr> %ptrs, i32 8, <2 x i1> , <2 x i8> undef) + store <2 x i8> %vals, ptr %a ret void } -define void @masked_gather_v4i8(<4 x i8>* %a, <4 x i8*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v4i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v4i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -33,13 +33,13 @@ define void @masked_gather_v4i8(<4 x i8>* %a, <4 x i8*>* %b) vscale_range(2,0) # ; CHECK-NEXT: ld1b { z0.d }, p0/z, [z0.d] ; CHECK-NEXT: st1b { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %ptrs = load <4 x i8*>, <4 x i8*>* %b - %vals = call <4 x i8> @llvm.masked.gather.v4i8(<4 x i8*> %ptrs, i32 8, <4 x i1> , <4 x i8> undef) - store <4 x i8> %vals, <4 x i8>* %a + %ptrs = load <4 x ptr>, ptr %b + %vals = call <4 x i8> @llvm.masked.gather.v4i8(<4 x ptr> %ptrs, i32 8, <4 x i1> , <4 x i8> undef) + store <4 x i8> %vals, ptr %a ret void } -define void @masked_gather_v8i8(<8 x i8>* %a, <8 x i8*>* %b) #0 { +define void @masked_gather_v8i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: masked_gather_v8i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -66,13 +66,13 @@ define void @masked_gather_v8i8(<8 x i8>* %a, <8 x i8*>* %b) #0 { ; VBITS_GE_512-NEXT: uzp1 z0.b, z0.b, z0.b ; VBITS_GE_512-NEXT: str d0, [x0] ; VBITS_GE_512-NEXT: ret - %ptrs = load <8 x i8*>, <8 x i8*>* %b - %vals = call <8 x i8> @llvm.masked.gather.v8i8(<8 x i8*> %ptrs, i32 8, <8 x i1> , <8 x i8> undef) - store <8 x i8> %vals, <8 x i8>* %a + %ptrs = load <8 x ptr>, ptr %b + %vals = call <8 x i8> @llvm.masked.gather.v8i8(<8 x ptr> %ptrs, i32 8, <8 x i1> , <8 x i8> undef) + store <8 x i8> %vals, ptr %a ret void } -define void @masked_gather_v16i8(<16 x i8>* %a, <16 x i8*>* %b) vscale_range(8,0) #0 { +define void @masked_gather_v16i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_gather_v16i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -83,14 +83,14 @@ define void @masked_gather_v16i8(<16 x i8>* %a, <16 x i8*>* %b) vscale_range(8,0 ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %ptrs = load <16 x i8*>, <16 x i8*>* %b - %vals = call <16 x i8> @llvm.masked.gather.v16i8(<16 x i8*> %ptrs, i32 8, <16 x i1> , ptr %b + %vals = call <16 x i8> @llvm.masked.gather.v16i8(<16 x ptr> %ptrs, i32 8, <16 x i1> , <16 x i8> undef) - store <16 x i8> %vals, <16 x i8>* %a + store <16 x i8> %vals, ptr %a ret void } -define void @masked_gather_v32i8(<32 x i8>* %a, <32 x i8*>* %b) vscale_range(16,0) #0 { +define void @masked_gather_v32i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_gather_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -98,12 +98,12 @@ define void @masked_gather_v32i8(<32 x i8>* %a, <32 x i8*>* %b) vscale_range(16, ; CHECK-NEXT: ld1b { z0.d }, p0/z, [z0.d] ; CHECK-NEXT: st1b { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %ptrs = load <32 x i8*>, <32 x i8*>* %b - %vals = call <32 x i8> @llvm.masked.gather.v32i8(<32 x i8*> %ptrs, i32 8, <32 x i1> , ptr %b + %vals = call <32 x i8> @llvm.masked.gather.v32i8(<32 x ptr> %ptrs, i32 8, <32 x i1> , <32 x i8> undef) - store <32 x i8> %vals, <32 x i8>* %a + store <32 x i8> %vals, ptr %a ret void } @@ -111,7 +111,7 @@ define void @masked_gather_v32i8(<32 x i8>* %a, <32 x i8*>* %b) vscale_range(16, ; LD1H ; -define void @masked_gather_v2i16(<2 x i16>* %a, <2 x i16*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v2i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v2i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x1] @@ -121,13 +121,13 @@ define void @masked_gather_v2i16(<2 x i16>* %a, <2 x i16*>* %b) vscale_range(2,0 ; CHECK-NEXT: xtn v0.2s, v0.2d ; CHECK-NEXT: st1h { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %ptrs = load <2 x i16*>, <2 x i16*>* %b - %vals = call <2 x i16> @llvm.masked.gather.v2i16(<2 x i16*> %ptrs, i32 8, <2 x i1> , <2 x i16> undef) - store <2 x i16> %vals, <2 x i16>* %a + %ptrs = load <2 x ptr>, ptr %b + %vals = call <2 x i16> @llvm.masked.gather.v2i16(<2 x ptr> %ptrs, i32 8, <2 x i1> , <2 x i16> undef) + store <2 x i16> %vals, ptr %a ret void } -define void @masked_gather_v4i16(<4 x i16>* %a, <4 x i16*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v4i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v4i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -137,13 +137,13 @@ define void @masked_gather_v4i16(<4 x i16>* %a, <4 x i16*>* %b) vscale_range(2,0 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret - %ptrs = load <4 x i16*>, <4 x i16*>* %b - %vals = call <4 x i16> @llvm.masked.gather.v4i16(<4 x i16*> %ptrs, i32 8, <4 x i1> , <4 x i16> undef) - store <4 x i16> %vals, <4 x i16>* %a + %ptrs = load <4 x ptr>, ptr %b + %vals = call <4 x i16> @llvm.masked.gather.v4i16(<4 x ptr> %ptrs, i32 8, <4 x i1> , <4 x i16> undef) + store <4 x i16> %vals, ptr %a ret void } -define void @masked_gather_v8i16(<8 x i16>* %a, <8 x i16*>* %b) #0 { +define void @masked_gather_v8i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: masked_gather_v8i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -169,13 +169,13 @@ define void @masked_gather_v8i16(<8 x i16>* %a, <8 x i16*>* %b) #0 { ; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h ; VBITS_GE_512-NEXT: str q0, [x0] ; VBITS_GE_512-NEXT: ret - %ptrs = load <8 x i16*>, <8 x i16*>* %b - %vals = call <8 x i16> @llvm.masked.gather.v8i16(<8 x i16*> %ptrs, i32 8, <8 x i1> , <8 x i16> undef) - store <8 x i16> %vals, <8 x i16>* %a + %ptrs = load <8 x ptr>, ptr %b + %vals = call <8 x i16> @llvm.masked.gather.v8i16(<8 x ptr> %ptrs, i32 8, <8 x i1> , <8 x i16> undef) + store <8 x i16> %vals, ptr %a ret void } -define void @masked_gather_v16i16(<16 x i16>* %a, <16 x i16*>* %b) vscale_range(8,0) #0 { +define void @masked_gather_v16i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_gather_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -183,14 +183,14 @@ define void @masked_gather_v16i16(<16 x i16>* %a, <16 x i16*>* %b) vscale_range( ; CHECK-NEXT: ld1h { z0.d }, p0/z, [z0.d] ; CHECK-NEXT: st1h { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %ptrs = load <16 x i16*>, <16 x i16*>* %b - %vals = call <16 x i16> @llvm.masked.gather.v16i16(<16 x i16*> %ptrs, i32 8, <16 x i1> , ptr %b + %vals = call <16 x i16> @llvm.masked.gather.v16i16(<16 x ptr> %ptrs, i32 8, <16 x i1> , <16 x i16> undef) - store <16 x i16> %vals, <16 x i16>* %a + store <16 x i16> %vals, ptr %a ret void } -define void @masked_gather_v32i16(<32 x i16>* %a, <32 x i16*>* %b) vscale_range(16,0) #0 { +define void @masked_gather_v32i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_gather_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -198,12 +198,12 @@ define void @masked_gather_v32i16(<32 x i16>* %a, <32 x i16*>* %b) vscale_range( ; CHECK-NEXT: ld1h { z0.d }, p0/z, [z0.d] ; CHECK-NEXT: st1h { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %ptrs = load <32 x i16*>, <32 x i16*>* %b - %vals = call <32 x i16> @llvm.masked.gather.v32i16(<32 x i16*> %ptrs, i32 8, <32 x i1> , ptr %b + %vals = call <32 x i16> @llvm.masked.gather.v32i16(<32 x ptr> %ptrs, i32 8, <32 x i1> , <32 x i16> undef) - store <32 x i16> %vals, <32 x i16>* %a + store <32 x i16> %vals, ptr %a ret void } @@ -211,7 +211,7 @@ define void @masked_gather_v32i16(<32 x i16>* %a, <32 x i16*>* %b) vscale_range( ; LD1W ; -define void @masked_gather_v2i32(<2 x i32>* %a, <2 x i32*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v2i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v2i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x1] @@ -220,13 +220,13 @@ define void @masked_gather_v2i32(<2 x i32>* %a, <2 x i32*>* %b) vscale_range(2,0 ; CHECK-NEXT: xtn v0.2s, v0.2d ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret - %ptrs = load <2 x i32*>, <2 x i32*>* %b - %vals = call <2 x i32> @llvm.masked.gather.v2i32(<2 x i32*> %ptrs, i32 8, <2 x i1> , <2 x i32> undef) - store <2 x i32> %vals, <2 x i32>* %a + %ptrs = load <2 x ptr>, ptr %b + %vals = call <2 x i32> @llvm.masked.gather.v2i32(<2 x ptr> %ptrs, i32 8, <2 x i1> , <2 x i32> undef) + store <2 x i32> %vals, ptr %a ret void } -define void @masked_gather_v4i32(<4 x i32>* %a, <4 x i32*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v4i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v4i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -235,13 +235,13 @@ define void @masked_gather_v4i32(<4 x i32>* %a, <4 x i32*>* %b) vscale_range(2,0 ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %ptrs = load <4 x i32*>, <4 x i32*>* %b - %vals = call <4 x i32> @llvm.masked.gather.v4i32(<4 x i32*> %ptrs, i32 8, <4 x i1> , <4 x i32> undef) - store <4 x i32> %vals, <4 x i32>* %a + %ptrs = load <4 x ptr>, ptr %b + %vals = call <4 x i32> @llvm.masked.gather.v4i32(<4 x ptr> %ptrs, i32 8, <4 x i1> , <4 x i32> undef) + store <4 x i32> %vals, ptr %a ret void } -define void @masked_gather_v8i32(<8 x i32>* %a, <8 x i32*>* %b) #0 { +define void @masked_gather_v8i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: masked_gather_v8i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -265,13 +265,13 @@ define void @masked_gather_v8i32(<8 x i32>* %a, <8 x i32*>* %b) #0 { ; VBITS_GE_512-NEXT: ld1w { z0.d }, p0/z, [z0.d] ; VBITS_GE_512-NEXT: st1w { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %ptrs = load <8 x i32*>, <8 x i32*>* %b - %vals = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %ptrs, i32 8, <8 x i1> , <8 x i32> undef) - store <8 x i32> %vals, <8 x i32>* %a + %ptrs = load <8 x ptr>, ptr %b + %vals = call <8 x i32> @llvm.masked.gather.v8i32(<8 x ptr> %ptrs, i32 8, <8 x i1> , <8 x i32> undef) + store <8 x i32> %vals, ptr %a ret void } -define void @masked_gather_v16i32(<16 x i32>* %a, <16 x i32*>* %b) vscale_range(8,0) #0 { +define void @masked_gather_v16i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_gather_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -279,14 +279,14 @@ define void @masked_gather_v16i32(<16 x i32>* %a, <16 x i32*>* %b) vscale_range( ; CHECK-NEXT: ld1w { z0.d }, p0/z, [z0.d] ; CHECK-NEXT: st1w { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %ptrs = load <16 x i32*>, <16 x i32*>* %b - %vals = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %ptrs, i32 8, <16 x i1> , ptr %b + %vals = call <16 x i32> @llvm.masked.gather.v16i32(<16 x ptr> %ptrs, i32 8, <16 x i1> , <16 x i32> undef) - store <16 x i32> %vals, <16 x i32>* %a + store <16 x i32> %vals, ptr %a ret void } -define void @masked_gather_v32i32(<32 x i32>* %a, <32 x i32*>* %b) vscale_range(16,0) #0 { +define void @masked_gather_v32i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_gather_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -294,12 +294,12 @@ define void @masked_gather_v32i32(<32 x i32>* %a, <32 x i32*>* %b) vscale_range( ; CHECK-NEXT: ld1w { z0.d }, p0/z, [z0.d] ; CHECK-NEXT: st1w { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %ptrs = load <32 x i32*>, <32 x i32*>* %b - %vals = call <32 x i32> @llvm.masked.gather.v32i32(<32 x i32*> %ptrs, i32 8, <32 x i1> , ptr %b + %vals = call <32 x i32> @llvm.masked.gather.v32i32(<32 x ptr> %ptrs, i32 8, <32 x i1> , <32 x i32> undef) - store <32 x i32> %vals, <32 x i32>* %a + store <32 x i32> %vals, ptr %a ret void } @@ -307,7 +307,7 @@ define void @masked_gather_v32i32(<32 x i32>* %a, <32 x i32*>* %b) vscale_range( ; LD1D ; -define void @masked_gather_v2i64(<2 x i64>* %a, <2 x i64*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v2i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v2i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x1] @@ -315,13 +315,13 @@ define void @masked_gather_v2i64(<2 x i64>* %a, <2 x i64*>* %b) vscale_range(2,0 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [z0.d] ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %ptrs = load <2 x i64*>, <2 x i64*>* %b - %vals = call <2 x i64> @llvm.masked.gather.v2i64(<2 x i64*> %ptrs, i32 8, <2 x i1> , <2 x i64> undef) - store <2 x i64> %vals, <2 x i64>* %a + %ptrs = load <2 x ptr>, ptr %b + %vals = call <2 x i64> @llvm.masked.gather.v2i64(<2 x ptr> %ptrs, i32 8, <2 x i1> , <2 x i64> undef) + store <2 x i64> %vals, ptr %a ret void } -define void @masked_gather_v4i64(<4 x i64>* %a, <4 x i64*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -329,13 +329,13 @@ define void @masked_gather_v4i64(<4 x i64>* %a, <4 x i64*>* %b) vscale_range(2,0 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [z0.d] ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %ptrs = load <4 x i64*>, <4 x i64*>* %b - %vals = call <4 x i64> @llvm.masked.gather.v4i64(<4 x i64*> %ptrs, i32 8, <4 x i1> , <4 x i64> undef) - store <4 x i64> %vals, <4 x i64>* %a + %ptrs = load <4 x ptr>, ptr %b + %vals = call <4 x i64> @llvm.masked.gather.v4i64(<4 x ptr> %ptrs, i32 8, <4 x i1> , <4 x i64> undef) + store <4 x i64> %vals, ptr %a ret void } -define void @masked_gather_v8i64(<8 x i64>* %a, <8 x i64*>* %b) #0 { +define void @masked_gather_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: masked_gather_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -355,13 +355,13 @@ define void @masked_gather_v8i64(<8 x i64>* %a, <8 x i64*>* %b) #0 { ; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [z0.d] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %ptrs = load <8 x i64*>, <8 x i64*>* %b - %vals = call <8 x i64> @llvm.masked.gather.v8i64(<8 x i64*> %ptrs, i32 8, <8 x i1> , <8 x i64> undef) - store <8 x i64> %vals, <8 x i64>* %a + %ptrs = load <8 x ptr>, ptr %b + %vals = call <8 x i64> @llvm.masked.gather.v8i64(<8 x ptr> %ptrs, i32 8, <8 x i1> , <8 x i64> undef) + store <8 x i64> %vals, ptr %a ret void } -define void @masked_gather_v16i64(<16 x i64>* %a, <16 x i64*>* %b) vscale_range(8,0) #0 { +define void @masked_gather_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_gather_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -369,14 +369,14 @@ define void @masked_gather_v16i64(<16 x i64>* %a, <16 x i64*>* %b) vscale_range( ; CHECK-NEXT: ld1d { z0.d }, p0/z, [z0.d] ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %ptrs = load <16 x i64*>, <16 x i64*>* %b - %vals = call <16 x i64> @llvm.masked.gather.v16i64(<16 x i64*> %ptrs, i32 8, <16 x i1> , ptr %b + %vals = call <16 x i64> @llvm.masked.gather.v16i64(<16 x ptr> %ptrs, i32 8, <16 x i1> , <16 x i64> undef) - store <16 x i64> %vals, <16 x i64>* %a + store <16 x i64> %vals, ptr %a ret void } -define void @masked_gather_v32i64(<32 x i64>* %a, <32 x i64*>* %b) vscale_range(16,0) #0 { +define void @masked_gather_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_gather_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -384,37 +384,37 @@ define void @masked_gather_v32i64(<32 x i64>* %a, <32 x i64*>* %b) vscale_range( ; CHECK-NEXT: ld1d { z0.d }, p0/z, [z0.d] ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %ptrs = load <32 x i64*>, <32 x i64*>* %b - %vals = call <32 x i64> @llvm.masked.gather.v32i64(<32 x i64*> %ptrs, i32 8, <32 x i1> , ptr %b + %vals = call <32 x i64> @llvm.masked.gather.v32i64(<32 x ptr> %ptrs, i32 8, <32 x i1> , <32 x i64> undef) - store <32 x i64> %vals, <32 x i64>* %a + store <32 x i64> %vals, ptr %a ret void } -declare <2 x i8> @llvm.masked.gather.v2i8(<2 x i8*>, i32, <2 x i1>, <2 x i8>) -declare <4 x i8> @llvm.masked.gather.v4i8(<4 x i8*>, i32, <4 x i1>, <4 x i8>) -declare <8 x i8> @llvm.masked.gather.v8i8(<8 x i8*>, i32, <8 x i1>, <8 x i8>) -declare <16 x i8> @llvm.masked.gather.v16i8(<16 x i8*>, i32, <16 x i1>, <16 x i8>) -declare <32 x i8> @llvm.masked.gather.v32i8(<32 x i8*>, i32, <32 x i1>, <32 x i8>) +declare <2 x i8> @llvm.masked.gather.v2i8(<2 x ptr>, i32, <2 x i1>, <2 x i8>) +declare <4 x i8> @llvm.masked.gather.v4i8(<4 x ptr>, i32, <4 x i1>, <4 x i8>) +declare <8 x i8> @llvm.masked.gather.v8i8(<8 x ptr>, i32, <8 x i1>, <8 x i8>) +declare <16 x i8> @llvm.masked.gather.v16i8(<16 x ptr>, i32, <16 x i1>, <16 x i8>) +declare <32 x i8> @llvm.masked.gather.v32i8(<32 x ptr>, i32, <32 x i1>, <32 x i8>) -declare <2 x i16> @llvm.masked.gather.v2i16(<2 x i16*>, i32, <2 x i1>, <2 x i16>) -declare <4 x i16> @llvm.masked.gather.v4i16(<4 x i16*>, i32, <4 x i1>, <4 x i16>) -declare <8 x i16> @llvm.masked.gather.v8i16(<8 x i16*>, i32, <8 x i1>, <8 x i16>) -declare <16 x i16> @llvm.masked.gather.v16i16(<16 x i16*>, i32, <16 x i1>, <16 x i16>) -declare <32 x i16> @llvm.masked.gather.v32i16(<32 x i16*>, i32, <32 x i1>, <32 x i16>) +declare <2 x i16> @llvm.masked.gather.v2i16(<2 x ptr>, i32, <2 x i1>, <2 x i16>) +declare <4 x i16> @llvm.masked.gather.v4i16(<4 x ptr>, i32, <4 x i1>, <4 x i16>) +declare <8 x i16> @llvm.masked.gather.v8i16(<8 x ptr>, i32, <8 x i1>, <8 x i16>) +declare <16 x i16> @llvm.masked.gather.v16i16(<16 x ptr>, i32, <16 x i1>, <16 x i16>) +declare <32 x i16> @llvm.masked.gather.v32i16(<32 x ptr>, i32, <32 x i1>, <32 x i16>) -declare <2 x i32> @llvm.masked.gather.v2i32(<2 x i32*>, i32, <2 x i1>, <2 x i32>) -declare <4 x i32> @llvm.masked.gather.v4i32(<4 x i32*>, i32, <4 x i1>, <4 x i32>) -declare <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*>, i32, <8 x i1>, <8 x i32>) -declare <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*>, i32, <16 x i1>, <16 x i32>) -declare <32 x i32> @llvm.masked.gather.v32i32(<32 x i32*>, i32, <32 x i1>, <32 x i32>) +declare <2 x i32> @llvm.masked.gather.v2i32(<2 x ptr>, i32, <2 x i1>, <2 x i32>) +declare <4 x i32> @llvm.masked.gather.v4i32(<4 x ptr>, i32, <4 x i1>, <4 x i32>) +declare <8 x i32> @llvm.masked.gather.v8i32(<8 x ptr>, i32, <8 x i1>, <8 x i32>) +declare <16 x i32> @llvm.masked.gather.v16i32(<16 x ptr>, i32, <16 x i1>, <16 x i32>) +declare <32 x i32> @llvm.masked.gather.v32i32(<32 x ptr>, i32, <32 x i1>, <32 x i32>) -declare <2 x i64> @llvm.masked.gather.v2i64(<2 x i64*>, i32, <2 x i1>, <2 x i64>) -declare <4 x i64> @llvm.masked.gather.v4i64(<4 x i64*>, i32, <4 x i1>, <4 x i64>) -declare <8 x i64> @llvm.masked.gather.v8i64(<8 x i64*>, i32, <8 x i1>, <8 x i64>) -declare <16 x i64> @llvm.masked.gather.v16i64(<16 x i64*>, i32, <16 x i1>, <16 x i64>) -declare <32 x i64> @llvm.masked.gather.v32i64(<32 x i64*>, i32, <32 x i1>, <32 x i64>) +declare <2 x i64> @llvm.masked.gather.v2i64(<2 x ptr>, i32, <2 x i1>, <2 x i64>) +declare <4 x i64> @llvm.masked.gather.v4i64(<4 x ptr>, i32, <4 x i1>, <4 x i64>) +declare <8 x i64> @llvm.masked.gather.v8i64(<8 x ptr>, i32, <8 x i1>, <8 x i64>) +declare <16 x i64> @llvm.masked.gather.v16i64(<16 x ptr>, i32, <16 x i1>, <16 x i64>) +declare <32 x i64> @llvm.masked.gather.v32i64(<32 x ptr>, i32, <32 x i1>, <32 x i64>) attributes #0 = { "target-features"="+sve" } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll index 6a2e40a..393a936 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll @@ -9,7 +9,7 @@ target triple = "aarch64-unknown-linux-gnu" ; LD1B ; -define void @masked_gather_v2i8(<2 x i8>* %a, <2 x i8*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v2i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v2i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldrb w8, [x0] @@ -26,15 +26,15 @@ define void @masked_gather_v2i8(<2 x i8>* %a, <2 x i8*>* %b) vscale_range(2,0) # ; CHECK-NEXT: xtn v0.2s, v0.2d ; CHECK-NEXT: st1b { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %cval = load <2 x i8>, <2 x i8>* %a - %ptrs = load <2 x i8*>, <2 x i8*>* %b + %cval = load <2 x i8>, ptr %a + %ptrs = load <2 x ptr>, ptr %b %mask = icmp eq <2 x i8> %cval, zeroinitializer - %vals = call <2 x i8> @llvm.masked.gather.v2i8(<2 x i8*> %ptrs, i32 8, <2 x i1> %mask, <2 x i8> undef) - store <2 x i8> %vals, <2 x i8>* %a + %vals = call <2 x i8> @llvm.masked.gather.v2i8(<2 x ptr> %ptrs, i32 8, <2 x i1> %mask, <2 x i8> undef) + store <2 x i8> %vals, ptr %a ret void } -define void @masked_gather_v4i8(<4 x i8>* %a, <4 x i8*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v4i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v4i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr s0, [x0] @@ -48,15 +48,15 @@ define void @masked_gather_v4i8(<4 x i8>* %a, <4 x i8*>* %b) vscale_range(2,0) # ; CHECK-NEXT: ld1b { z0.d }, p1/z, [z1.d] ; CHECK-NEXT: st1b { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %cval = load <4 x i8>, <4 x i8>* %a - %ptrs = load <4 x i8*>, <4 x i8*>* %b + %cval = load <4 x i8>, ptr %a + %ptrs = load <4 x ptr>, ptr %b %mask = icmp eq <4 x i8> %cval, zeroinitializer - %vals = call <4 x i8> @llvm.masked.gather.v4i8(<4 x i8*> %ptrs, i32 8, <4 x i1> %mask, <4 x i8> undef) - store <4 x i8> %vals, <4 x i8>* %a + %vals = call <4 x i8> @llvm.masked.gather.v4i8(<4 x ptr> %ptrs, i32 8, <4 x i1> %mask, <4 x i8> undef) + store <4 x i8> %vals, ptr %a ret void } -define void @masked_gather_v8i8(<8 x i8>* %a, <8 x i8*>* %b) #0 { +define void @masked_gather_v8i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: masked_gather_v8i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ldr d0, [x0] @@ -103,15 +103,15 @@ define void @masked_gather_v8i8(<8 x i8>* %a, <8 x i8*>* %b) #0 { ; VBITS_GE_512-NEXT: uzp1 z0.b, z0.b, z0.b ; VBITS_GE_512-NEXT: str d0, [x0] ; VBITS_GE_512-NEXT: ret - %cval = load <8 x i8>, <8 x i8>* %a - %ptrs = load <8 x i8*>, <8 x i8*>* %b + %cval = load <8 x i8>, ptr %a + %ptrs = load <8 x ptr>, ptr %b %mask = icmp eq <8 x i8> %cval, zeroinitializer - %vals = call <8 x i8> @llvm.masked.gather.v8i8(<8 x i8*> %ptrs, i32 8, <8 x i1> %mask, <8 x i8> undef) - store <8 x i8> %vals, <8 x i8>* %a + %vals = call <8 x i8> @llvm.masked.gather.v8i8(<8 x ptr> %ptrs, i32 8, <8 x i1> %mask, <8 x i8> undef) + store <8 x i8> %vals, ptr %a ret void } -define void @masked_gather_v16i8(<16 x i8>* %a, <16 x i8*>* %b) vscale_range(8,0) #0 { +define void @masked_gather_v16i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_gather_v16i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -128,15 +128,15 @@ define void @masked_gather_v16i8(<16 x i8>* %a, <16 x i8*>* %b) vscale_range(8,0 ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %cval = load <16 x i8>, <16 x i8>* %a - %ptrs = load <16 x i8*>, <16 x i8*>* %b + %cval = load <16 x i8>, ptr %a + %ptrs = load <16 x ptr>, ptr %b %mask = icmp eq <16 x i8> %cval, zeroinitializer - %vals = call <16 x i8> @llvm.masked.gather.v16i8(<16 x i8*> %ptrs, i32 8, <16 x i1> %mask, <16 x i8> undef) - store <16 x i8> %vals, <16 x i8>* %a + %vals = call <16 x i8> @llvm.masked.gather.v16i8(<16 x ptr> %ptrs, i32 8, <16 x i1> %mask, <16 x i8> undef) + store <16 x i8> %vals, ptr %a ret void } -define void @masked_gather_v32i8(<32 x i8>* %a, <32 x i8*>* %b) vscale_range(16,0) #0 { +define void @masked_gather_v32i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_gather_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -150,11 +150,11 @@ define void @masked_gather_v32i8(<32 x i8>* %a, <32 x i8*>* %b) vscale_range(16, ; CHECK-NEXT: ld1b { z0.d }, p0/z, [z1.d] ; CHECK-NEXT: st1b { z0.d }, p1, [x0] ; CHECK-NEXT: ret - %cval = load <32 x i8>, <32 x i8>* %a - %ptrs = load <32 x i8*>, <32 x i8*>* %b + %cval = load <32 x i8>, ptr %a + %ptrs = load <32 x ptr>, ptr %b %mask = icmp eq <32 x i8> %cval, zeroinitializer - %vals = call <32 x i8> @llvm.masked.gather.v32i8(<32 x i8*> %ptrs, i32 8, <32 x i1> %mask, <32 x i8> undef) - store <32 x i8> %vals, <32 x i8>* %a + %vals = call <32 x i8> @llvm.masked.gather.v32i8(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x i8> undef) + store <32 x i8> %vals, ptr %a ret void } @@ -162,7 +162,7 @@ define void @masked_gather_v32i8(<32 x i8>* %a, <32 x i8*>* %b) vscale_range(16, ; LD1H ; -define void @masked_gather_v2i16(<2 x i16>* %a, <2 x i16*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v2i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v2i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldrh w8, [x0] @@ -179,15 +179,15 @@ define void @masked_gather_v2i16(<2 x i16>* %a, <2 x i16*>* %b) vscale_range(2,0 ; CHECK-NEXT: xtn v0.2s, v0.2d ; CHECK-NEXT: st1h { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %cval = load <2 x i16>, <2 x i16>* %a - %ptrs = load <2 x i16*>, <2 x i16*>* %b + %cval = load <2 x i16>, ptr %a + %ptrs = load <2 x ptr>, ptr %b %mask = icmp eq <2 x i16> %cval, zeroinitializer - %vals = call <2 x i16> @llvm.masked.gather.v2i16(<2 x i16*> %ptrs, i32 8, <2 x i1> %mask, <2 x i16> undef) - store <2 x i16> %vals, <2 x i16>* %a + %vals = call <2 x i16> @llvm.masked.gather.v2i16(<2 x ptr> %ptrs, i32 8, <2 x i1> %mask, <2 x i16> undef) + store <2 x i16> %vals, ptr %a ret void } -define void @masked_gather_v4i16(<4 x i16>* %a, <4 x i16*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v4i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v4i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -202,15 +202,15 @@ define void @masked_gather_v4i16(<4 x i16>* %a, <4 x i16*>* %b) vscale_range(2,0 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret - %cval = load <4 x i16>, <4 x i16>* %a - %ptrs = load <4 x i16*>, <4 x i16*>* %b + %cval = load <4 x i16>, ptr %a + %ptrs = load <4 x ptr>, ptr %b %mask = icmp eq <4 x i16> %cval, zeroinitializer - %vals = call <4 x i16> @llvm.masked.gather.v4i16(<4 x i16*> %ptrs, i32 8, <4 x i1> %mask, <4 x i16> undef) - store <4 x i16> %vals, <4 x i16>* %a + %vals = call <4 x i16> @llvm.masked.gather.v4i16(<4 x ptr> %ptrs, i32 8, <4 x i1> %mask, <4 x i16> undef) + store <4 x i16> %vals, ptr %a ret void } -define void @masked_gather_v8i16(<8 x i16>* %a, <8 x i16*>* %b) #0 { +define void @masked_gather_v8i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: masked_gather_v8i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ldr q0, [x0] @@ -250,15 +250,15 @@ define void @masked_gather_v8i16(<8 x i16>* %a, <8 x i16*>* %b) #0 { ; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h ; VBITS_GE_512-NEXT: str q0, [x0] ; VBITS_GE_512-NEXT: ret - %cval = load <8 x i16>, <8 x i16>* %a - %ptrs = load <8 x i16*>, <8 x i16*>* %b + %cval = load <8 x i16>, ptr %a + %ptrs = load <8 x ptr>, ptr %b %mask = icmp eq <8 x i16> %cval, zeroinitializer - %vals = call <8 x i16> @llvm.masked.gather.v8i16(<8 x i16*> %ptrs, i32 8, <8 x i1> %mask, <8 x i16> undef) - store <8 x i16> %vals, <8 x i16>* %a + %vals = call <8 x i16> @llvm.masked.gather.v8i16(<8 x ptr> %ptrs, i32 8, <8 x i1> %mask, <8 x i16> undef) + store <8 x i16> %vals, ptr %a ret void } -define void @masked_gather_v16i16(<16 x i16>* %a, <16 x i16*>* %b) vscale_range(8,0) #0 { +define void @masked_gather_v16i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_gather_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -271,15 +271,15 @@ define void @masked_gather_v16i16(<16 x i16>* %a, <16 x i16*>* %b) vscale_range( ; CHECK-NEXT: ld1h { z0.d }, p0/z, [z1.d] ; CHECK-NEXT: st1h { z0.d }, p1, [x0] ; CHECK-NEXT: ret - %cval = load <16 x i16>, <16 x i16>* %a - %ptrs = load <16 x i16*>, <16 x i16*>* %b + %cval = load <16 x i16>, ptr %a + %ptrs = load <16 x ptr>, ptr %b %mask = icmp eq <16 x i16> %cval, zeroinitializer - %vals = call <16 x i16> @llvm.masked.gather.v16i16(<16 x i16*> %ptrs, i32 8, <16 x i1> %mask, <16 x i16> undef) - store <16 x i16> %vals, <16 x i16>* %a + %vals = call <16 x i16> @llvm.masked.gather.v16i16(<16 x ptr> %ptrs, i32 8, <16 x i1> %mask, <16 x i16> undef) + store <16 x i16> %vals, ptr %a ret void } -define void @masked_gather_v32i16(<32 x i16>* %a, <32 x i16*>* %b) vscale_range(16,0) #0 { +define void @masked_gather_v32i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_gather_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -292,11 +292,11 @@ define void @masked_gather_v32i16(<32 x i16>* %a, <32 x i16*>* %b) vscale_range( ; CHECK-NEXT: ld1h { z0.d }, p0/z, [z1.d] ; CHECK-NEXT: st1h { z0.d }, p1, [x0] ; CHECK-NEXT: ret - %cval = load <32 x i16>, <32 x i16>* %a - %ptrs = load <32 x i16*>, <32 x i16*>* %b + %cval = load <32 x i16>, ptr %a + %ptrs = load <32 x ptr>, ptr %b %mask = icmp eq <32 x i16> %cval, zeroinitializer - %vals = call <32 x i16> @llvm.masked.gather.v32i16(<32 x i16*> %ptrs, i32 8, <32 x i1> %mask, <32 x i16> undef) - store <32 x i16> %vals, <32 x i16>* %a + %vals = call <32 x i16> @llvm.masked.gather.v32i16(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x i16> undef) + store <32 x i16> %vals, ptr %a ret void } @@ -304,7 +304,7 @@ define void @masked_gather_v32i16(<32 x i16>* %a, <32 x i16*>* %b) vscale_range( ; LD1W ; -define void @masked_gather_v2i32(<2 x i32>* %a, <2 x i32*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v2i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v2i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -317,15 +317,15 @@ define void @masked_gather_v2i32(<2 x i32>* %a, <2 x i32*>* %b) vscale_range(2,0 ; CHECK-NEXT: xtn v0.2s, v0.2d ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret - %cval = load <2 x i32>, <2 x i32>* %a - %ptrs = load <2 x i32*>, <2 x i32*>* %b + %cval = load <2 x i32>, ptr %a + %ptrs = load <2 x ptr>, ptr %b %mask = icmp eq <2 x i32> %cval, zeroinitializer - %vals = call <2 x i32> @llvm.masked.gather.v2i32(<2 x i32*> %ptrs, i32 8, <2 x i1> %mask, <2 x i32> undef) - store <2 x i32> %vals, <2 x i32>* %a + %vals = call <2 x i32> @llvm.masked.gather.v2i32(<2 x ptr> %ptrs, i32 8, <2 x i1> %mask, <2 x i32> undef) + store <2 x i32> %vals, ptr %a ret void } -define void @masked_gather_v4i32(<4 x i32>* %a, <4 x i32*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v4i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v4i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -338,15 +338,15 @@ define void @masked_gather_v4i32(<4 x i32>* %a, <4 x i32*>* %b) vscale_range(2,0 ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %cval = load <4 x i32>, <4 x i32>* %a - %ptrs = load <4 x i32*>, <4 x i32*>* %b + %cval = load <4 x i32>, ptr %a + %ptrs = load <4 x ptr>, ptr %b %mask = icmp eq <4 x i32> %cval, zeroinitializer - %vals = call <4 x i32> @llvm.masked.gather.v4i32(<4 x i32*> %ptrs, i32 8, <4 x i1> %mask, <4 x i32> undef) - store <4 x i32> %vals, <4 x i32>* %a + %vals = call <4 x i32> @llvm.masked.gather.v4i32(<4 x ptr> %ptrs, i32 8, <4 x i1> %mask, <4 x i32> undef) + store <4 x i32> %vals, ptr %a ret void } -define void @masked_gather_v8i32(<8 x i32>* %a, <8 x i32*>* %b) #0 { +define void @masked_gather_v8i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: masked_gather_v8i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.s, vl8 @@ -382,15 +382,15 @@ define void @masked_gather_v8i32(<8 x i32>* %a, <8 x i32*>* %b) #0 { ; VBITS_GE_512-NEXT: ld1w { z0.d }, p0/z, [z1.d] ; VBITS_GE_512-NEXT: st1w { z0.d }, p1, [x0] ; VBITS_GE_512-NEXT: ret - %cval = load <8 x i32>, <8 x i32>* %a - %ptrs = load <8 x i32*>, <8 x i32*>* %b + %cval = load <8 x i32>, ptr %a + %ptrs = load <8 x ptr>, ptr %b %mask = icmp eq <8 x i32> %cval, zeroinitializer - %vals = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %ptrs, i32 8, <8 x i1> %mask, <8 x i32> undef) - store <8 x i32> %vals, <8 x i32>* %a + %vals = call <8 x i32> @llvm.masked.gather.v8i32(<8 x ptr> %ptrs, i32 8, <8 x i1> %mask, <8 x i32> undef) + store <8 x i32> %vals, ptr %a ret void } -define void @masked_gather_v16i32(<16 x i32>* %a, <16 x i32*>* %b) vscale_range(8,0) #0 { +define void @masked_gather_v16i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_gather_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -402,15 +402,15 @@ define void @masked_gather_v16i32(<16 x i32>* %a, <16 x i32*>* %b) vscale_range( ; CHECK-NEXT: ld1w { z0.d }, p0/z, [z1.d] ; CHECK-NEXT: st1w { z0.d }, p1, [x0] ; CHECK-NEXT: ret - %cval = load <16 x i32>, <16 x i32>* %a - %ptrs = load <16 x i32*>, <16 x i32*>* %b + %cval = load <16 x i32>, ptr %a + %ptrs = load <16 x ptr>, ptr %b %mask = icmp eq <16 x i32> %cval, zeroinitializer - %vals = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %ptrs, i32 8, <16 x i1> %mask, <16 x i32> undef) - store <16 x i32> %vals, <16 x i32>* %a + %vals = call <16 x i32> @llvm.masked.gather.v16i32(<16 x ptr> %ptrs, i32 8, <16 x i1> %mask, <16 x i32> undef) + store <16 x i32> %vals, ptr %a ret void } -define void @masked_gather_v32i32(<32 x i32>* %a, <32 x i32*>* %b) vscale_range(16,0) #0 { +define void @masked_gather_v32i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_gather_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -422,11 +422,11 @@ define void @masked_gather_v32i32(<32 x i32>* %a, <32 x i32*>* %b) vscale_range( ; CHECK-NEXT: ld1w { z0.d }, p0/z, [z1.d] ; CHECK-NEXT: st1w { z0.d }, p1, [x0] ; CHECK-NEXT: ret - %cval = load <32 x i32>, <32 x i32>* %a - %ptrs = load <32 x i32*>, <32 x i32*>* %b + %cval = load <32 x i32>, ptr %a + %ptrs = load <32 x ptr>, ptr %b %mask = icmp eq <32 x i32> %cval, zeroinitializer - %vals = call <32 x i32> @llvm.masked.gather.v32i32(<32 x i32*> %ptrs, i32 8, <32 x i1> %mask, <32 x i32> undef) - store <32 x i32> %vals, <32 x i32>* %a + %vals = call <32 x i32> @llvm.masked.gather.v32i32(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x i32> undef) + store <32 x i32> %vals, ptr %a ret void } @@ -435,7 +435,7 @@ define void @masked_gather_v32i32(<32 x i32>* %a, <32 x i32*>* %b) vscale_range( ; ; Scalarize 1 x i64 gathers -define void @masked_gather_v1i64(<1 x i64>* %a, <1 x i64*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v1i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v1i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -449,15 +449,15 @@ define void @masked_gather_v1i64(<1 x i64>* %a, <1 x i64*>* %b) vscale_range(2,0 ; CHECK-NEXT: .LBB15_2: // %else ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret - %cval = load <1 x i64>, <1 x i64>* %a - %ptrs = load <1 x i64*>, <1 x i64*>* %b + %cval = load <1 x i64>, ptr %a + %ptrs = load <1 x ptr>, ptr %b %mask = icmp eq <1 x i64> %cval, zeroinitializer - %vals = call <1 x i64> @llvm.masked.gather.v1i64(<1 x i64*> %ptrs, i32 8, <1 x i1> %mask, <1 x i64> undef) - store <1 x i64> %vals, <1 x i64>* %a + %vals = call <1 x i64> @llvm.masked.gather.v1i64(<1 x ptr> %ptrs, i32 8, <1 x i1> %mask, <1 x i64> undef) + store <1 x i64> %vals, ptr %a ret void } -define void @masked_gather_v2i64(<2 x i64>* %a, <2 x i64*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v2i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v2i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -468,15 +468,15 @@ define void @masked_gather_v2i64(<2 x i64>* %a, <2 x i64*>* %b) vscale_range(2,0 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [z1.d] ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %cval = load <2 x i64>, <2 x i64>* %a - %ptrs = load <2 x i64*>, <2 x i64*>* %b + %cval = load <2 x i64>, ptr %a + %ptrs = load <2 x ptr>, ptr %b %mask = icmp eq <2 x i64> %cval, zeroinitializer - %vals = call <2 x i64> @llvm.masked.gather.v2i64(<2 x i64*> %ptrs, i32 8, <2 x i1> %mask, <2 x i64> undef) - store <2 x i64> %vals, <2 x i64>* %a + %vals = call <2 x i64> @llvm.masked.gather.v2i64(<2 x ptr> %ptrs, i32 8, <2 x i1> %mask, <2 x i64> undef) + store <2 x i64> %vals, ptr %a ret void } -define void @masked_gather_v4i64(<4 x i64>* %a, <4 x i64*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -486,15 +486,15 @@ define void @masked_gather_v4i64(<4 x i64>* %a, <4 x i64*>* %b) vscale_range(2,0 ; CHECK-NEXT: ld1d { z0.d }, p1/z, [z1.d] ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %cval = load <4 x i64>, <4 x i64>* %a - %ptrs = load <4 x i64*>, <4 x i64*>* %b + %cval = load <4 x i64>, ptr %a + %ptrs = load <4 x ptr>, ptr %b %mask = icmp eq <4 x i64> %cval, zeroinitializer - %vals = call <4 x i64> @llvm.masked.gather.v4i64(<4 x i64*> %ptrs, i32 8, <4 x i1> %mask, <4 x i64> undef) - store <4 x i64> %vals, <4 x i64>* %a + %vals = call <4 x i64> @llvm.masked.gather.v4i64(<4 x ptr> %ptrs, i32 8, <4 x i1> %mask, <4 x i64> undef) + store <4 x i64> %vals, ptr %a ret void } -define void @masked_gather_v8i64(<8 x i64>* %a, <8 x i64*>* %b) #0 { +define void @masked_gather_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: masked_gather_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -520,15 +520,15 @@ define void @masked_gather_v8i64(<8 x i64>* %a, <8 x i64*>* %b) #0 { ; VBITS_GE_512-NEXT: ld1d { z0.d }, p1/z, [z1.d] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %cval = load <8 x i64>, <8 x i64>* %a - %ptrs = load <8 x i64*>, <8 x i64*>* %b + %cval = load <8 x i64>, ptr %a + %ptrs = load <8 x ptr>, ptr %b %mask = icmp eq <8 x i64> %cval, zeroinitializer - %vals = call <8 x i64> @llvm.masked.gather.v8i64(<8 x i64*> %ptrs, i32 8, <8 x i1> %mask, <8 x i64> undef) - store <8 x i64> %vals, <8 x i64>* %a + %vals = call <8 x i64> @llvm.masked.gather.v8i64(<8 x ptr> %ptrs, i32 8, <8 x i1> %mask, <8 x i64> undef) + store <8 x i64> %vals, ptr %a ret void } -define void @masked_gather_v16i64(<16 x i64>* %a, <16 x i64*>* %b) vscale_range(8,0) #0 { +define void @masked_gather_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_gather_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -538,15 +538,15 @@ define void @masked_gather_v16i64(<16 x i64>* %a, <16 x i64*>* %b) vscale_range( ; CHECK-NEXT: ld1d { z0.d }, p1/z, [z1.d] ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %cval = load <16 x i64>, <16 x i64>* %a - %ptrs = load <16 x i64*>, <16 x i64*>* %b + %cval = load <16 x i64>, ptr %a + %ptrs = load <16 x ptr>, ptr %b %mask = icmp eq <16 x i64> %cval, zeroinitializer - %vals = call <16 x i64> @llvm.masked.gather.v16i64(<16 x i64*> %ptrs, i32 8, <16 x i1> %mask, <16 x i64> undef) - store <16 x i64> %vals, <16 x i64>* %a + %vals = call <16 x i64> @llvm.masked.gather.v16i64(<16 x ptr> %ptrs, i32 8, <16 x i1> %mask, <16 x i64> undef) + store <16 x i64> %vals, ptr %a ret void } -define void @masked_gather_v32i64(<32 x i64>* %a, <32 x i64*>* %b) vscale_range(16,0) #0 { +define void @masked_gather_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_gather_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -556,11 +556,11 @@ define void @masked_gather_v32i64(<32 x i64>* %a, <32 x i64*>* %b) vscale_range( ; CHECK-NEXT: ld1d { z0.d }, p1/z, [z1.d] ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %cval = load <32 x i64>, <32 x i64>* %a - %ptrs = load <32 x i64*>, <32 x i64*>* %b + %cval = load <32 x i64>, ptr %a + %ptrs = load <32 x ptr>, ptr %b %mask = icmp eq <32 x i64> %cval, zeroinitializer - %vals = call <32 x i64> @llvm.masked.gather.v32i64(<32 x i64*> %ptrs, i32 8, <32 x i1> %mask, <32 x i64> undef) - store <32 x i64> %vals, <32 x i64>* %a + %vals = call <32 x i64> @llvm.masked.gather.v32i64(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x i64> undef) + store <32 x i64> %vals, ptr %a ret void } @@ -568,7 +568,7 @@ define void @masked_gather_v32i64(<32 x i64>* %a, <32 x i64*>* %b) vscale_range( ; LD1H (float) ; -define void @masked_gather_v2f16(<2 x half>* %a, <2 x half*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v2f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v2f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr s1, [x0] @@ -591,15 +591,15 @@ define void @masked_gather_v2f16(<2 x half>* %a, <2 x half*>* %b) vscale_range(2 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: str s0, [x0] ; CHECK-NEXT: ret - %cval = load <2 x half>, <2 x half>* %a - %ptrs = load <2 x half*>, <2 x half*>* %b + %cval = load <2 x half>, ptr %a + %ptrs = load <2 x ptr>, ptr %b %mask = fcmp oeq <2 x half> %cval, zeroinitializer - %vals = call <2 x half> @llvm.masked.gather.v2f16(<2 x half*> %ptrs, i32 8, <2 x i1> %mask, <2 x half> undef) - store <2 x half> %vals, <2 x half>* %a + %vals = call <2 x half> @llvm.masked.gather.v2f16(<2 x ptr> %ptrs, i32 8, <2 x i1> %mask, <2 x half> undef) + store <2 x half> %vals, ptr %a ret void } -define void @masked_gather_v4f16(<4 x half>* %a, <4 x half*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v4f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v4f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -614,15 +614,15 @@ define void @masked_gather_v4f16(<4 x half>* %a, <4 x half*>* %b) vscale_range(2 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret - %cval = load <4 x half>, <4 x half>* %a - %ptrs = load <4 x half*>, <4 x half*>* %b + %cval = load <4 x half>, ptr %a + %ptrs = load <4 x ptr>, ptr %b %mask = fcmp oeq <4 x half> %cval, zeroinitializer - %vals = call <4 x half> @llvm.masked.gather.v4f16(<4 x half*> %ptrs, i32 8, <4 x i1> %mask, <4 x half> undef) - store <4 x half> %vals, <4 x half>* %a + %vals = call <4 x half> @llvm.masked.gather.v4f16(<4 x ptr> %ptrs, i32 8, <4 x i1> %mask, <4 x half> undef) + store <4 x half> %vals, ptr %a ret void } -define void @masked_gather_v8f16(<8 x half>* %a, <8 x half*>* %b) #0 { +define void @masked_gather_v8f16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: masked_gather_v8f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ldr q0, [x0] @@ -662,15 +662,15 @@ define void @masked_gather_v8f16(<8 x half>* %a, <8 x half*>* %b) #0 { ; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h ; VBITS_GE_512-NEXT: str q0, [x0] ; VBITS_GE_512-NEXT: ret - %cval = load <8 x half>, <8 x half>* %a - %ptrs = load <8 x half*>, <8 x half*>* %b + %cval = load <8 x half>, ptr %a + %ptrs = load <8 x ptr>, ptr %b %mask = fcmp oeq <8 x half> %cval, zeroinitializer - %vals = call <8 x half> @llvm.masked.gather.v8f16(<8 x half*> %ptrs, i32 8, <8 x i1> %mask, <8 x half> undef) - store <8 x half> %vals, <8 x half>* %a + %vals = call <8 x half> @llvm.masked.gather.v8f16(<8 x ptr> %ptrs, i32 8, <8 x i1> %mask, <8 x half> undef) + store <8 x half> %vals, ptr %a ret void } -define void @masked_gather_v16f16(<16 x half>* %a, <16 x half*>* %b) vscale_range(8,0) #0 { +define void @masked_gather_v16f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_gather_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -683,15 +683,15 @@ define void @masked_gather_v16f16(<16 x half>* %a, <16 x half*>* %b) vscale_rang ; CHECK-NEXT: ld1h { z0.d }, p0/z, [z1.d] ; CHECK-NEXT: st1h { z0.d }, p1, [x0] ; CHECK-NEXT: ret - %cval = load <16 x half>, <16 x half>* %a - %ptrs = load <16 x half*>, <16 x half*>* %b + %cval = load <16 x half>, ptr %a + %ptrs = load <16 x ptr>, ptr %b %mask = fcmp oeq <16 x half> %cval, zeroinitializer - %vals = call <16 x half> @llvm.masked.gather.v16f16(<16 x half*> %ptrs, i32 8, <16 x i1> %mask, <16 x half> undef) - store <16 x half> %vals, <16 x half>* %a + %vals = call <16 x half> @llvm.masked.gather.v16f16(<16 x ptr> %ptrs, i32 8, <16 x i1> %mask, <16 x half> undef) + store <16 x half> %vals, ptr %a ret void } -define void @masked_gather_v32f16(<32 x half>* %a, <32 x half*>* %b) vscale_range(16,0) #0 { +define void @masked_gather_v32f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_gather_v32f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -704,11 +704,11 @@ define void @masked_gather_v32f16(<32 x half>* %a, <32 x half*>* %b) vscale_rang ; CHECK-NEXT: ld1h { z0.d }, p0/z, [z1.d] ; CHECK-NEXT: st1h { z0.d }, p1, [x0] ; CHECK-NEXT: ret - %cval = load <32 x half>, <32 x half>* %a - %ptrs = load <32 x half*>, <32 x half*>* %b + %cval = load <32 x half>, ptr %a + %ptrs = load <32 x ptr>, ptr %b %mask = fcmp oeq <32 x half> %cval, zeroinitializer - %vals = call <32 x half> @llvm.masked.gather.v32f16(<32 x half*> %ptrs, i32 8, <32 x i1> %mask, <32 x half> undef) - store <32 x half> %vals, <32 x half>* %a + %vals = call <32 x half> @llvm.masked.gather.v32f16(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x half> undef) + store <32 x half> %vals, ptr %a ret void } @@ -716,7 +716,7 @@ define void @masked_gather_v32f16(<32 x half>* %a, <32 x half*>* %b) vscale_rang ; LD1W (float) ; -define void @masked_gather_v2f32(<2 x float>* %a, <2 x float*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v2f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v2f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -729,15 +729,15 @@ define void @masked_gather_v2f32(<2 x float>* %a, <2 x float*>* %b) vscale_range ; CHECK-NEXT: xtn v0.2s, v0.2d ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret - %cval = load <2 x float>, <2 x float>* %a - %ptrs = load <2 x float*>, <2 x float*>* %b + %cval = load <2 x float>, ptr %a + %ptrs = load <2 x ptr>, ptr %b %mask = fcmp oeq <2 x float> %cval, zeroinitializer - %vals = call <2 x float> @llvm.masked.gather.v2f32(<2 x float*> %ptrs, i32 8, <2 x i1> %mask, <2 x float> undef) - store <2 x float> %vals, <2 x float>* %a + %vals = call <2 x float> @llvm.masked.gather.v2f32(<2 x ptr> %ptrs, i32 8, <2 x i1> %mask, <2 x float> undef) + store <2 x float> %vals, ptr %a ret void } -define void @masked_gather_v4f32(<4 x float>* %a, <4 x float*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v4f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v4f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -750,15 +750,15 @@ define void @masked_gather_v4f32(<4 x float>* %a, <4 x float*>* %b) vscale_range ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %cval = load <4 x float>, <4 x float>* %a - %ptrs = load <4 x float*>, <4 x float*>* %b + %cval = load <4 x float>, ptr %a + %ptrs = load <4 x ptr>, ptr %b %mask = fcmp oeq <4 x float> %cval, zeroinitializer - %vals = call <4 x float> @llvm.masked.gather.v4f32(<4 x float*> %ptrs, i32 8, <4 x i1> %mask, <4 x float> undef) - store <4 x float> %vals, <4 x float>* %a + %vals = call <4 x float> @llvm.masked.gather.v4f32(<4 x ptr> %ptrs, i32 8, <4 x i1> %mask, <4 x float> undef) + store <4 x float> %vals, ptr %a ret void } -define void @masked_gather_v8f32(<8 x float>* %a, <8 x float*>* %b) #0 { +define void @masked_gather_v8f32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: masked_gather_v8f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.s, vl8 @@ -794,15 +794,15 @@ define void @masked_gather_v8f32(<8 x float>* %a, <8 x float*>* %b) #0 { ; VBITS_GE_512-NEXT: ld1w { z0.d }, p0/z, [z1.d] ; VBITS_GE_512-NEXT: st1w { z0.d }, p1, [x0] ; VBITS_GE_512-NEXT: ret - %cval = load <8 x float>, <8 x float>* %a - %ptrs = load <8 x float*>, <8 x float*>* %b + %cval = load <8 x float>, ptr %a + %ptrs = load <8 x ptr>, ptr %b %mask = fcmp oeq <8 x float> %cval, zeroinitializer - %vals = call <8 x float> @llvm.masked.gather.v8f32(<8 x float*> %ptrs, i32 8, <8 x i1> %mask, <8 x float> undef) - store <8 x float> %vals, <8 x float>* %a + %vals = call <8 x float> @llvm.masked.gather.v8f32(<8 x ptr> %ptrs, i32 8, <8 x i1> %mask, <8 x float> undef) + store <8 x float> %vals, ptr %a ret void } -define void @masked_gather_v16f32(<16 x float>* %a, <16 x float*>* %b) vscale_range(8,0) #0 { +define void @masked_gather_v16f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_gather_v16f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -814,15 +814,15 @@ define void @masked_gather_v16f32(<16 x float>* %a, <16 x float*>* %b) vscale_ra ; CHECK-NEXT: ld1w { z0.d }, p0/z, [z1.d] ; CHECK-NEXT: st1w { z0.d }, p1, [x0] ; CHECK-NEXT: ret - %cval = load <16 x float>, <16 x float>* %a - %ptrs = load <16 x float*>, <16 x float*>* %b + %cval = load <16 x float>, ptr %a + %ptrs = load <16 x ptr>, ptr %b %mask = fcmp oeq <16 x float> %cval, zeroinitializer - %vals = call <16 x float> @llvm.masked.gather.v16f32(<16 x float*> %ptrs, i32 8, <16 x i1> %mask, <16 x float> undef) - store <16 x float> %vals, <16 x float>* %a + %vals = call <16 x float> @llvm.masked.gather.v16f32(<16 x ptr> %ptrs, i32 8, <16 x i1> %mask, <16 x float> undef) + store <16 x float> %vals, ptr %a ret void } -define void @masked_gather_v32f32(<32 x float>* %a, <32 x float*>* %b) vscale_range(16,0) #0 { +define void @masked_gather_v32f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_gather_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -834,11 +834,11 @@ define void @masked_gather_v32f32(<32 x float>* %a, <32 x float*>* %b) vscale_ra ; CHECK-NEXT: ld1w { z0.d }, p0/z, [z1.d] ; CHECK-NEXT: st1w { z0.d }, p1, [x0] ; CHECK-NEXT: ret - %cval = load <32 x float>, <32 x float>* %a - %ptrs = load <32 x float*>, <32 x float*>* %b + %cval = load <32 x float>, ptr %a + %ptrs = load <32 x ptr>, ptr %b %mask = fcmp oeq <32 x float> %cval, zeroinitializer - %vals = call <32 x float> @llvm.masked.gather.v32f32(<32 x float*> %ptrs, i32 8, <32 x i1> %mask, <32 x float> undef) - store <32 x float> %vals, <32 x float>* %a + %vals = call <32 x float> @llvm.masked.gather.v32f32(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x float> undef) + store <32 x float> %vals, ptr %a ret void } @@ -847,7 +847,7 @@ define void @masked_gather_v32f32(<32 x float>* %a, <32 x float*>* %b) vscale_ra ; ; Scalarize 1 x double gathers -define void @masked_gather_v1f64(<1 x double>* %a, <1 x double*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v1f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v1f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -861,15 +861,15 @@ define void @masked_gather_v1f64(<1 x double>* %a, <1 x double*>* %b) vscale_ran ; CHECK-NEXT: .LBB31_2: // %else ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret - %cval = load <1 x double>, <1 x double>* %a - %ptrs = load <1 x double*>, <1 x double*>* %b + %cval = load <1 x double>, ptr %a + %ptrs = load <1 x ptr>, ptr %b %mask = fcmp oeq <1 x double> %cval, zeroinitializer - %vals = call <1 x double> @llvm.masked.gather.v1f64(<1 x double*> %ptrs, i32 8, <1 x i1> %mask, <1 x double> undef) - store <1 x double> %vals, <1 x double>* %a + %vals = call <1 x double> @llvm.masked.gather.v1f64(<1 x ptr> %ptrs, i32 8, <1 x i1> %mask, <1 x double> undef) + store <1 x double> %vals, ptr %a ret void } -define void @masked_gather_v2f64(<2 x double>* %a, <2 x double*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v2f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v2f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -880,15 +880,15 @@ define void @masked_gather_v2f64(<2 x double>* %a, <2 x double*>* %b) vscale_ran ; CHECK-NEXT: ld1d { z0.d }, p0/z, [z1.d] ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %cval = load <2 x double>, <2 x double>* %a - %ptrs = load <2 x double*>, <2 x double*>* %b + %cval = load <2 x double>, ptr %a + %ptrs = load <2 x ptr>, ptr %b %mask = fcmp oeq <2 x double> %cval, zeroinitializer - %vals = call <2 x double> @llvm.masked.gather.v2f64(<2 x double*> %ptrs, i32 8, <2 x i1> %mask, <2 x double> undef) - store <2 x double> %vals, <2 x double>* %a + %vals = call <2 x double> @llvm.masked.gather.v2f64(<2 x ptr> %ptrs, i32 8, <2 x i1> %mask, <2 x double> undef) + store <2 x double> %vals, ptr %a ret void } -define void @masked_gather_v4f64(<4 x double>* %a, <4 x double*>* %b) vscale_range(2,0) #0 { +define void @masked_gather_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_gather_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -898,15 +898,15 @@ define void @masked_gather_v4f64(<4 x double>* %a, <4 x double*>* %b) vscale_ran ; CHECK-NEXT: ld1d { z0.d }, p1/z, [z1.d] ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %cval = load <4 x double>, <4 x double>* %a - %ptrs = load <4 x double*>, <4 x double*>* %b + %cval = load <4 x double>, ptr %a + %ptrs = load <4 x ptr>, ptr %b %mask = fcmp oeq <4 x double> %cval, zeroinitializer - %vals = call <4 x double> @llvm.masked.gather.v4f64(<4 x double*> %ptrs, i32 8, <4 x i1> %mask, <4 x double> undef) - store <4 x double> %vals, <4 x double>* %a + %vals = call <4 x double> @llvm.masked.gather.v4f64(<4 x ptr> %ptrs, i32 8, <4 x i1> %mask, <4 x double> undef) + store <4 x double> %vals, ptr %a ret void } -define void @masked_gather_v8f64(<8 x double>* %a, <8 x double*>* %b) #0 { +define void @masked_gather_v8f64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: masked_gather_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -932,15 +932,15 @@ define void @masked_gather_v8f64(<8 x double>* %a, <8 x double*>* %b) #0 { ; VBITS_GE_512-NEXT: ld1d { z0.d }, p1/z, [z1.d] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %cval = load <8 x double>, <8 x double>* %a - %ptrs = load <8 x double*>, <8 x double*>* %b + %cval = load <8 x double>, ptr %a + %ptrs = load <8 x ptr>, ptr %b %mask = fcmp oeq <8 x double> %cval, zeroinitializer - %vals = call <8 x double> @llvm.masked.gather.v8f64(<8 x double*> %ptrs, i32 8, <8 x i1> %mask, <8 x double> undef) - store <8 x double> %vals, <8 x double>* %a + %vals = call <8 x double> @llvm.masked.gather.v8f64(<8 x ptr> %ptrs, i32 8, <8 x i1> %mask, <8 x double> undef) + store <8 x double> %vals, ptr %a ret void } -define void @masked_gather_v16f64(<16 x double>* %a, <16 x double*>* %b) vscale_range(8,0) #0 { +define void @masked_gather_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_gather_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -950,15 +950,15 @@ define void @masked_gather_v16f64(<16 x double>* %a, <16 x double*>* %b) vscale_ ; CHECK-NEXT: ld1d { z0.d }, p1/z, [z1.d] ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %cval = load <16 x double>, <16 x double>* %a - %ptrs = load <16 x double*>, <16 x double*>* %b + %cval = load <16 x double>, ptr %a + %ptrs = load <16 x ptr>, ptr %b %mask = fcmp oeq <16 x double> %cval, zeroinitializer - %vals = call <16 x double> @llvm.masked.gather.v16f64(<16 x double*> %ptrs, i32 8, <16 x i1> %mask, <16 x double> undef) - store <16 x double> %vals, <16 x double>* %a + %vals = call <16 x double> @llvm.masked.gather.v16f64(<16 x ptr> %ptrs, i32 8, <16 x i1> %mask, <16 x double> undef) + store <16 x double> %vals, ptr %a ret void } -define void @masked_gather_v32f64(<32 x double>* %a, <32 x double*>* %b) vscale_range(16,0) #0 { +define void @masked_gather_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_gather_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -968,18 +968,18 @@ define void @masked_gather_v32f64(<32 x double>* %a, <32 x double*>* %b) vscale_ ; CHECK-NEXT: ld1d { z0.d }, p1/z, [z1.d] ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %cval = load <32 x double>, <32 x double>* %a - %ptrs = load <32 x double*>, <32 x double*>* %b + %cval = load <32 x double>, ptr %a + %ptrs = load <32 x ptr>, ptr %b %mask = fcmp oeq <32 x double> %cval, zeroinitializer - %vals = call <32 x double> @llvm.masked.gather.v32f64(<32 x double*> %ptrs, i32 8, <32 x i1> %mask, <32 x double> undef) - store <32 x double> %vals, <32 x double>* %a + %vals = call <32 x double> @llvm.masked.gather.v32f64(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x double> undef) + store <32 x double> %vals, ptr %a ret void } ; The above tests test the types, the below tests check that the addressing ; modes still function -define void @masked_gather_32b_scaled_sext_f16(<32 x half>* %a, <32 x i32>* %b, half* %base) vscale_range(8,0) #0 { +define void @masked_gather_32b_scaled_sext_f16(ptr %a, ptr %b, ptr %base) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_gather_32b_scaled_sext_f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -991,17 +991,17 @@ define void @masked_gather_32b_scaled_sext_f16(<32 x half>* %a, <32 x i32>* %b, ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x2, z1.s, sxtw #1] ; CHECK-NEXT: st1h { z0.s }, p1, [x0] ; CHECK-NEXT: ret - %cvals = load <32 x half>, <32 x half>* %a - %idxs = load <32 x i32>, <32 x i32>* %b + %cvals = load <32 x half>, ptr %a + %idxs = load <32 x i32>, ptr %b %ext = sext <32 x i32> %idxs to <32 x i64> - %ptrs = getelementptr half, half* %base, <32 x i64> %ext + %ptrs = getelementptr half, ptr %base, <32 x i64> %ext %mask = fcmp oeq <32 x half> %cvals, zeroinitializer - %vals = call <32 x half> @llvm.masked.gather.v32f16(<32 x half*> %ptrs, i32 8, <32 x i1> %mask, <32 x half> undef) - store <32 x half> %vals, <32 x half>* %a + %vals = call <32 x half> @llvm.masked.gather.v32f16(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x half> undef) + store <32 x half> %vals, ptr %a ret void } -define void @masked_gather_32b_scaled_sext_f32(<32 x float>* %a, <32 x i32>* %b, float* %base) vscale_range(8,0) #0 { +define void @masked_gather_32b_scaled_sext_f32(ptr %a, ptr %b, ptr %base) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_gather_32b_scaled_sext_f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1011,17 +1011,17 @@ define void @masked_gather_32b_scaled_sext_f32(<32 x float>* %a, <32 x i32>* %b, ; CHECK-NEXT: ld1w { z0.s }, p1/z, [x2, z1.s, sxtw #2] ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %cvals = load <32 x float>, <32 x float>* %a - %idxs = load <32 x i32>, <32 x i32>* %b + %cvals = load <32 x float>, ptr %a + %idxs = load <32 x i32>, ptr %b %ext = sext <32 x i32> %idxs to <32 x i64> - %ptrs = getelementptr float, float* %base, <32 x i64> %ext + %ptrs = getelementptr float, ptr %base, <32 x i64> %ext %mask = fcmp oeq <32 x float> %cvals, zeroinitializer - %vals = call <32 x float> @llvm.masked.gather.v32f32(<32 x float*> %ptrs, i32 8, <32 x i1> %mask, <32 x float> undef) - store <32 x float> %vals, <32 x float>* %a + %vals = call <32 x float> @llvm.masked.gather.v32f32(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x float> undef) + store <32 x float> %vals, ptr %a ret void } -define void @masked_gather_32b_scaled_sext_f64(<32 x double>* %a, <32 x i32>* %b, double* %base) vscale_range(16,0) #0 { +define void @masked_gather_32b_scaled_sext_f64(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_gather_32b_scaled_sext_f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1031,17 +1031,17 @@ define void @masked_gather_32b_scaled_sext_f64(<32 x double>* %a, <32 x i32>* %b ; CHECK-NEXT: ld1d { z0.d }, p1/z, [x2, z1.d, lsl #3] ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %cvals = load <32 x double>, <32 x double>* %a - %idxs = load <32 x i32>, <32 x i32>* %b + %cvals = load <32 x double>, ptr %a + %idxs = load <32 x i32>, ptr %b %ext = sext <32 x i32> %idxs to <32 x i64> - %ptrs = getelementptr double, double* %base, <32 x i64> %ext + %ptrs = getelementptr double, ptr %base, <32 x i64> %ext %mask = fcmp oeq <32 x double> %cvals, zeroinitializer - %vals = call <32 x double> @llvm.masked.gather.v32f64(<32 x double*> %ptrs, i32 8, <32 x i1> %mask, <32 x double> undef) - store <32 x double> %vals, <32 x double>* %a + %vals = call <32 x double> @llvm.masked.gather.v32f64(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x double> undef) + store <32 x double> %vals, ptr %a ret void } -define void @masked_gather_32b_scaled_zext(<32 x half>* %a, <32 x i32>* %b, half* %base) vscale_range(8,0) #0 { +define void @masked_gather_32b_scaled_zext(ptr %a, ptr %b, ptr %base) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_gather_32b_scaled_zext: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -1053,17 +1053,17 @@ define void @masked_gather_32b_scaled_zext(<32 x half>* %a, <32 x i32>* %b, half ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x2, z1.s, uxtw #1] ; CHECK-NEXT: st1h { z0.s }, p1, [x0] ; CHECK-NEXT: ret - %cvals = load <32 x half>, <32 x half>* %a - %idxs = load <32 x i32>, <32 x i32>* %b + %cvals = load <32 x half>, ptr %a + %idxs = load <32 x i32>, ptr %b %ext = zext <32 x i32> %idxs to <32 x i64> - %ptrs = getelementptr half, half* %base, <32 x i64> %ext + %ptrs = getelementptr half, ptr %base, <32 x i64> %ext %mask = fcmp oeq <32 x half> %cvals, zeroinitializer - %vals = call <32 x half> @llvm.masked.gather.v32f16(<32 x half*> %ptrs, i32 8, <32 x i1> %mask, <32 x half> undef) - store <32 x half> %vals, <32 x half>* %a + %vals = call <32 x half> @llvm.masked.gather.v32f16(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x half> undef) + store <32 x half> %vals, ptr %a ret void } -define void @masked_gather_32b_unscaled_sext(<32 x half>* %a, <32 x i32>* %b, i8* %base) vscale_range(8,0) #0 { +define void @masked_gather_32b_unscaled_sext(ptr %a, ptr %b, ptr %base) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_gather_32b_unscaled_sext: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -1075,18 +1075,18 @@ define void @masked_gather_32b_unscaled_sext(<32 x half>* %a, <32 x i32>* %b, i8 ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x2, z1.s, sxtw] ; CHECK-NEXT: st1h { z0.s }, p1, [x0] ; CHECK-NEXT: ret - %cvals = load <32 x half>, <32 x half>* %a - %idxs = load <32 x i32>, <32 x i32>* %b + %cvals = load <32 x half>, ptr %a + %idxs = load <32 x i32>, ptr %b %ext = sext <32 x i32> %idxs to <32 x i64> - %byte_ptrs = getelementptr i8, i8* %base, <32 x i64> %ext - %ptrs = bitcast <32 x i8*> %byte_ptrs to <32 x half*> + %byte_ptrs = getelementptr i8, ptr %base, <32 x i64> %ext + %ptrs = bitcast <32 x ptr> %byte_ptrs to <32 x ptr> %mask = fcmp oeq <32 x half> %cvals, zeroinitializer - %vals = call <32 x half> @llvm.masked.gather.v32f16(<32 x half*> %ptrs, i32 8, <32 x i1> %mask, <32 x half> undef) - store <32 x half> %vals, <32 x half>* %a + %vals = call <32 x half> @llvm.masked.gather.v32f16(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x half> undef) + store <32 x half> %vals, ptr %a ret void } -define void @masked_gather_32b_unscaled_zext(<32 x half>* %a, <32 x i32>* %b, i8* %base) vscale_range(8,0) #0 { +define void @masked_gather_32b_unscaled_zext(ptr %a, ptr %b, ptr %base) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_gather_32b_unscaled_zext: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -1098,18 +1098,18 @@ define void @masked_gather_32b_unscaled_zext(<32 x half>* %a, <32 x i32>* %b, i8 ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x2, z1.s, uxtw] ; CHECK-NEXT: st1h { z0.s }, p1, [x0] ; CHECK-NEXT: ret - %cvals = load <32 x half>, <32 x half>* %a - %idxs = load <32 x i32>, <32 x i32>* %b + %cvals = load <32 x half>, ptr %a + %idxs = load <32 x i32>, ptr %b %ext = zext <32 x i32> %idxs to <32 x i64> - %byte_ptrs = getelementptr i8, i8* %base, <32 x i64> %ext - %ptrs = bitcast <32 x i8*> %byte_ptrs to <32 x half*> + %byte_ptrs = getelementptr i8, ptr %base, <32 x i64> %ext + %ptrs = bitcast <32 x ptr> %byte_ptrs to <32 x ptr> %mask = fcmp oeq <32 x half> %cvals, zeroinitializer - %vals = call <32 x half> @llvm.masked.gather.v32f16(<32 x half*> %ptrs, i32 8, <32 x i1> %mask, <32 x half> undef) - store <32 x half> %vals, <32 x half>* %a + %vals = call <32 x half> @llvm.masked.gather.v32f16(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x half> undef) + store <32 x half> %vals, ptr %a ret void } -define void @masked_gather_64b_scaled(<32 x float>* %a, <32 x i64>* %b, float* %base) vscale_range(16,0) #0 { +define void @masked_gather_64b_scaled(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_gather_64b_scaled: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1121,16 +1121,16 @@ define void @masked_gather_64b_scaled(<32 x float>* %a, <32 x i64>* %b, float* % ; CHECK-NEXT: ld1w { z0.d }, p0/z, [x2, z1.d, lsl #2] ; CHECK-NEXT: st1w { z0.d }, p1, [x0] ; CHECK-NEXT: ret - %cvals = load <32 x float>, <32 x float>* %a - %idxs = load <32 x i64>, <32 x i64>* %b - %ptrs = getelementptr float, float* %base, <32 x i64> %idxs + %cvals = load <32 x float>, ptr %a + %idxs = load <32 x i64>, ptr %b + %ptrs = getelementptr float, ptr %base, <32 x i64> %idxs %mask = fcmp oeq <32 x float> %cvals, zeroinitializer - %vals = call <32 x float> @llvm.masked.gather.v32f32(<32 x float*> %ptrs, i32 8, <32 x i1> %mask, <32 x float> undef) - store <32 x float> %vals, <32 x float>* %a + %vals = call <32 x float> @llvm.masked.gather.v32f32(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x float> undef) + store <32 x float> %vals, ptr %a ret void } -define void @masked_gather_64b_unscaled(<32 x float>* %a, <32 x i64>* %b, i8* %base) vscale_range(16,0) #0 { +define void @masked_gather_64b_unscaled(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_gather_64b_unscaled: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1142,17 +1142,17 @@ define void @masked_gather_64b_unscaled(<32 x float>* %a, <32 x i64>* %b, i8* %b ; CHECK-NEXT: ld1w { z0.d }, p0/z, [x2, z1.d] ; CHECK-NEXT: st1w { z0.d }, p1, [x0] ; CHECK-NEXT: ret - %cvals = load <32 x float>, <32 x float>* %a - %idxs = load <32 x i64>, <32 x i64>* %b - %byte_ptrs = getelementptr i8, i8* %base, <32 x i64> %idxs - %ptrs = bitcast <32 x i8*> %byte_ptrs to <32 x float*> + %cvals = load <32 x float>, ptr %a + %idxs = load <32 x i64>, ptr %b + %byte_ptrs = getelementptr i8, ptr %base, <32 x i64> %idxs + %ptrs = bitcast <32 x ptr> %byte_ptrs to <32 x ptr> %mask = fcmp oeq <32 x float> %cvals, zeroinitializer - %vals = call <32 x float> @llvm.masked.gather.v32f32(<32 x float*> %ptrs, i32 8, <32 x i1> %mask, <32 x float> undef) - store <32 x float> %vals, <32 x float>* %a + %vals = call <32 x float> @llvm.masked.gather.v32f32(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x float> undef) + store <32 x float> %vals, ptr %a ret void } -define void @masked_gather_vec_plus_reg(<32 x float>* %a, <32 x i8*>* %b, i64 %off) vscale_range(16,0) #0 { +define void @masked_gather_vec_plus_reg(ptr %a, ptr %b, i64 %off) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_gather_vec_plus_reg: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1164,17 +1164,17 @@ define void @masked_gather_vec_plus_reg(<32 x float>* %a, <32 x i8*>* %b, i64 %o ; CHECK-NEXT: ld1w { z0.d }, p0/z, [x2, z1.d] ; CHECK-NEXT: st1w { z0.d }, p1, [x0] ; CHECK-NEXT: ret - %cvals = load <32 x float>, <32 x float>* %a - %bases = load <32 x i8*>, <32 x i8*>* %b - %byte_ptrs = getelementptr i8, <32 x i8*> %bases, i64 %off - %ptrs = bitcast <32 x i8*> %byte_ptrs to <32 x float*> + %cvals = load <32 x float>, ptr %a + %bases = load <32 x ptr>, ptr %b + %byte_ptrs = getelementptr i8, <32 x ptr> %bases, i64 %off + %ptrs = bitcast <32 x ptr> %byte_ptrs to <32 x ptr> %mask = fcmp oeq <32 x float> %cvals, zeroinitializer - %vals = call <32 x float> @llvm.masked.gather.v32f32(<32 x float*> %ptrs, i32 8, <32 x i1> %mask, <32 x float> undef) - store <32 x float> %vals, <32 x float>* %a + %vals = call <32 x float> @llvm.masked.gather.v32f32(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x float> undef) + store <32 x float> %vals, ptr %a ret void } -define void @masked_gather_vec_plus_imm(<32 x float>* %a, <32 x i8*>* %b) vscale_range(16,0) #0 { +define void @masked_gather_vec_plus_imm(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_gather_vec_plus_imm: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1186,17 +1186,17 @@ define void @masked_gather_vec_plus_imm(<32 x float>* %a, <32 x i8*>* %b) vscale ; CHECK-NEXT: ld1w { z0.d }, p0/z, [z1.d, #4] ; CHECK-NEXT: st1w { z0.d }, p1, [x0] ; CHECK-NEXT: ret - %cvals = load <32 x float>, <32 x float>* %a - %bases = load <32 x i8*>, <32 x i8*>* %b - %byte_ptrs = getelementptr i8, <32 x i8*> %bases, i64 4 - %ptrs = bitcast <32 x i8*> %byte_ptrs to <32 x float*> + %cvals = load <32 x float>, ptr %a + %bases = load <32 x ptr>, ptr %b + %byte_ptrs = getelementptr i8, <32 x ptr> %bases, i64 4 + %ptrs = bitcast <32 x ptr> %byte_ptrs to <32 x ptr> %mask = fcmp oeq <32 x float> %cvals, zeroinitializer - %vals = call <32 x float> @llvm.masked.gather.v32f32(<32 x float*> %ptrs, i32 8, <32 x i1> %mask, <32 x float> undef) - store <32 x float> %vals, <32 x float>* %a + %vals = call <32 x float> @llvm.masked.gather.v32f32(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x float> undef) + store <32 x float> %vals, ptr %a ret void } -define void @masked_gather_passthru(<32 x float>* %a, <32 x float*>* %b, <32 x float>* %c) vscale_range(16,0) #0 { +define void @masked_gather_passthru(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_gather_passthru: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1211,16 +1211,16 @@ define void @masked_gather_passthru(<32 x float>* %a, <32 x float*>* %b, <32 x f ; CHECK-NEXT: mov z0.s, p1/m, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %cvals = load <32 x float>, <32 x float>* %a - %ptrs = load <32 x float*>, <32 x float*>* %b - %passthru = load <32 x float>, <32 x float>* %c + %cvals = load <32 x float>, ptr %a + %ptrs = load <32 x ptr>, ptr %b + %passthru = load <32 x float>, ptr %c %mask = fcmp oeq <32 x float> %cvals, zeroinitializer - %vals = call <32 x float> @llvm.masked.gather.v32f32(<32 x float*> %ptrs, i32 8, <32 x i1> %mask, <32 x float> %passthru) - store <32 x float> %vals, <32 x float>* %a + %vals = call <32 x float> @llvm.masked.gather.v32f32(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x float> %passthru) + store <32 x float> %vals, ptr %a ret void } -define void @masked_gather_passthru_0(<32 x float>* %a, <32 x float*>* %b) vscale_range(16,0) #0 { +define void @masked_gather_passthru_0(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_gather_passthru_0: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1232,56 +1232,56 @@ define void @masked_gather_passthru_0(<32 x float>* %a, <32 x float*>* %b) vscal ; CHECK-NEXT: ld1w { z0.d }, p0/z, [z1.d] ; CHECK-NEXT: st1w { z0.d }, p1, [x0] ; CHECK-NEXT: ret - %cvals = load <32 x float>, <32 x float>* %a - %ptrs = load <32 x float*>, <32 x float*>* %b + %cvals = load <32 x float>, ptr %a + %ptrs = load <32 x ptr>, ptr %b %mask = fcmp oeq <32 x float> %cvals, zeroinitializer - %vals = call <32 x float> @llvm.masked.gather.v32f32(<32 x float*> %ptrs, i32 8, <32 x i1> %mask, <32 x float> zeroinitializer) - store <32 x float> %vals, <32 x float>* %a + %vals = call <32 x float> @llvm.masked.gather.v32f32(<32 x ptr> %ptrs, i32 8, <32 x i1> %mask, <32 x float> zeroinitializer) + store <32 x float> %vals, ptr %a ret void } -declare <2 x i8> @llvm.masked.gather.v2i8(<2 x i8*>, i32, <2 x i1>, <2 x i8>) -declare <4 x i8> @llvm.masked.gather.v4i8(<4 x i8*>, i32, <4 x i1>, <4 x i8>) -declare <8 x i8> @llvm.masked.gather.v8i8(<8 x i8*>, i32, <8 x i1>, <8 x i8>) -declare <16 x i8> @llvm.masked.gather.v16i8(<16 x i8*>, i32, <16 x i1>, <16 x i8>) -declare <32 x i8> @llvm.masked.gather.v32i8(<32 x i8*>, i32, <32 x i1>, <32 x i8>) - -declare <2 x i16> @llvm.masked.gather.v2i16(<2 x i16*>, i32, <2 x i1>, <2 x i16>) -declare <4 x i16> @llvm.masked.gather.v4i16(<4 x i16*>, i32, <4 x i1>, <4 x i16>) -declare <8 x i16> @llvm.masked.gather.v8i16(<8 x i16*>, i32, <8 x i1>, <8 x i16>) -declare <16 x i16> @llvm.masked.gather.v16i16(<16 x i16*>, i32, <16 x i1>, <16 x i16>) -declare <32 x i16> @llvm.masked.gather.v32i16(<32 x i16*>, i32, <32 x i1>, <32 x i16>) - -declare <2 x i32> @llvm.masked.gather.v2i32(<2 x i32*>, i32, <2 x i1>, <2 x i32>) -declare <4 x i32> @llvm.masked.gather.v4i32(<4 x i32*>, i32, <4 x i1>, <4 x i32>) -declare <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*>, i32, <8 x i1>, <8 x i32>) -declare <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*>, i32, <16 x i1>, <16 x i32>) -declare <32 x i32> @llvm.masked.gather.v32i32(<32 x i32*>, i32, <32 x i1>, <32 x i32>) - -declare <1 x i64> @llvm.masked.gather.v1i64(<1 x i64*>, i32, <1 x i1>, <1 x i64>) -declare <2 x i64> @llvm.masked.gather.v2i64(<2 x i64*>, i32, <2 x i1>, <2 x i64>) -declare <4 x i64> @llvm.masked.gather.v4i64(<4 x i64*>, i32, <4 x i1>, <4 x i64>) -declare <8 x i64> @llvm.masked.gather.v8i64(<8 x i64*>, i32, <8 x i1>, <8 x i64>) -declare <16 x i64> @llvm.masked.gather.v16i64(<16 x i64*>, i32, <16 x i1>, <16 x i64>) -declare <32 x i64> @llvm.masked.gather.v32i64(<32 x i64*>, i32, <32 x i1>, <32 x i64>) - -declare <2 x half> @llvm.masked.gather.v2f16(<2 x half*>, i32, <2 x i1>, <2 x half>) -declare <4 x half> @llvm.masked.gather.v4f16(<4 x half*>, i32, <4 x i1>, <4 x half>) -declare <8 x half> @llvm.masked.gather.v8f16(<8 x half*>, i32, <8 x i1>, <8 x half>) -declare <16 x half> @llvm.masked.gather.v16f16(<16 x half*>, i32, <16 x i1>, <16 x half>) -declare <32 x half> @llvm.masked.gather.v32f16(<32 x half*>, i32, <32 x i1>, <32 x half>) - -declare <2 x float> @llvm.masked.gather.v2f32(<2 x float*>, i32, <2 x i1>, <2 x float>) -declare <4 x float> @llvm.masked.gather.v4f32(<4 x float*>, i32, <4 x i1>, <4 x float>) -declare <8 x float> @llvm.masked.gather.v8f32(<8 x float*>, i32, <8 x i1>, <8 x float>) -declare <16 x float> @llvm.masked.gather.v16f32(<16 x float*>, i32, <16 x i1>, <16 x float>) -declare <32 x float> @llvm.masked.gather.v32f32(<32 x float*>, i32, <32 x i1>, <32 x float>) - -declare <1 x double> @llvm.masked.gather.v1f64(<1 x double*>, i32, <1 x i1>, <1 x double>) -declare <2 x double> @llvm.masked.gather.v2f64(<2 x double*>, i32, <2 x i1>, <2 x double>) -declare <4 x double> @llvm.masked.gather.v4f64(<4 x double*>, i32, <4 x i1>, <4 x double>) -declare <8 x double> @llvm.masked.gather.v8f64(<8 x double*>, i32, <8 x i1>, <8 x double>) -declare <16 x double> @llvm.masked.gather.v16f64(<16 x double*>, i32, <16 x i1>, <16 x double>) -declare <32 x double> @llvm.masked.gather.v32f64(<32 x double*>, i32, <32 x i1>, <32 x double>) +declare <2 x i8> @llvm.masked.gather.v2i8(<2 x ptr>, i32, <2 x i1>, <2 x i8>) +declare <4 x i8> @llvm.masked.gather.v4i8(<4 x ptr>, i32, <4 x i1>, <4 x i8>) +declare <8 x i8> @llvm.masked.gather.v8i8(<8 x ptr>, i32, <8 x i1>, <8 x i8>) +declare <16 x i8> @llvm.masked.gather.v16i8(<16 x ptr>, i32, <16 x i1>, <16 x i8>) +declare <32 x i8> @llvm.masked.gather.v32i8(<32 x ptr>, i32, <32 x i1>, <32 x i8>) + +declare <2 x i16> @llvm.masked.gather.v2i16(<2 x ptr>, i32, <2 x i1>, <2 x i16>) +declare <4 x i16> @llvm.masked.gather.v4i16(<4 x ptr>, i32, <4 x i1>, <4 x i16>) +declare <8 x i16> @llvm.masked.gather.v8i16(<8 x ptr>, i32, <8 x i1>, <8 x i16>) +declare <16 x i16> @llvm.masked.gather.v16i16(<16 x ptr>, i32, <16 x i1>, <16 x i16>) +declare <32 x i16> @llvm.masked.gather.v32i16(<32 x ptr>, i32, <32 x i1>, <32 x i16>) + +declare <2 x i32> @llvm.masked.gather.v2i32(<2 x ptr>, i32, <2 x i1>, <2 x i32>) +declare <4 x i32> @llvm.masked.gather.v4i32(<4 x ptr>, i32, <4 x i1>, <4 x i32>) +declare <8 x i32> @llvm.masked.gather.v8i32(<8 x ptr>, i32, <8 x i1>, <8 x i32>) +declare <16 x i32> @llvm.masked.gather.v16i32(<16 x ptr>, i32, <16 x i1>, <16 x i32>) +declare <32 x i32> @llvm.masked.gather.v32i32(<32 x ptr>, i32, <32 x i1>, <32 x i32>) + +declare <1 x i64> @llvm.masked.gather.v1i64(<1 x ptr>, i32, <1 x i1>, <1 x i64>) +declare <2 x i64> @llvm.masked.gather.v2i64(<2 x ptr>, i32, <2 x i1>, <2 x i64>) +declare <4 x i64> @llvm.masked.gather.v4i64(<4 x ptr>, i32, <4 x i1>, <4 x i64>) +declare <8 x i64> @llvm.masked.gather.v8i64(<8 x ptr>, i32, <8 x i1>, <8 x i64>) +declare <16 x i64> @llvm.masked.gather.v16i64(<16 x ptr>, i32, <16 x i1>, <16 x i64>) +declare <32 x i64> @llvm.masked.gather.v32i64(<32 x ptr>, i32, <32 x i1>, <32 x i64>) + +declare <2 x half> @llvm.masked.gather.v2f16(<2 x ptr>, i32, <2 x i1>, <2 x half>) +declare <4 x half> @llvm.masked.gather.v4f16(<4 x ptr>, i32, <4 x i1>, <4 x half>) +declare <8 x half> @llvm.masked.gather.v8f16(<8 x ptr>, i32, <8 x i1>, <8 x half>) +declare <16 x half> @llvm.masked.gather.v16f16(<16 x ptr>, i32, <16 x i1>, <16 x half>) +declare <32 x half> @llvm.masked.gather.v32f16(<32 x ptr>, i32, <32 x i1>, <32 x half>) + +declare <2 x float> @llvm.masked.gather.v2f32(<2 x ptr>, i32, <2 x i1>, <2 x float>) +declare <4 x float> @llvm.masked.gather.v4f32(<4 x ptr>, i32, <4 x i1>, <4 x float>) +declare <8 x float> @llvm.masked.gather.v8f32(<8 x ptr>, i32, <8 x i1>, <8 x float>) +declare <16 x float> @llvm.masked.gather.v16f32(<16 x ptr>, i32, <16 x i1>, <16 x float>) +declare <32 x float> @llvm.masked.gather.v32f32(<32 x ptr>, i32, <32 x i1>, <32 x float>) + +declare <1 x double> @llvm.masked.gather.v1f64(<1 x ptr>, i32, <1 x i1>, <1 x double>) +declare <2 x double> @llvm.masked.gather.v2f64(<2 x ptr>, i32, <2 x i1>, <2 x double>) +declare <4 x double> @llvm.masked.gather.v4f64(<4 x ptr>, i32, <4 x i1>, <4 x double>) +declare <8 x double> @llvm.masked.gather.v8f64(<8 x ptr>, i32, <8 x i1>, <8 x double>) +declare <16 x double> @llvm.masked.gather.v16f64(<16 x ptr>, i32, <16 x i1>, <16 x double>) +declare <32 x double> @llvm.masked.gather.v32f64(<32 x ptr>, i32, <32 x i1>, <32 x double>) attributes #0 = { "target-features"="+sve" } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll index a602d64..eb396ca 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll @@ -9,7 +9,7 @@ target triple = "aarch64-unknown-linux-gnu" ; Masked Loads ; -define <2 x half> @masked_load_v2f16(<2 x half>* %ap, <2 x half>* %bp) vscale_range(2,0) #0 { +define <2 x half> @masked_load_v2f16(ptr %ap, ptr %bp) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_load_v2f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr s1, [x0] @@ -26,14 +26,14 @@ define <2 x half> @masked_load_v2f16(<2 x half>* %ap, <2 x half>* %bp) vscale_ra ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %a = load <2 x half>, <2 x half>* %ap - %b = load <2 x half>, <2 x half>* %bp + %a = load <2 x half>, ptr %ap + %b = load <2 x half>, ptr %bp %mask = fcmp oeq <2 x half> %a, %b - %load = call <2 x half> @llvm.masked.load.v2f16(<2 x half>* %ap, i32 8, <2 x i1> %mask, <2 x half> zeroinitializer) + %load = call <2 x half> @llvm.masked.load.v2f16(ptr %ap, i32 8, <2 x i1> %mask, <2 x half> zeroinitializer) ret <2 x half> %load } -define <2 x float> @masked_load_v2f32(<2 x float>* %ap, <2 x float>* %bp) vscale_range(2,0) #0 { +define <2 x float> @masked_load_v2f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_load_v2f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -44,14 +44,14 @@ define <2 x float> @masked_load_v2f32(<2 x float>* %ap, <2 x float>* %bp) vscale ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %a = load <2 x float>, <2 x float>* %ap - %b = load <2 x float>, <2 x float>* %bp + %a = load <2 x float>, ptr %ap + %b = load <2 x float>, ptr %bp %mask = fcmp oeq <2 x float> %a, %b - %load = call <2 x float> @llvm.masked.load.v2f32(<2 x float>* %ap, i32 8, <2 x i1> %mask, <2 x float> zeroinitializer) + %load = call <2 x float> @llvm.masked.load.v2f32(ptr %ap, i32 8, <2 x i1> %mask, <2 x float> zeroinitializer) ret <2 x float> %load } -define <4 x float> @masked_load_v4f32(<4 x float>* %ap, <4 x float>* %bp) vscale_range(2,0) #0 { +define <4 x float> @masked_load_v4f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_load_v4f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -62,14 +62,14 @@ define <4 x float> @masked_load_v4f32(<4 x float>* %ap, <4 x float>* %bp) vscale ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret - %a = load <4 x float>, <4 x float>* %ap - %b = load <4 x float>, <4 x float>* %bp + %a = load <4 x float>, ptr %ap + %b = load <4 x float>, ptr %bp %mask = fcmp oeq <4 x float> %a, %b - %load = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %ap, i32 8, <4 x i1> %mask, <4 x float> zeroinitializer) + %load = call <4 x float> @llvm.masked.load.v4f32(ptr %ap, i32 8, <4 x i1> %mask, <4 x float> zeroinitializer) ret <4 x float> %load } -define <8 x float> @masked_load_v8f32(<8 x float>* %ap, <8 x float>* %bp) vscale_range(2,0) #0 { +define <8 x float> @masked_load_v8f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_load_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -79,14 +79,14 @@ define <8 x float> @masked_load_v8f32(<8 x float>* %ap, <8 x float>* %bp) vscale ; CHECK-NEXT: ld1w { z0.s }, p1/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x8] ; CHECK-NEXT: ret - %a = load <8 x float>, <8 x float>* %ap - %b = load <8 x float>, <8 x float>* %bp + %a = load <8 x float>, ptr %ap + %b = load <8 x float>, ptr %bp %mask = fcmp oeq <8 x float> %a, %b - %load = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %ap, i32 8, <8 x i1> %mask, <8 x float> zeroinitializer) + %load = call <8 x float> @llvm.masked.load.v8f32(ptr %ap, i32 8, <8 x i1> %mask, <8 x float> zeroinitializer) ret <8 x float> %load } -define <16 x float> @masked_load_v16f32(<16 x float>* %ap, <16 x float>* %bp) #0 { +define <16 x float> @masked_load_v16f32(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #8 @@ -112,14 +112,14 @@ define <16 x float> @masked_load_v16f32(<16 x float>* %ap, <16 x float>* %bp) #0 ; VBITS_GE_512-NEXT: ld1w { z0.s }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %a = load <16 x float>, <16 x float>* %ap - %b = load <16 x float>, <16 x float>* %bp + %a = load <16 x float>, ptr %ap + %b = load <16 x float>, ptr %bp %mask = fcmp oeq <16 x float> %a, %b - %load = call <16 x float> @llvm.masked.load.v16f32(<16 x float>* %ap, i32 8, <16 x i1> %mask, <16 x float> zeroinitializer) + %load = call <16 x float> @llvm.masked.load.v16f32(ptr %ap, i32 8, <16 x i1> %mask, <16 x float> zeroinitializer) ret <16 x float> %load } -define <32 x float> @masked_load_v32f32(<32 x float>* %ap, <32 x float>* %bp) vscale_range(8,0) #0 { +define <32 x float> @masked_load_v32f32(ptr %ap, ptr %bp) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_load_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -129,14 +129,14 @@ define <32 x float> @masked_load_v32f32(<32 x float>* %ap, <32 x float>* %bp) vs ; CHECK-NEXT: ld1w { z0.s }, p1/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x8] ; CHECK-NEXT: ret - %a = load <32 x float>, <32 x float>* %ap - %b = load <32 x float>, <32 x float>* %bp + %a = load <32 x float>, ptr %ap + %b = load <32 x float>, ptr %bp %mask = fcmp oeq <32 x float> %a, %b - %load = call <32 x float> @llvm.masked.load.v32f32(<32 x float>* %ap, i32 8, <32 x i1> %mask, <32 x float> zeroinitializer) + %load = call <32 x float> @llvm.masked.load.v32f32(ptr %ap, i32 8, <32 x i1> %mask, <32 x float> zeroinitializer) ret <32 x float> %load } -define <64 x float> @masked_load_v64f32(<64 x float>* %ap, <64 x float>* %bp) vscale_range(16,0) #0 { +define <64 x float> @masked_load_v64f32(ptr %ap, ptr %bp) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_load_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -146,14 +146,14 @@ define <64 x float> @masked_load_v64f32(<64 x float>* %ap, <64 x float>* %bp) vs ; CHECK-NEXT: ld1w { z0.s }, p1/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x8] ; CHECK-NEXT: ret - %a = load <64 x float>, <64 x float>* %ap - %b = load <64 x float>, <64 x float>* %bp + %a = load <64 x float>, ptr %ap + %b = load <64 x float>, ptr %bp %mask = fcmp oeq <64 x float> %a, %b - %load = call <64 x float> @llvm.masked.load.v64f32(<64 x float>* %ap, i32 8, <64 x i1> %mask, <64 x float> zeroinitializer) + %load = call <64 x float> @llvm.masked.load.v64f32(ptr %ap, i32 8, <64 x i1> %mask, <64 x float> zeroinitializer) ret <64 x float> %load } -define <64 x i8> @masked_load_v64i8(<64 x i8>* %ap, <64 x i8>* %bp) #0 { +define <64 x i8> @masked_load_v64i8(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w9, #32 @@ -179,14 +179,14 @@ define <64 x i8> @masked_load_v64i8(<64 x i8>* %ap, <64 x i8>* %bp) #0 { ; VBITS_GE_512-NEXT: ld1b { z0.b }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %a = load <64 x i8>, <64 x i8>* %ap - %b = load <64 x i8>, <64 x i8>* %bp + %a = load <64 x i8>, ptr %ap + %b = load <64 x i8>, ptr %bp %mask = icmp eq <64 x i8> %a, %b - %load = call <64 x i8> @llvm.masked.load.v64i8(<64 x i8>* %ap, i32 8, <64 x i1> %mask, <64 x i8> undef) + %load = call <64 x i8> @llvm.masked.load.v64i8(ptr %ap, i32 8, <64 x i1> %mask, <64 x i8> undef) ret <64 x i8> %load } -define <32 x i16> @masked_load_v32i16(<32 x i16>* %ap, <32 x i16>* %bp) #0 { +define <32 x i16> @masked_load_v32i16(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #16 @@ -212,14 +212,14 @@ define <32 x i16> @masked_load_v32i16(<32 x i16>* %ap, <32 x i16>* %bp) #0 { ; VBITS_GE_512-NEXT: ld1h { z0.h }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %a = load <32 x i16>, <32 x i16>* %ap - %b = load <32 x i16>, <32 x i16>* %bp + %a = load <32 x i16>, ptr %ap + %b = load <32 x i16>, ptr %bp %mask = icmp eq <32 x i16> %a, %b - %load = call <32 x i16> @llvm.masked.load.v32i16(<32 x i16>* %ap, i32 8, <32 x i1> %mask, <32 x i16> undef) + %load = call <32 x i16> @llvm.masked.load.v32i16(ptr %ap, i32 8, <32 x i1> %mask, <32 x i16> undef) ret <32 x i16> %load } -define <16 x i32> @masked_load_v16i32(<16 x i32>* %ap, <16 x i32>* %bp) #0 { +define <16 x i32> @masked_load_v16i32(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #8 @@ -245,14 +245,14 @@ define <16 x i32> @masked_load_v16i32(<16 x i32>* %ap, <16 x i32>* %bp) #0 { ; VBITS_GE_512-NEXT: ld1w { z0.s }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %a = load <16 x i32>, <16 x i32>* %ap - %b = load <16 x i32>, <16 x i32>* %bp + %a = load <16 x i32>, ptr %ap + %b = load <16 x i32>, ptr %bp %mask = icmp eq <16 x i32> %a, %b - %load = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %ap, i32 8, <16 x i1> %mask, <16 x i32> undef) + %load = call <16 x i32> @llvm.masked.load.v16i32(ptr %ap, i32 8, <16 x i1> %mask, <16 x i32> undef) ret <16 x i32> %load } -define <8 x i64> @masked_load_v8i64(<8 x i64>* %ap, <8 x i64>* %bp) #0 { +define <8 x i64> @masked_load_v8i64(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #4 @@ -278,14 +278,14 @@ define <8 x i64> @masked_load_v8i64(<8 x i64>* %ap, <8 x i64>* %bp) #0 { ; VBITS_GE_512-NEXT: ld1d { z0.d }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %a = load <8 x i64>, <8 x i64>* %ap - %b = load <8 x i64>, <8 x i64>* %bp + %a = load <8 x i64>, ptr %ap + %b = load <8 x i64>, ptr %bp %mask = icmp eq <8 x i64> %a, %b - %load = call <8 x i64> @llvm.masked.load.v8i64(<8 x i64>* %ap, i32 8, <8 x i1> %mask, <8 x i64> undef) + %load = call <8 x i64> @llvm.masked.load.v8i64(ptr %ap, i32 8, <8 x i1> %mask, <8 x i64> undef) ret <8 x i64> %load } -define <8 x i64> @masked_load_passthru_v8i64(<8 x i64>* %ap, <8 x i64>* %bp) #0 { +define <8 x i64> @masked_load_passthru_v8i64(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_passthru_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #4 @@ -314,14 +314,14 @@ define <8 x i64> @masked_load_passthru_v8i64(<8 x i64>* %ap, <8 x i64>* %bp) #0 ; VBITS_GE_512-NEXT: sel z0.d, p1, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %a = load <8 x i64>, <8 x i64>* %ap - %b = load <8 x i64>, <8 x i64>* %bp + %a = load <8 x i64>, ptr %ap + %b = load <8 x i64>, ptr %bp %mask = icmp eq <8 x i64> %a, %b - %load = call <8 x i64> @llvm.masked.load.v8i64(<8 x i64>* %ap, i32 8, <8 x i1> %mask, <8 x i64> %b) + %load = call <8 x i64> @llvm.masked.load.v8i64(ptr %ap, i32 8, <8 x i1> %mask, <8 x i64> %b) ret <8 x i64> %load } -define <8 x double> @masked_load_passthru_v8f64(<8 x double>* %ap, <8 x double>* %bp) #0 { +define <8 x double> @masked_load_passthru_v8f64(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_passthru_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #4 @@ -350,14 +350,14 @@ define <8 x double> @masked_load_passthru_v8f64(<8 x double>* %ap, <8 x double>* ; VBITS_GE_512-NEXT: sel z0.d, p1, z0.d, z1.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %a = load <8 x double>, <8 x double>* %ap - %b = load <8 x double>, <8 x double>* %bp + %a = load <8 x double>, ptr %ap + %b = load <8 x double>, ptr %bp %mask = fcmp oeq <8 x double> %a, %b - %load = call <8 x double> @llvm.masked.load.v8f64(<8 x double>* %ap, i32 8, <8 x i1> %mask, <8 x double> %b) + %load = call <8 x double> @llvm.masked.load.v8f64(ptr %ap, i32 8, <8 x i1> %mask, <8 x double> %b) ret <8 x double> %load } -define <32 x i16> @masked_load_sext_v32i8i16(<32 x i8>* %ap, <32 x i8>* %bp) #0 { +define <32 x i16> @masked_load_sext_v32i8i16(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_sext_v32i8i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.b, vl32 @@ -381,14 +381,14 @@ define <32 x i16> @masked_load_sext_v32i8i16(<32 x i8>* %ap, <32 x i8>* %bp) #0 ; VBITS_GE_512-NEXT: ld1sb { z0.h }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <32 x i8>, <32 x i8>* %bp + %b = load <32 x i8>, ptr %bp %mask = icmp eq <32 x i8> %b, zeroinitializer - %load = call <32 x i8> @llvm.masked.load.v32i8(<32 x i8>* %ap, i32 8, <32 x i1> %mask, <32 x i8> undef) + %load = call <32 x i8> @llvm.masked.load.v32i8(ptr %ap, i32 8, <32 x i1> %mask, <32 x i8> undef) %ext = sext <32 x i8> %load to <32 x i16> ret <32 x i16> %ext } -define <16 x i32> @masked_load_sext_v16i8i32(<16 x i8>* %ap, <16 x i8>* %bp) #0 { +define <16 x i32> @masked_load_sext_v16i8i32(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_sext_v16i8i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ldr q0, [x1] @@ -415,14 +415,14 @@ define <16 x i32> @masked_load_sext_v16i8i32(<16 x i8>* %ap, <16 x i8>* %bp) #0 ; VBITS_GE_512-NEXT: ld1sb { z0.s }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <16 x i8>, <16 x i8>* %bp + %b = load <16 x i8>, ptr %bp %mask = icmp eq <16 x i8> %b, zeroinitializer - %load = call <16 x i8> @llvm.masked.load.v16i8(<16 x i8>* %ap, i32 8, <16 x i1> %mask, <16 x i8> undef) + %load = call <16 x i8> @llvm.masked.load.v16i8(ptr %ap, i32 8, <16 x i1> %mask, <16 x i8> undef) %ext = sext <16 x i8> %load to <16 x i32> ret <16 x i32> %ext } -define <8 x i64> @masked_load_sext_v8i8i64(<8 x i8>* %ap, <8 x i8>* %bp) #0 { +define <8 x i64> @masked_load_sext_v8i8i64(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_sext_v8i8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ldr d0, [x1] @@ -450,14 +450,14 @@ define <8 x i64> @masked_load_sext_v8i8i64(<8 x i8>* %ap, <8 x i8>* %bp) #0 { ; VBITS_GE_512-NEXT: ld1sb { z0.d }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <8 x i8>, <8 x i8>* %bp + %b = load <8 x i8>, ptr %bp %mask = icmp eq <8 x i8> %b, zeroinitializer - %load = call <8 x i8> @llvm.masked.load.v8i8(<8 x i8>* %ap, i32 8, <8 x i1> %mask, <8 x i8> undef) + %load = call <8 x i8> @llvm.masked.load.v8i8(ptr %ap, i32 8, <8 x i1> %mask, <8 x i8> undef) %ext = sext <8 x i8> %load to <8 x i64> ret <8 x i64> %ext } -define <16 x i32> @masked_load_sext_v16i16i32(<16 x i16>* %ap, <16 x i16>* %bp) #0 { +define <16 x i32> @masked_load_sext_v16i16i32(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_sext_v16i16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.h, vl16 @@ -481,14 +481,14 @@ define <16 x i32> @masked_load_sext_v16i16i32(<16 x i16>* %ap, <16 x i16>* %bp) ; VBITS_GE_512-NEXT: ld1sh { z0.s }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <16 x i16>, <16 x i16>* %bp + %b = load <16 x i16>, ptr %bp %mask = icmp eq <16 x i16> %b, zeroinitializer - %load = call <16 x i16> @llvm.masked.load.v16i16(<16 x i16>* %ap, i32 8, <16 x i1> %mask, <16 x i16> undef) + %load = call <16 x i16> @llvm.masked.load.v16i16(ptr %ap, i32 8, <16 x i1> %mask, <16 x i16> undef) %ext = sext <16 x i16> %load to <16 x i32> ret <16 x i32> %ext } -define <8 x i64> @masked_load_sext_v8i16i64(<8 x i16>* %ap, <8 x i16>* %bp) #0 { +define <8 x i64> @masked_load_sext_v8i16i64(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_sext_v8i16i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ldr q0, [x1] @@ -515,14 +515,14 @@ define <8 x i64> @masked_load_sext_v8i16i64(<8 x i16>* %ap, <8 x i16>* %bp) #0 { ; VBITS_GE_512-NEXT: ld1sh { z0.d }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <8 x i16>, <8 x i16>* %bp + %b = load <8 x i16>, ptr %bp %mask = icmp eq <8 x i16> %b, zeroinitializer - %load = call <8 x i16> @llvm.masked.load.v8i16(<8 x i16>* %ap, i32 8, <8 x i1> %mask, <8 x i16> undef) + %load = call <8 x i16> @llvm.masked.load.v8i16(ptr %ap, i32 8, <8 x i1> %mask, <8 x i16> undef) %ext = sext <8 x i16> %load to <8 x i64> ret <8 x i64> %ext } -define <8 x i64> @masked_load_sext_v8i32i64(<8 x i32>* %ap, <8 x i32>* %bp) #0 { +define <8 x i64> @masked_load_sext_v8i32i64(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_sext_v8i32i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.s, vl8 @@ -546,14 +546,14 @@ define <8 x i64> @masked_load_sext_v8i32i64(<8 x i32>* %ap, <8 x i32>* %bp) #0 { ; VBITS_GE_512-NEXT: ld1sw { z0.d }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <8 x i32>, <8 x i32>* %bp + %b = load <8 x i32>, ptr %bp %mask = icmp eq <8 x i32> %b, zeroinitializer - %load = call <8 x i32> @llvm.masked.load.v8i32(<8 x i32>* %ap, i32 8, <8 x i1> %mask, <8 x i32> undef) + %load = call <8 x i32> @llvm.masked.load.v8i32(ptr %ap, i32 8, <8 x i1> %mask, <8 x i32> undef) %ext = sext <8 x i32> %load to <8 x i64> ret <8 x i64> %ext } -define <32 x i16> @masked_load_zext_v32i8i16(<32 x i8>* %ap, <32 x i8>* %bp) #0 { +define <32 x i16> @masked_load_zext_v32i8i16(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_zext_v32i8i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.b, vl32 @@ -577,14 +577,14 @@ define <32 x i16> @masked_load_zext_v32i8i16(<32 x i8>* %ap, <32 x i8>* %bp) #0 ; VBITS_GE_512-NEXT: ld1b { z0.h }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <32 x i8>, <32 x i8>* %bp + %b = load <32 x i8>, ptr %bp %mask = icmp eq <32 x i8> %b, zeroinitializer - %load = call <32 x i8> @llvm.masked.load.v32i8(<32 x i8>* %ap, i32 8, <32 x i1> %mask, <32 x i8> undef) + %load = call <32 x i8> @llvm.masked.load.v32i8(ptr %ap, i32 8, <32 x i1> %mask, <32 x i8> undef) %ext = zext <32 x i8> %load to <32 x i16> ret <32 x i16> %ext } -define <16 x i32> @masked_load_zext_v16i8i32(<16 x i8>* %ap, <16 x i8>* %bp) #0 { +define <16 x i32> @masked_load_zext_v16i8i32(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_zext_v16i8i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ldr q0, [x1] @@ -611,14 +611,14 @@ define <16 x i32> @masked_load_zext_v16i8i32(<16 x i8>* %ap, <16 x i8>* %bp) #0 ; VBITS_GE_512-NEXT: ld1b { z0.s }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <16 x i8>, <16 x i8>* %bp + %b = load <16 x i8>, ptr %bp %mask = icmp eq <16 x i8> %b, zeroinitializer - %load = call <16 x i8> @llvm.masked.load.v16i8(<16 x i8>* %ap, i32 8, <16 x i1> %mask, <16 x i8> undef) + %load = call <16 x i8> @llvm.masked.load.v16i8(ptr %ap, i32 8, <16 x i1> %mask, <16 x i8> undef) %ext = zext <16 x i8> %load to <16 x i32> ret <16 x i32> %ext } -define <8 x i64> @masked_load_zext_v8i8i64(<8 x i8>* %ap, <8 x i8>* %bp) #0 { +define <8 x i64> @masked_load_zext_v8i8i64(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_zext_v8i8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ldr d0, [x1] @@ -646,14 +646,14 @@ define <8 x i64> @masked_load_zext_v8i8i64(<8 x i8>* %ap, <8 x i8>* %bp) #0 { ; VBITS_GE_512-NEXT: ld1b { z0.d }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <8 x i8>, <8 x i8>* %bp + %b = load <8 x i8>, ptr %bp %mask = icmp eq <8 x i8> %b, zeroinitializer - %load = call <8 x i8> @llvm.masked.load.v8i8(<8 x i8>* %ap, i32 8, <8 x i1> %mask, <8 x i8> undef) + %load = call <8 x i8> @llvm.masked.load.v8i8(ptr %ap, i32 8, <8 x i1> %mask, <8 x i8> undef) %ext = zext <8 x i8> %load to <8 x i64> ret <8 x i64> %ext } -define <16 x i32> @masked_load_zext_v16i16i32(<16 x i16>* %ap, <16 x i16>* %bp) #0 { +define <16 x i32> @masked_load_zext_v16i16i32(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_zext_v16i16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.h, vl16 @@ -677,14 +677,14 @@ define <16 x i32> @masked_load_zext_v16i16i32(<16 x i16>* %ap, <16 x i16>* %bp) ; VBITS_GE_512-NEXT: ld1h { z0.s }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <16 x i16>, <16 x i16>* %bp + %b = load <16 x i16>, ptr %bp %mask = icmp eq <16 x i16> %b, zeroinitializer - %load = call <16 x i16> @llvm.masked.load.v16i16(<16 x i16>* %ap, i32 8, <16 x i1> %mask, <16 x i16> undef) + %load = call <16 x i16> @llvm.masked.load.v16i16(ptr %ap, i32 8, <16 x i1> %mask, <16 x i16> undef) %ext = zext <16 x i16> %load to <16 x i32> ret <16 x i32> %ext } -define <8 x i64> @masked_load_zext_v8i16i64(<8 x i16>* %ap, <8 x i16>* %bp) #0 { +define <8 x i64> @masked_load_zext_v8i16i64(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_zext_v8i16i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ldr q0, [x1] @@ -711,14 +711,14 @@ define <8 x i64> @masked_load_zext_v8i16i64(<8 x i16>* %ap, <8 x i16>* %bp) #0 { ; VBITS_GE_512-NEXT: ld1h { z0.d }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <8 x i16>, <8 x i16>* %bp + %b = load <8 x i16>, ptr %bp %mask = icmp eq <8 x i16> %b, zeroinitializer - %load = call <8 x i16> @llvm.masked.load.v8i16(<8 x i16>* %ap, i32 8, <8 x i1> %mask, <8 x i16> undef) + %load = call <8 x i16> @llvm.masked.load.v8i16(ptr %ap, i32 8, <8 x i1> %mask, <8 x i16> undef) %ext = zext <8 x i16> %load to <8 x i64> ret <8 x i64> %ext } -define <8 x i64> @masked_load_zext_v8i32i64(<8 x i32>* %ap, <8 x i32>* %bp) #0 { +define <8 x i64> @masked_load_zext_v8i32i64(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_zext_v8i32i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.s, vl8 @@ -742,14 +742,14 @@ define <8 x i64> @masked_load_zext_v8i32i64(<8 x i32>* %ap, <8 x i32>* %bp) #0 { ; VBITS_GE_512-NEXT: ld1w { z0.d }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <8 x i32>, <8 x i32>* %bp + %b = load <8 x i32>, ptr %bp %mask = icmp eq <8 x i32> %b, zeroinitializer - %load = call <8 x i32> @llvm.masked.load.v8i32(<8 x i32>* %ap, i32 8, <8 x i1> %mask, <8 x i32> undef) + %load = call <8 x i32> @llvm.masked.load.v8i32(ptr %ap, i32 8, <8 x i1> %mask, <8 x i32> undef) %ext = zext <8 x i32> %load to <8 x i64> ret <8 x i64> %ext } -define <32 x i16> @masked_load_sext_v32i8i16_m16(<32 x i8>* %ap, <32 x i16>* %bp) #0 { +define <32 x i16> @masked_load_sext_v32i8i16_m16(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_sext_v32i8i16_m16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #16 @@ -782,14 +782,14 @@ define <32 x i16> @masked_load_sext_v32i8i16_m16(<32 x i8>* %ap, <32 x i16>* %bp ; VBITS_GE_512-NEXT: ld1sb { z0.h }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <32 x i16>, <32 x i16>* %bp + %b = load <32 x i16>, ptr %bp %mask = icmp eq <32 x i16> %b, zeroinitializer - %load = call <32 x i8> @llvm.masked.load.v32i8(<32 x i8>* %ap, i32 8, <32 x i1> %mask, <32 x i8> undef) + %load = call <32 x i8> @llvm.masked.load.v32i8(ptr %ap, i32 8, <32 x i1> %mask, <32 x i8> undef) %ext = sext <32 x i8> %load to <32 x i16> ret <32 x i16> %ext } -define <16 x i32> @masked_load_sext_v16i8i32_m32(<16 x i8>* %ap, <16 x i32>* %bp) #0 { +define <16 x i32> @masked_load_sext_v16i8i32_m32(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_sext_v16i8i32_m32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #8 @@ -825,14 +825,14 @@ define <16 x i32> @masked_load_sext_v16i8i32_m32(<16 x i8>* %ap, <16 x i32>* %bp ; VBITS_GE_512-NEXT: ld1sb { z0.s }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <16 x i32>, <16 x i32>* %bp + %b = load <16 x i32>, ptr %bp %mask = icmp eq <16 x i32> %b, zeroinitializer - %load = call <16 x i8> @llvm.masked.load.v16i8(<16 x i8>* %ap, i32 8, <16 x i1> %mask, <16 x i8> undef) + %load = call <16 x i8> @llvm.masked.load.v16i8(ptr %ap, i32 8, <16 x i1> %mask, <16 x i8> undef) %ext = sext <16 x i8> %load to <16 x i32> ret <16 x i32> %ext } -define <8 x i64> @masked_load_sext_v8i8i64_m64(<8 x i8>* %ap, <8 x i64>* %bp) #0 { +define <8 x i64> @masked_load_sext_v8i8i64_m64(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_sext_v8i8i64_m64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #4 @@ -870,14 +870,14 @@ define <8 x i64> @masked_load_sext_v8i8i64_m64(<8 x i8>* %ap, <8 x i64>* %bp) #0 ; VBITS_GE_512-NEXT: ld1sb { z0.d }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <8 x i64>, <8 x i64>* %bp + %b = load <8 x i64>, ptr %bp %mask = icmp eq <8 x i64> %b, zeroinitializer - %load = call <8 x i8> @llvm.masked.load.v8i8(<8 x i8>* %ap, i32 8, <8 x i1> %mask, <8 x i8> undef) + %load = call <8 x i8> @llvm.masked.load.v8i8(ptr %ap, i32 8, <8 x i1> %mask, <8 x i8> undef) %ext = sext <8 x i8> %load to <8 x i64> ret <8 x i64> %ext } -define <16 x i32> @masked_load_sext_v16i16i32_m32(<16 x i16>* %ap, <16 x i32>* %bp) #0 { +define <16 x i32> @masked_load_sext_v16i16i32_m32(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_sext_v16i16i32_m32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #8 @@ -912,14 +912,14 @@ define <16 x i32> @masked_load_sext_v16i16i32_m32(<16 x i16>* %ap, <16 x i32>* % ; VBITS_GE_512-NEXT: ld1sh { z0.s }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <16 x i32>, <16 x i32>* %bp + %b = load <16 x i32>, ptr %bp %mask = icmp eq <16 x i32> %b, zeroinitializer - %load = call <16 x i16> @llvm.masked.load.v16i16(<16 x i16>* %ap, i32 8, <16 x i1> %mask, <16 x i16> undef) + %load = call <16 x i16> @llvm.masked.load.v16i16(ptr %ap, i32 8, <16 x i1> %mask, <16 x i16> undef) %ext = sext <16 x i16> %load to <16 x i32> ret <16 x i32> %ext } -define <8 x i64> @masked_load_sext_v8i16i64_m64(<8 x i16>* %ap, <8 x i64>* %bp) #0 { +define <8 x i64> @masked_load_sext_v8i16i64_m64(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_sext_v8i16i64_m64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #4 @@ -955,14 +955,14 @@ define <8 x i64> @masked_load_sext_v8i16i64_m64(<8 x i16>* %ap, <8 x i64>* %bp) ; VBITS_GE_512-NEXT: ld1sh { z0.d }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <8 x i64>, <8 x i64>* %bp + %b = load <8 x i64>, ptr %bp %mask = icmp eq <8 x i64> %b, zeroinitializer - %load = call <8 x i16> @llvm.masked.load.v8i16(<8 x i16>* %ap, i32 8, <8 x i1> %mask, <8 x i16> undef) + %load = call <8 x i16> @llvm.masked.load.v8i16(ptr %ap, i32 8, <8 x i1> %mask, <8 x i16> undef) %ext = sext <8 x i16> %load to <8 x i64> ret <8 x i64> %ext } -define <8 x i64> @masked_load_sext_v8i32i64_m64(<8 x i32>* %ap, <8 x i64>* %bp) #0 { +define <8 x i64> @masked_load_sext_v8i32i64_m64(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_sext_v8i32i64_m64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #4 @@ -995,14 +995,14 @@ define <8 x i64> @masked_load_sext_v8i32i64_m64(<8 x i32>* %ap, <8 x i64>* %bp) ; VBITS_GE_512-NEXT: ld1sw { z0.d }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <8 x i64>, <8 x i64>* %bp + %b = load <8 x i64>, ptr %bp %mask = icmp eq <8 x i64> %b, zeroinitializer - %load = call <8 x i32> @llvm.masked.load.v8i32(<8 x i32>* %ap, i32 8, <8 x i1> %mask, <8 x i32> undef) + %load = call <8 x i32> @llvm.masked.load.v8i32(ptr %ap, i32 8, <8 x i1> %mask, <8 x i32> undef) %ext = sext <8 x i32> %load to <8 x i64> ret <8 x i64> %ext } -define <32 x i16> @masked_load_zext_v32i8i16_m16(<32 x i8>* %ap, <32 x i16>* %bp) #0 { +define <32 x i16> @masked_load_zext_v32i8i16_m16(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_zext_v32i8i16_m16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #16 @@ -1035,14 +1035,14 @@ define <32 x i16> @masked_load_zext_v32i8i16_m16(<32 x i8>* %ap, <32 x i16>* %bp ; VBITS_GE_512-NEXT: ld1b { z0.h }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <32 x i16>, <32 x i16>* %bp + %b = load <32 x i16>, ptr %bp %mask = icmp eq <32 x i16> %b, zeroinitializer - %load = call <32 x i8> @llvm.masked.load.v32i8(<32 x i8>* %ap, i32 8, <32 x i1> %mask, <32 x i8> undef) + %load = call <32 x i8> @llvm.masked.load.v32i8(ptr %ap, i32 8, <32 x i1> %mask, <32 x i8> undef) %ext = zext <32 x i8> %load to <32 x i16> ret <32 x i16> %ext } -define <16 x i32> @masked_load_zext_v16i8i32_m32(<16 x i8>* %ap, <16 x i32>* %bp) #0 { +define <16 x i32> @masked_load_zext_v16i8i32_m32(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_zext_v16i8i32_m32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #8 @@ -1078,14 +1078,14 @@ define <16 x i32> @masked_load_zext_v16i8i32_m32(<16 x i8>* %ap, <16 x i32>* %bp ; VBITS_GE_512-NEXT: ld1b { z0.s }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <16 x i32>, <16 x i32>* %bp + %b = load <16 x i32>, ptr %bp %mask = icmp eq <16 x i32> %b, zeroinitializer - %load = call <16 x i8> @llvm.masked.load.v16i8(<16 x i8>* %ap, i32 8, <16 x i1> %mask, <16 x i8> undef) + %load = call <16 x i8> @llvm.masked.load.v16i8(ptr %ap, i32 8, <16 x i1> %mask, <16 x i8> undef) %ext = zext <16 x i8> %load to <16 x i32> ret <16 x i32> %ext } -define <8 x i64> @masked_load_zext_v8i8i64_m64(<8 x i8>* %ap, <8 x i64>* %bp) #0 { +define <8 x i64> @masked_load_zext_v8i8i64_m64(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_zext_v8i8i64_m64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #4 @@ -1123,14 +1123,14 @@ define <8 x i64> @masked_load_zext_v8i8i64_m64(<8 x i8>* %ap, <8 x i64>* %bp) #0 ; VBITS_GE_512-NEXT: ld1b { z0.d }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <8 x i64>, <8 x i64>* %bp + %b = load <8 x i64>, ptr %bp %mask = icmp eq <8 x i64> %b, zeroinitializer - %load = call <8 x i8> @llvm.masked.load.v8i8(<8 x i8>* %ap, i32 8, <8 x i1> %mask, <8 x i8> undef) + %load = call <8 x i8> @llvm.masked.load.v8i8(ptr %ap, i32 8, <8 x i1> %mask, <8 x i8> undef) %ext = zext <8 x i8> %load to <8 x i64> ret <8 x i64> %ext } -define <16 x i32> @masked_load_zext_v16i16i32_m32(<16 x i16>* %ap, <16 x i32>* %bp) #0 { +define <16 x i32> @masked_load_zext_v16i16i32_m32(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_zext_v16i16i32_m32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #8 @@ -1165,14 +1165,14 @@ define <16 x i32> @masked_load_zext_v16i16i32_m32(<16 x i16>* %ap, <16 x i32>* % ; VBITS_GE_512-NEXT: ld1h { z0.s }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <16 x i32>, <16 x i32>* %bp + %b = load <16 x i32>, ptr %bp %mask = icmp eq <16 x i32> %b, zeroinitializer - %load = call <16 x i16> @llvm.masked.load.v16i16(<16 x i16>* %ap, i32 8, <16 x i1> %mask, <16 x i16> undef) + %load = call <16 x i16> @llvm.masked.load.v16i16(ptr %ap, i32 8, <16 x i1> %mask, <16 x i16> undef) %ext = zext <16 x i16> %load to <16 x i32> ret <16 x i32> %ext } -define <8 x i64> @masked_load_zext_v8i16i64_m64(<8 x i16>* %ap, <8 x i64>* %bp) #0 { +define <8 x i64> @masked_load_zext_v8i16i64_m64(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_zext_v8i16i64_m64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #4 @@ -1208,14 +1208,14 @@ define <8 x i64> @masked_load_zext_v8i16i64_m64(<8 x i16>* %ap, <8 x i64>* %bp) ; VBITS_GE_512-NEXT: ld1h { z0.d }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <8 x i64>, <8 x i64>* %bp + %b = load <8 x i64>, ptr %bp %mask = icmp eq <8 x i64> %b, zeroinitializer - %load = call <8 x i16> @llvm.masked.load.v8i16(<8 x i16>* %ap, i32 8, <8 x i1> %mask, <8 x i16> undef) + %load = call <8 x i16> @llvm.masked.load.v8i16(ptr %ap, i32 8, <8 x i1> %mask, <8 x i16> undef) %ext = zext <8 x i16> %load to <8 x i64> ret <8 x i64> %ext } -define <8 x i64> @masked_load_zext_v8i32i64_m64(<8 x i32>* %ap, <8 x i64>* %bp) #0 { +define <8 x i64> @masked_load_zext_v8i32i64_m64(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_zext_v8i32i64_m64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x9, #4 @@ -1248,14 +1248,14 @@ define <8 x i64> @masked_load_zext_v8i32i64_m64(<8 x i32>* %ap, <8 x i64>* %bp) ; VBITS_GE_512-NEXT: ld1w { z0.d }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <8 x i64>, <8 x i64>* %bp + %b = load <8 x i64>, ptr %bp %mask = icmp eq <8 x i64> %b, zeroinitializer - %load = call <8 x i32> @llvm.masked.load.v8i32(<8 x i32>* %ap, i32 8, <8 x i1> %mask, <8 x i32> undef) + %load = call <8 x i32> @llvm.masked.load.v8i32(ptr %ap, i32 8, <8 x i1> %mask, <8 x i32> undef) %ext = zext <8 x i32> %load to <8 x i64> ret <8 x i64> %ext } -define <128 x i16> @masked_load_sext_v128i8i16(<128 x i8>* %ap, <128 x i8>* %bp) vscale_range(16,0) #0 { +define <128 x i16> @masked_load_sext_v128i8i16(ptr %ap, ptr %bp) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_load_sext_v128i8i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1264,14 +1264,14 @@ define <128 x i16> @masked_load_sext_v128i8i16(<128 x i8>* %ap, <128 x i8>* %bp) ; CHECK-NEXT: ld1sb { z0.h }, p1/z, [x0] ; CHECK-NEXT: st1h { z0.h }, p0, [x8] ; CHECK-NEXT: ret - %b = load <128 x i8>, <128 x i8>* %bp + %b = load <128 x i8>, ptr %bp %mask = icmp eq <128 x i8> %b, zeroinitializer - %load = call <128 x i8> @llvm.masked.load.v128i8(<128 x i8>* %ap, i32 8, <128 x i1> %mask, <128 x i8> undef) + %load = call <128 x i8> @llvm.masked.load.v128i8(ptr %ap, i32 8, <128 x i1> %mask, <128 x i8> undef) %ext = sext <128 x i8> %load to <128 x i16> ret <128 x i16> %ext } -define <64 x i32> @masked_load_sext_v64i8i32(<64 x i8>* %ap, <64 x i8>* %bp) vscale_range(16,0) #0 { +define <64 x i32> @masked_load_sext_v64i8i32(ptr %ap, ptr %bp) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_load_sext_v64i8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1280,14 +1280,14 @@ define <64 x i32> @masked_load_sext_v64i8i32(<64 x i8>* %ap, <64 x i8>* %bp) vsc ; CHECK-NEXT: ld1sb { z0.s }, p1/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x8] ; CHECK-NEXT: ret - %b = load <64 x i8>, <64 x i8>* %bp + %b = load <64 x i8>, ptr %bp %mask = icmp eq <64 x i8> %b, zeroinitializer - %load = call <64 x i8> @llvm.masked.load.v64i8(<64 x i8>* %ap, i32 8, <64 x i1> %mask, <64 x i8> undef) + %load = call <64 x i8> @llvm.masked.load.v64i8(ptr %ap, i32 8, <64 x i1> %mask, <64 x i8> undef) %ext = sext <64 x i8> %load to <64 x i32> ret <64 x i32> %ext } -define <32 x i64> @masked_load_sext_v32i8i64(<32 x i8>* %ap, <32 x i8>* %bp) vscale_range(16,0) #0 { +define <32 x i64> @masked_load_sext_v32i8i64(ptr %ap, ptr %bp) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_load_sext_v32i8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1296,14 +1296,14 @@ define <32 x i64> @masked_load_sext_v32i8i64(<32 x i8>* %ap, <32 x i8>* %bp) vsc ; CHECK-NEXT: ld1sb { z0.d }, p1/z, [x0] ; CHECK-NEXT: st1d { z0.d }, p0, [x8] ; CHECK-NEXT: ret - %b = load <32 x i8>, <32 x i8>* %bp + %b = load <32 x i8>, ptr %bp %mask = icmp eq <32 x i8> %b, zeroinitializer - %load = call <32 x i8> @llvm.masked.load.v32i8(<32 x i8>* %ap, i32 8, <32 x i1> %mask, <32 x i8> undef) + %load = call <32 x i8> @llvm.masked.load.v32i8(ptr %ap, i32 8, <32 x i1> %mask, <32 x i8> undef) %ext = sext <32 x i8> %load to <32 x i64> ret <32 x i64> %ext } -define <64 x i32> @masked_load_sext_v64i16i32(<64 x i16>* %ap, <64 x i16>* %bp) vscale_range(16,0) #0 { +define <64 x i32> @masked_load_sext_v64i16i32(ptr %ap, ptr %bp) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_load_sext_v64i16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1312,14 +1312,14 @@ define <64 x i32> @masked_load_sext_v64i16i32(<64 x i16>* %ap, <64 x i16>* %bp) ; CHECK-NEXT: ld1sh { z0.s }, p1/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x8] ; CHECK-NEXT: ret - %b = load <64 x i16>, <64 x i16>* %bp + %b = load <64 x i16>, ptr %bp %mask = icmp eq <64 x i16> %b, zeroinitializer - %load = call <64 x i16> @llvm.masked.load.v64i16(<64 x i16>* %ap, i32 8, <64 x i1> %mask, <64 x i16> undef) + %load = call <64 x i16> @llvm.masked.load.v64i16(ptr %ap, i32 8, <64 x i1> %mask, <64 x i16> undef) %ext = sext <64 x i16> %load to <64 x i32> ret <64 x i32> %ext } -define <32 x i64> @masked_load_sext_v32i16i64(<32 x i16>* %ap, <32 x i16>* %bp) vscale_range(16,0) #0 { +define <32 x i64> @masked_load_sext_v32i16i64(ptr %ap, ptr %bp) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_load_sext_v32i16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1328,14 +1328,14 @@ define <32 x i64> @masked_load_sext_v32i16i64(<32 x i16>* %ap, <32 x i16>* %bp) ; CHECK-NEXT: ld1sh { z0.d }, p1/z, [x0] ; CHECK-NEXT: st1d { z0.d }, p0, [x8] ; CHECK-NEXT: ret - %b = load <32 x i16>, <32 x i16>* %bp + %b = load <32 x i16>, ptr %bp %mask = icmp eq <32 x i16> %b, zeroinitializer - %load = call <32 x i16> @llvm.masked.load.v32i16(<32 x i16>* %ap, i32 8, <32 x i1> %mask, <32 x i16> undef) + %load = call <32 x i16> @llvm.masked.load.v32i16(ptr %ap, i32 8, <32 x i1> %mask, <32 x i16> undef) %ext = sext <32 x i16> %load to <32 x i64> ret <32 x i64> %ext } -define <32 x i64> @masked_load_sext_v32i32i64(<32 x i32>* %ap, <32 x i32>* %bp) vscale_range(16,0) #0 { +define <32 x i64> @masked_load_sext_v32i32i64(ptr %ap, ptr %bp) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_load_sext_v32i32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1344,14 +1344,14 @@ define <32 x i64> @masked_load_sext_v32i32i64(<32 x i32>* %ap, <32 x i32>* %bp) ; CHECK-NEXT: ld1sw { z0.d }, p1/z, [x0] ; CHECK-NEXT: st1d { z0.d }, p0, [x8] ; CHECK-NEXT: ret - %b = load <32 x i32>, <32 x i32>* %bp + %b = load <32 x i32>, ptr %bp %mask = icmp eq <32 x i32> %b, zeroinitializer - %load = call <32 x i32> @llvm.masked.load.v32i32(<32 x i32>* %ap, i32 8, <32 x i1> %mask, <32 x i32> undef) + %load = call <32 x i32> @llvm.masked.load.v32i32(ptr %ap, i32 8, <32 x i1> %mask, <32 x i32> undef) %ext = sext <32 x i32> %load to <32 x i64> ret <32 x i64> %ext } -define <128 x i16> @masked_load_zext_v128i8i16(<128 x i8>* %ap, <128 x i8>* %bp) vscale_range(16,0) #0 { +define <128 x i16> @masked_load_zext_v128i8i16(ptr %ap, ptr %bp) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_load_zext_v128i8i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -1360,14 +1360,14 @@ define <128 x i16> @masked_load_zext_v128i8i16(<128 x i8>* %ap, <128 x i8>* %bp) ; CHECK-NEXT: ld1b { z0.h }, p1/z, [x0] ; CHECK-NEXT: st1h { z0.h }, p0, [x8] ; CHECK-NEXT: ret - %b = load <128 x i8>, <128 x i8>* %bp + %b = load <128 x i8>, ptr %bp %mask = icmp eq <128 x i8> %b, zeroinitializer - %load = call <128 x i8> @llvm.masked.load.v128i8(<128 x i8>* %ap, i32 8, <128 x i1> %mask, <128 x i8> undef) + %load = call <128 x i8> @llvm.masked.load.v128i8(ptr %ap, i32 8, <128 x i1> %mask, <128 x i8> undef) %ext = zext <128 x i8> %load to <128 x i16> ret <128 x i16> %ext } -define <64 x i32> @masked_load_zext_v64i8i32(<64 x i8>* %ap, <64 x i8>* %bp) vscale_range(16,0) #0 { +define <64 x i32> @masked_load_zext_v64i8i32(ptr %ap, ptr %bp) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_load_zext_v64i8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1376,14 +1376,14 @@ define <64 x i32> @masked_load_zext_v64i8i32(<64 x i8>* %ap, <64 x i8>* %bp) vsc ; CHECK-NEXT: ld1b { z0.s }, p1/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x8] ; CHECK-NEXT: ret - %b = load <64 x i8>, <64 x i8>* %bp + %b = load <64 x i8>, ptr %bp %mask = icmp eq <64 x i8> %b, zeroinitializer - %load = call <64 x i8> @llvm.masked.load.v64i8(<64 x i8>* %ap, i32 8, <64 x i1> %mask, <64 x i8> undef) + %load = call <64 x i8> @llvm.masked.load.v64i8(ptr %ap, i32 8, <64 x i1> %mask, <64 x i8> undef) %ext = zext <64 x i8> %load to <64 x i32> ret <64 x i32> %ext } -define <32 x i64> @masked_load_zext_v32i8i64(<32 x i8>* %ap, <32 x i8>* %bp) vscale_range(16,0) #0 { +define <32 x i64> @masked_load_zext_v32i8i64(ptr %ap, ptr %bp) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_load_zext_v32i8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1392,14 +1392,14 @@ define <32 x i64> @masked_load_zext_v32i8i64(<32 x i8>* %ap, <32 x i8>* %bp) vsc ; CHECK-NEXT: ld1b { z0.d }, p1/z, [x0] ; CHECK-NEXT: st1d { z0.d }, p0, [x8] ; CHECK-NEXT: ret - %b = load <32 x i8>, <32 x i8>* %bp + %b = load <32 x i8>, ptr %bp %mask = icmp eq <32 x i8> %b, zeroinitializer - %load = call <32 x i8> @llvm.masked.load.v32i8(<32 x i8>* %ap, i32 8, <32 x i1> %mask, <32 x i8> undef) + %load = call <32 x i8> @llvm.masked.load.v32i8(ptr %ap, i32 8, <32 x i1> %mask, <32 x i8> undef) %ext = zext <32 x i8> %load to <32 x i64> ret <32 x i64> %ext } -define <64 x i32> @masked_load_zext_v64i16i32(<64 x i16>* %ap, <64 x i16>* %bp) vscale_range(16,0) #0 { +define <64 x i32> @masked_load_zext_v64i16i32(ptr %ap, ptr %bp) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_load_zext_v64i16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -1408,14 +1408,14 @@ define <64 x i32> @masked_load_zext_v64i16i32(<64 x i16>* %ap, <64 x i16>* %bp) ; CHECK-NEXT: ld1h { z0.s }, p1/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x8] ; CHECK-NEXT: ret - %b = load <64 x i16>, <64 x i16>* %bp + %b = load <64 x i16>, ptr %bp %mask = icmp eq <64 x i16> %b, zeroinitializer - %load = call <64 x i16> @llvm.masked.load.v64i16(<64 x i16>* %ap, i32 8, <64 x i1> %mask, <64 x i16> undef) + %load = call <64 x i16> @llvm.masked.load.v64i16(ptr %ap, i32 8, <64 x i1> %mask, <64 x i16> undef) %ext = zext <64 x i16> %load to <64 x i32> ret <64 x i32> %ext } -define <32 x i64> @masked_load_zext_v32i16i64(<32 x i16>* %ap, <32 x i16>* %bp) vscale_range(16,0) #0 { +define <32 x i64> @masked_load_zext_v32i16i64(ptr %ap, ptr %bp) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_load_zext_v32i16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1424,14 +1424,14 @@ define <32 x i64> @masked_load_zext_v32i16i64(<32 x i16>* %ap, <32 x i16>* %bp) ; CHECK-NEXT: ld1h { z0.d }, p1/z, [x0] ; CHECK-NEXT: st1d { z0.d }, p0, [x8] ; CHECK-NEXT: ret - %b = load <32 x i16>, <32 x i16>* %bp + %b = load <32 x i16>, ptr %bp %mask = icmp eq <32 x i16> %b, zeroinitializer - %load = call <32 x i16> @llvm.masked.load.v32i16(<32 x i16>* %ap, i32 8, <32 x i1> %mask, <32 x i16> undef) + %load = call <32 x i16> @llvm.masked.load.v32i16(ptr %ap, i32 8, <32 x i1> %mask, <32 x i16> undef) %ext = zext <32 x i16> %load to <32 x i64> ret <32 x i64> %ext } -define <32 x i64> @masked_load_zext_v32i32i64(<32 x i32>* %ap, <32 x i32>* %bp) vscale_range(16,0) #0 { +define <32 x i64> @masked_load_zext_v32i32i64(ptr %ap, ptr %bp) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_load_zext_v32i32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -1440,14 +1440,14 @@ define <32 x i64> @masked_load_zext_v32i32i64(<32 x i32>* %ap, <32 x i32>* %bp) ; CHECK-NEXT: ld1w { z0.d }, p1/z, [x0] ; CHECK-NEXT: st1d { z0.d }, p0, [x8] ; CHECK-NEXT: ret - %b = load <32 x i32>, <32 x i32>* %bp + %b = load <32 x i32>, ptr %bp %mask = icmp eq <32 x i32> %b, zeroinitializer - %load = call <32 x i32> @llvm.masked.load.v32i32(<32 x i32>* %ap, i32 8, <32 x i1> %mask, <32 x i32> undef) + %load = call <32 x i32> @llvm.masked.load.v32i32(ptr %ap, i32 8, <32 x i1> %mask, <32 x i32> undef) %ext = zext <32 x i32> %load to <32 x i64> ret <32 x i64> %ext } -define <8 x i64> @masked_load_sext_ugt_v8i32i64(<8 x i32>* %ap, <8 x i32>* %bp) #0 { +define <8 x i64> @masked_load_sext_ugt_v8i32i64(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_sext_ugt_v8i32i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.s, vl8 @@ -1471,14 +1471,14 @@ define <8 x i64> @masked_load_sext_ugt_v8i32i64(<8 x i32>* %ap, <8 x i32>* %bp) ; VBITS_GE_512-NEXT: ld1sw { z0.d }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <8 x i32>, <8 x i32>* %bp + %b = load <8 x i32>, ptr %bp %mask = icmp ugt <8 x i32> %b, zeroinitializer - %load = call <8 x i32> @llvm.masked.load.v8i32(<8 x i32>* %ap, i32 8, <8 x i1> %mask, <8 x i32> undef) + %load = call <8 x i32> @llvm.masked.load.v8i32(ptr %ap, i32 8, <8 x i1> %mask, <8 x i32> undef) %ext = sext <8 x i32> %load to <8 x i64> ret <8 x i64> %ext } -define <8 x i64> @masked_load_zext_sgt_v8i32i64(<8 x i32>* %ap, <8 x i32>* %bp) #0 { +define <8 x i64> @masked_load_zext_sgt_v8i32i64(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_load_zext_sgt_v8i32i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.s, vl8 @@ -1502,34 +1502,34 @@ define <8 x i64> @masked_load_zext_sgt_v8i32i64(<8 x i32>* %ap, <8 x i32>* %bp) ; VBITS_GE_512-NEXT: ld1w { z0.d }, p1/z, [x0] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8] ; VBITS_GE_512-NEXT: ret - %b = load <8 x i32>, <8 x i32>* %bp + %b = load <8 x i32>, ptr %bp %mask = icmp sgt <8 x i32> %b, zeroinitializer - %load = call <8 x i32> @llvm.masked.load.v8i32(<8 x i32>* %ap, i32 8, <8 x i1> %mask, <8 x i32> undef) + %load = call <8 x i32> @llvm.masked.load.v8i32(ptr %ap, i32 8, <8 x i1> %mask, <8 x i32> undef) %ext = zext <8 x i32> %load to <8 x i64> ret <8 x i64> %ext } -declare <2 x half> @llvm.masked.load.v2f16(<2 x half>*, i32, <2 x i1>, <2 x half>) -declare <2 x float> @llvm.masked.load.v2f32(<2 x float>*, i32, <2 x i1>, <2 x float>) -declare <4 x float> @llvm.masked.load.v4f32(<4 x float>*, i32, <4 x i1>, <4 x float>) -declare <8 x float> @llvm.masked.load.v8f32(<8 x float>*, i32, <8 x i1>, <8 x float>) -declare <16 x float> @llvm.masked.load.v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>) -declare <32 x float> @llvm.masked.load.v32f32(<32 x float>*, i32, <32 x i1>, <32 x float>) -declare <64 x float> @llvm.masked.load.v64f32(<64 x float>*, i32, <64 x i1>, <64 x float>) +declare <2 x half> @llvm.masked.load.v2f16(ptr, i32, <2 x i1>, <2 x half>) +declare <2 x float> @llvm.masked.load.v2f32(ptr, i32, <2 x i1>, <2 x float>) +declare <4 x float> @llvm.masked.load.v4f32(ptr, i32, <4 x i1>, <4 x float>) +declare <8 x float> @llvm.masked.load.v8f32(ptr, i32, <8 x i1>, <8 x float>) +declare <16 x float> @llvm.masked.load.v16f32(ptr, i32, <16 x i1>, <16 x float>) +declare <32 x float> @llvm.masked.load.v32f32(ptr, i32, <32 x i1>, <32 x float>) +declare <64 x float> @llvm.masked.load.v64f32(ptr, i32, <64 x i1>, <64 x float>) -declare <128 x i8> @llvm.masked.load.v128i8(<128 x i8>*, i32, <128 x i1>, <128 x i8>) -declare <64 x i8> @llvm.masked.load.v64i8(<64 x i8>*, i32, <64 x i1>, <64 x i8>) -declare <32 x i8> @llvm.masked.load.v32i8(<32 x i8>*, i32, <32 x i1>, <32 x i8>) -declare <16 x i8> @llvm.masked.load.v16i8(<16 x i8>*, i32, <16 x i1>, <16 x i8>) -declare <16 x i16> @llvm.masked.load.v16i16(<16 x i16>*, i32, <16 x i1>, <16 x i16>) -declare <8 x i8> @llvm.masked.load.v8i8(<8 x i8>*, i32, <8 x i1>, <8 x i8>) -declare <8 x i16> @llvm.masked.load.v8i16(<8 x i16>*, i32, <8 x i1>, <8 x i16>) -declare <8 x i32> @llvm.masked.load.v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>) -declare <32 x i32> @llvm.masked.load.v32i32(<32 x i32>*, i32, <32 x i1>, <32 x i32>) -declare <32 x i16> @llvm.masked.load.v32i16(<32 x i16>*, i32, <32 x i1>, <32 x i16>) -declare <64 x i16> @llvm.masked.load.v64i16(<64 x i16>*, i32, <64 x i1>, <64 x i16>) -declare <16 x i32> @llvm.masked.load.v16i32(<16 x i32>*, i32, <16 x i1>, <16 x i32>) -declare <8 x i64> @llvm.masked.load.v8i64(<8 x i64>*, i32, <8 x i1>, <8 x i64>) -declare <8 x double> @llvm.masked.load.v8f64(<8 x double>*, i32, <8 x i1>, <8 x double>) +declare <128 x i8> @llvm.masked.load.v128i8(ptr, i32, <128 x i1>, <128 x i8>) +declare <64 x i8> @llvm.masked.load.v64i8(ptr, i32, <64 x i1>, <64 x i8>) +declare <32 x i8> @llvm.masked.load.v32i8(ptr, i32, <32 x i1>, <32 x i8>) +declare <16 x i8> @llvm.masked.load.v16i8(ptr, i32, <16 x i1>, <16 x i8>) +declare <16 x i16> @llvm.masked.load.v16i16(ptr, i32, <16 x i1>, <16 x i16>) +declare <8 x i8> @llvm.masked.load.v8i8(ptr, i32, <8 x i1>, <8 x i8>) +declare <8 x i16> @llvm.masked.load.v8i16(ptr, i32, <8 x i1>, <8 x i16>) +declare <8 x i32> @llvm.masked.load.v8i32(ptr, i32, <8 x i1>, <8 x i32>) +declare <32 x i32> @llvm.masked.load.v32i32(ptr, i32, <32 x i1>, <32 x i32>) +declare <32 x i16> @llvm.masked.load.v32i16(ptr, i32, <32 x i1>, <32 x i16>) +declare <64 x i16> @llvm.masked.load.v64i16(ptr, i32, <64 x i1>, <64 x i16>) +declare <16 x i32> @llvm.masked.load.v16i32(ptr, i32, <16 x i1>, <16 x i32>) +declare <8 x i64> @llvm.masked.load.v8i64(ptr, i32, <8 x i1>, <8 x i64>) +declare <8 x double> @llvm.masked.load.v8f64(ptr, i32, <8 x i1>, <8 x double>) attributes #0 = { "target-features"="+sve" } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll index d7a87af..a57fe58 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll @@ -9,7 +9,7 @@ target triple = "aarch64-unknown-linux-gnu" ; ST1B ; -define void @masked_scatter_v2i8(<2 x i8>* %a, <2 x i8*>* %b) vscale_range(2,0) #0 { +define void @masked_scatter_v2i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_scatter_v2i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldrb w8, [x0] @@ -24,14 +24,14 @@ define void @masked_scatter_v2i8(<2 x i8>* %a, <2 x i8*>* %b) vscale_range(2,0) ; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, #0 ; CHECK-NEXT: st1b { z0.d }, p0, [z2.d] ; CHECK-NEXT: ret - %vals = load <2 x i8>, <2 x i8>* %a - %ptrs = load <2 x i8*>, <2 x i8*>* %b + %vals = load <2 x i8>, ptr %a + %ptrs = load <2 x ptr>, ptr %b %mask = icmp eq <2 x i8> %vals, zeroinitializer - call void @llvm.masked.scatter.v2i8(<2 x i8> %vals, <2 x i8*> %ptrs, i32 8, <2 x i1> %mask) + call void @llvm.masked.scatter.v2i8(<2 x i8> %vals, <2 x ptr> %ptrs, i32 8, <2 x i1> %mask) ret void } -define void @masked_scatter_v4i8(<4 x i8>* %a, <4 x i8*>* %b) vscale_range(2,0) #0 { +define void @masked_scatter_v4i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_scatter_v4i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr s0, [x0] @@ -46,14 +46,14 @@ define void @masked_scatter_v4i8(<4 x i8>* %a, <4 x i8*>* %b) vscale_range(2,0) ; CHECK-NEXT: cmpne p0.d, p0/z, z2.d, #0 ; CHECK-NEXT: st1b { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <4 x i8>, <4 x i8>* %a - %ptrs = load <4 x i8*>, <4 x i8*>* %b + %vals = load <4 x i8>, ptr %a + %ptrs = load <4 x ptr>, ptr %b %mask = icmp eq <4 x i8> %vals, zeroinitializer - call void @llvm.masked.scatter.v4i8(<4 x i8> %vals, <4 x i8*> %ptrs, i32 8, <4 x i1> %mask) + call void @llvm.masked.scatter.v4i8(<4 x i8> %vals, <4 x ptr> %ptrs, i32 8, <4 x i1> %mask) ret void } -define void @masked_scatter_v8i8(<8 x i8>* %a, <8 x i8*>* %b) #0 { +define void @masked_scatter_v8i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: masked_scatter_v8i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ldr d0, [x0] @@ -99,14 +99,14 @@ define void @masked_scatter_v8i8(<8 x i8>* %a, <8 x i8*>* %b) #0 { ; VBITS_GE_512-NEXT: cmpne p0.d, p0/z, z2.d, #0 ; VBITS_GE_512-NEXT: st1b { z0.d }, p0, [z1.d] ; VBITS_GE_512-NEXT: ret - %vals = load <8 x i8>, <8 x i8>* %a - %ptrs = load <8 x i8*>, <8 x i8*>* %b + %vals = load <8 x i8>, ptr %a + %ptrs = load <8 x ptr>, ptr %b %mask = icmp eq <8 x i8> %vals, zeroinitializer - call void @llvm.masked.scatter.v8i8(<8 x i8> %vals, <8 x i8*> %ptrs, i32 8, <8 x i1> %mask) + call void @llvm.masked.scatter.v8i8(<8 x i8> %vals, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask) ret void } -define void @masked_scatter_v16i8(<16 x i8>* %a, <16 x i8*>* %b) vscale_range(8,0) #0 { +define void @masked_scatter_v16i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_scatter_v16i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -122,14 +122,14 @@ define void @masked_scatter_v16i8(<16 x i8>* %a, <16 x i8*>* %b) vscale_range(8, ; CHECK-NEXT: cmpne p0.d, p0/z, z2.d, #0 ; CHECK-NEXT: st1b { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <16 x i8>, <16 x i8>* %a - %ptrs = load <16 x i8*>, <16 x i8*>* %b + %vals = load <16 x i8>, ptr %a + %ptrs = load <16 x ptr>, ptr %b %mask = icmp eq <16 x i8> %vals, zeroinitializer - call void @llvm.masked.scatter.v16i8(<16 x i8> %vals, <16 x i8*> %ptrs, i32 8, <16 x i1> %mask) + call void @llvm.masked.scatter.v16i8(<16 x i8> %vals, <16 x ptr> %ptrs, i32 8, <16 x i1> %mask) ret void } -define void @masked_scatter_v32i8(<32 x i8>* %a, <32 x i8*>* %b) vscale_range(16,0) #0 { +define void @masked_scatter_v32i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_scatter_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -145,10 +145,10 @@ define void @masked_scatter_v32i8(<32 x i8>* %a, <32 x i8*>* %b) vscale_range(16 ; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: st1b { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <32 x i8>, <32 x i8>* %a - %ptrs = load <32 x i8*>, <32 x i8*>* %b + %vals = load <32 x i8>, ptr %a + %ptrs = load <32 x ptr>, ptr %b %mask = icmp eq <32 x i8> %vals, zeroinitializer - call void @llvm.masked.scatter.v32i8(<32 x i8> %vals, <32 x i8*> %ptrs, i32 8, <32 x i1> %mask) + call void @llvm.masked.scatter.v32i8(<32 x i8> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask) ret void } @@ -156,7 +156,7 @@ define void @masked_scatter_v32i8(<32 x i8>* %a, <32 x i8*>* %b) vscale_range(16 ; ST1H ; -define void @masked_scatter_v2i16(<2 x i16>* %a, <2 x i16*>* %b) vscale_range(2,0) #0 { +define void @masked_scatter_v2i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_scatter_v2i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldrh w8, [x0] @@ -171,14 +171,14 @@ define void @masked_scatter_v2i16(<2 x i16>* %a, <2 x i16*>* %b) vscale_range(2, ; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, #0 ; CHECK-NEXT: st1h { z0.d }, p0, [z2.d] ; CHECK-NEXT: ret - %vals = load <2 x i16>, <2 x i16>* %a - %ptrs = load <2 x i16*>, <2 x i16*>* %b + %vals = load <2 x i16>, ptr %a + %ptrs = load <2 x ptr>, ptr %b %mask = icmp eq <2 x i16> %vals, zeroinitializer - call void @llvm.masked.scatter.v2i16(<2 x i16> %vals, <2 x i16*> %ptrs, i32 8, <2 x i1> %mask) + call void @llvm.masked.scatter.v2i16(<2 x i16> %vals, <2 x ptr> %ptrs, i32 8, <2 x i1> %mask) ret void } -define void @masked_scatter_v4i16(<4 x i16>* %a, <4 x i16*>* %b) vscale_range(2,0) #0 { +define void @masked_scatter_v4i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_scatter_v4i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -192,14 +192,14 @@ define void @masked_scatter_v4i16(<4 x i16>* %a, <4 x i16*>* %b) vscale_range(2, ; CHECK-NEXT: cmpne p0.d, p0/z, z2.d, #0 ; CHECK-NEXT: st1h { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <4 x i16>, <4 x i16>* %a - %ptrs = load <4 x i16*>, <4 x i16*>* %b + %vals = load <4 x i16>, ptr %a + %ptrs = load <4 x ptr>, ptr %b %mask = icmp eq <4 x i16> %vals, zeroinitializer - call void @llvm.masked.scatter.v4i16(<4 x i16> %vals, <4 x i16*> %ptrs, i32 8, <4 x i1> %mask) + call void @llvm.masked.scatter.v4i16(<4 x i16> %vals, <4 x ptr> %ptrs, i32 8, <4 x i1> %mask) ret void } -define void @masked_scatter_v8i16(<8 x i16>* %a, <8 x i16*>* %b) #0 { +define void @masked_scatter_v8i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: masked_scatter_v8i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ldr q0, [x0] @@ -237,14 +237,14 @@ define void @masked_scatter_v8i16(<8 x i16>* %a, <8 x i16*>* %b) #0 { ; VBITS_GE_512-NEXT: cmpne p0.d, p0/z, z2.d, #0 ; VBITS_GE_512-NEXT: st1h { z0.d }, p0, [z1.d] ; VBITS_GE_512-NEXT: ret - %vals = load <8 x i16>, <8 x i16>* %a - %ptrs = load <8 x i16*>, <8 x i16*>* %b + %vals = load <8 x i16>, ptr %a + %ptrs = load <8 x ptr>, ptr %b %mask = icmp eq <8 x i16> %vals, zeroinitializer - call void @llvm.masked.scatter.v8i16(<8 x i16> %vals, <8 x i16*> %ptrs, i32 8, <8 x i1> %mask) + call void @llvm.masked.scatter.v8i16(<8 x i16> %vals, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask) ret void } -define void @masked_scatter_v16i16(<16 x i16>* %a, <16 x i16*>* %b) vscale_range(8,0) #0 { +define void @masked_scatter_v16i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_scatter_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -258,14 +258,14 @@ define void @masked_scatter_v16i16(<16 x i16>* %a, <16 x i16*>* %b) vscale_range ; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: st1h { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <16 x i16>, <16 x i16>* %a - %ptrs = load <16 x i16*>, <16 x i16*>* %b + %vals = load <16 x i16>, ptr %a + %ptrs = load <16 x ptr>, ptr %b %mask = icmp eq <16 x i16> %vals, zeroinitializer - call void @llvm.masked.scatter.v16i16(<16 x i16> %vals, <16 x i16*> %ptrs, i32 8, <16 x i1> %mask) + call void @llvm.masked.scatter.v16i16(<16 x i16> %vals, <16 x ptr> %ptrs, i32 8, <16 x i1> %mask) ret void } -define void @masked_scatter_v32i16(<32 x i16>* %a, <32 x i16*>* %b) vscale_range(16,0) #0 { +define void @masked_scatter_v32i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_scatter_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -279,10 +279,10 @@ define void @masked_scatter_v32i16(<32 x i16>* %a, <32 x i16*>* %b) vscale_range ; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: st1h { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <32 x i16>, <32 x i16>* %a - %ptrs = load <32 x i16*>, <32 x i16*>* %b + %vals = load <32 x i16>, ptr %a + %ptrs = load <32 x ptr>, ptr %b %mask = icmp eq <32 x i16> %vals, zeroinitializer - call void @llvm.masked.scatter.v32i16(<32 x i16> %vals, <32 x i16*> %ptrs, i32 8, <32 x i1> %mask) + call void @llvm.masked.scatter.v32i16(<32 x i16> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask) ret void } @@ -290,7 +290,7 @@ define void @masked_scatter_v32i16(<32 x i16>* %a, <32 x i16*>* %b) vscale_range ; ST1W ; -define void @masked_scatter_v2i32(<2 x i32>* %a, <2 x i32*>* %b) vscale_range(2,0) #0 { +define void @masked_scatter_v2i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_scatter_v2i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -302,14 +302,14 @@ define void @masked_scatter_v2i32(<2 x i32>* %a, <2 x i32*>* %b) vscale_range(2, ; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, #0 ; CHECK-NEXT: st1w { z0.d }, p0, [z2.d] ; CHECK-NEXT: ret - %vals = load <2 x i32>, <2 x i32>* %a - %ptrs = load <2 x i32*>, <2 x i32*>* %b + %vals = load <2 x i32>, ptr %a + %ptrs = load <2 x ptr>, ptr %b %mask = icmp eq <2 x i32> %vals, zeroinitializer - call void @llvm.masked.scatter.v2i32(<2 x i32> %vals, <2 x i32*> %ptrs, i32 8, <2 x i1> %mask) + call void @llvm.masked.scatter.v2i32(<2 x i32> %vals, <2 x ptr> %ptrs, i32 8, <2 x i1> %mask) ret void } -define void @masked_scatter_v4i32(<4 x i32>* %a, <4 x i32*>* %b) vscale_range(2,0) #0 { +define void @masked_scatter_v4i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_scatter_v4i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -321,14 +321,14 @@ define void @masked_scatter_v4i32(<4 x i32>* %a, <4 x i32*>* %b) vscale_range(2, ; CHECK-NEXT: cmpne p0.d, p0/z, z2.d, #0 ; CHECK-NEXT: st1w { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <4 x i32>, <4 x i32>* %a - %ptrs = load <4 x i32*>, <4 x i32*>* %b + %vals = load <4 x i32>, ptr %a + %ptrs = load <4 x ptr>, ptr %b %mask = icmp eq <4 x i32> %vals, zeroinitializer - call void @llvm.masked.scatter.v4i32(<4 x i32> %vals, <4 x i32*> %ptrs, i32 8, <4 x i1> %mask) + call void @llvm.masked.scatter.v4i32(<4 x i32> %vals, <4 x ptr> %ptrs, i32 8, <4 x i1> %mask) ret void } -define void @masked_scatter_v8i32(<8 x i32>* %a, <8 x i32*>* %b) #0 { +define void @masked_scatter_v8i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: masked_scatter_v8i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.s, vl8 @@ -362,14 +362,14 @@ define void @masked_scatter_v8i32(<8 x i32>* %a, <8 x i32*>* %b) #0 { ; VBITS_GE_512-NEXT: punpklo p0.h, p0.b ; VBITS_GE_512-NEXT: st1w { z0.d }, p0, [z1.d] ; VBITS_GE_512-NEXT: ret - %vals = load <8 x i32>, <8 x i32>* %a - %ptrs = load <8 x i32*>, <8 x i32*>* %b + %vals = load <8 x i32>, ptr %a + %ptrs = load <8 x ptr>, ptr %b %mask = icmp eq <8 x i32> %vals, zeroinitializer - call void @llvm.masked.scatter.v8i32(<8 x i32> %vals, <8 x i32*> %ptrs, i32 8, <8 x i1> %mask) + call void @llvm.masked.scatter.v8i32(<8 x i32> %vals, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask) ret void } -define void @masked_scatter_v16i32(<16 x i32>* %a, <16 x i32*>* %b) vscale_range(8,0) #0 { +define void @masked_scatter_v16i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_scatter_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -381,14 +381,14 @@ define void @masked_scatter_v16i32(<16 x i32>* %a, <16 x i32*>* %b) vscale_range ; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: st1w { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <16 x i32>, <16 x i32>* %a - %ptrs = load <16 x i32*>, <16 x i32*>* %b + %vals = load <16 x i32>, ptr %a + %ptrs = load <16 x ptr>, ptr %b %mask = icmp eq <16 x i32> %vals, zeroinitializer - call void @llvm.masked.scatter.v16i32(<16 x i32> %vals, <16 x i32*> %ptrs, i32 8, <16 x i1> %mask) + call void @llvm.masked.scatter.v16i32(<16 x i32> %vals, <16 x ptr> %ptrs, i32 8, <16 x i1> %mask) ret void } -define void @masked_scatter_v32i32(<32 x i32>* %a, <32 x i32*>* %b) vscale_range(16,0) #0 { +define void @masked_scatter_v32i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_scatter_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -400,10 +400,10 @@ define void @masked_scatter_v32i32(<32 x i32>* %a, <32 x i32*>* %b) vscale_range ; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: st1w { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <32 x i32>, <32 x i32>* %a - %ptrs = load <32 x i32*>, <32 x i32*>* %b + %vals = load <32 x i32>, ptr %a + %ptrs = load <32 x ptr>, ptr %b %mask = icmp eq <32 x i32> %vals, zeroinitializer - call void @llvm.masked.scatter.v32i32(<32 x i32> %vals, <32 x i32*> %ptrs, i32 8, <32 x i1> %mask) + call void @llvm.masked.scatter.v32i32(<32 x i32> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask) ret void } @@ -412,7 +412,7 @@ define void @masked_scatter_v32i32(<32 x i32>* %a, <32 x i32*>* %b) vscale_range ; ; Scalarize 1 x i64 scatters -define void @masked_scatter_v1i64(<1 x i64>* %a, <1 x i64*>* %b) vscale_range(2,0) #0 { +define void @masked_scatter_v1i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_scatter_v1i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -424,14 +424,14 @@ define void @masked_scatter_v1i64(<1 x i64>* %a, <1 x i64*>* %b) vscale_range(2, ; CHECK-NEXT: str d0, [x8] ; CHECK-NEXT: .LBB15_2: // %else ; CHECK-NEXT: ret - %vals = load <1 x i64>, <1 x i64>* %a - %ptrs = load <1 x i64*>, <1 x i64*>* %b + %vals = load <1 x i64>, ptr %a + %ptrs = load <1 x ptr>, ptr %b %mask = icmp eq <1 x i64> %vals, zeroinitializer - call void @llvm.masked.scatter.v1i64(<1 x i64> %vals, <1 x i64*> %ptrs, i32 8, <1 x i1> %mask) + call void @llvm.masked.scatter.v1i64(<1 x i64> %vals, <1 x ptr> %ptrs, i32 8, <1 x i1> %mask) ret void } -define void @masked_scatter_v2i64(<2 x i64>* %a, <2 x i64*>* %b) vscale_range(2,0) #0 { +define void @masked_scatter_v2i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_scatter_v2i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -441,14 +441,14 @@ define void @masked_scatter_v2i64(<2 x i64>* %a, <2 x i64*>* %b) vscale_range(2, ; CHECK-NEXT: cmpne p0.d, p0/z, z2.d, #0 ; CHECK-NEXT: st1d { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <2 x i64>, <2 x i64>* %a - %ptrs = load <2 x i64*>, <2 x i64*>* %b + %vals = load <2 x i64>, ptr %a + %ptrs = load <2 x ptr>, ptr %b %mask = icmp eq <2 x i64> %vals, zeroinitializer - call void @llvm.masked.scatter.v2i64(<2 x i64> %vals, <2 x i64*> %ptrs, i32 8, <2 x i1> %mask) + call void @llvm.masked.scatter.v2i64(<2 x i64> %vals, <2 x ptr> %ptrs, i32 8, <2 x i1> %mask) ret void } -define void @masked_scatter_v4i64(<4 x i64>* %a, <4 x i64*>* %b) vscale_range(2,0) #0 { +define void @masked_scatter_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_scatter_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -457,14 +457,14 @@ define void @masked_scatter_v4i64(<4 x i64>* %a, <4 x i64*>* %b) vscale_range(2, ; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, #0 ; CHECK-NEXT: st1d { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <4 x i64>, <4 x i64>* %a - %ptrs = load <4 x i64*>, <4 x i64*>* %b + %vals = load <4 x i64>, ptr %a + %ptrs = load <4 x ptr>, ptr %b %mask = icmp eq <4 x i64> %vals, zeroinitializer - call void @llvm.masked.scatter.v4i64(<4 x i64> %vals, <4 x i64*> %ptrs, i32 8, <4 x i1> %mask) + call void @llvm.masked.scatter.v4i64(<4 x i64> %vals, <4 x ptr> %ptrs, i32 8, <4 x i1> %mask) ret void } -define void @masked_scatter_v8i64(<8 x i64>* %a, <8 x i64*>* %b) #0 { +define void @masked_scatter_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: masked_scatter_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -487,14 +487,14 @@ define void @masked_scatter_v8i64(<8 x i64>* %a, <8 x i64*>* %b) #0 { ; VBITS_GE_512-NEXT: cmpeq p0.d, p0/z, z0.d, #0 ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [z1.d] ; VBITS_GE_512-NEXT: ret - %vals = load <8 x i64>, <8 x i64>* %a - %ptrs = load <8 x i64*>, <8 x i64*>* %b + %vals = load <8 x i64>, ptr %a + %ptrs = load <8 x ptr>, ptr %b %mask = icmp eq <8 x i64> %vals, zeroinitializer - call void @llvm.masked.scatter.v8i64(<8 x i64> %vals, <8 x i64*> %ptrs, i32 8, <8 x i1> %mask) + call void @llvm.masked.scatter.v8i64(<8 x i64> %vals, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask) ret void } -define void @masked_scatter_v16i64(<16 x i64>* %a, <16 x i64*>* %b) vscale_range(8,0) #0 { +define void @masked_scatter_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_scatter_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -503,14 +503,14 @@ define void @masked_scatter_v16i64(<16 x i64>* %a, <16 x i64*>* %b) vscale_range ; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, #0 ; CHECK-NEXT: st1d { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <16 x i64>, <16 x i64>* %a - %ptrs = load <16 x i64*>, <16 x i64*>* %b + %vals = load <16 x i64>, ptr %a + %ptrs = load <16 x ptr>, ptr %b %mask = icmp eq <16 x i64> %vals, zeroinitializer - call void @llvm.masked.scatter.v16i64(<16 x i64> %vals, <16 x i64*> %ptrs, i32 8, <16 x i1> %mask) + call void @llvm.masked.scatter.v16i64(<16 x i64> %vals, <16 x ptr> %ptrs, i32 8, <16 x i1> %mask) ret void } -define void @masked_scatter_v32i64(<32 x i64>* %a, <32 x i64*>* %b) vscale_range(16,0) #0 { +define void @masked_scatter_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_scatter_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -519,10 +519,10 @@ define void @masked_scatter_v32i64(<32 x i64>* %a, <32 x i64*>* %b) vscale_range ; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, #0 ; CHECK-NEXT: st1d { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <32 x i64>, <32 x i64>* %a - %ptrs = load <32 x i64*>, <32 x i64*>* %b + %vals = load <32 x i64>, ptr %a + %ptrs = load <32 x ptr>, ptr %b %mask = icmp eq <32 x i64> %vals, zeroinitializer - call void @llvm.masked.scatter.v32i64(<32 x i64> %vals, <32 x i64*> %ptrs, i32 8, <32 x i1> %mask) + call void @llvm.masked.scatter.v32i64(<32 x i64> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask) ret void } @@ -530,7 +530,7 @@ define void @masked_scatter_v32i64(<32 x i64>* %a, <32 x i64*>* %b) vscale_range ; ST1H (float) ; -define void @masked_scatter_v2f16(<2 x half>* %a, <2 x half*>* %b) vscale_range(2,0) #0 { +define void @masked_scatter_v2f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_scatter_v2f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr s1, [x0] @@ -552,14 +552,14 @@ define void @masked_scatter_v2f16(<2 x half>* %a, <2 x half*>* %b) vscale_range( ; CHECK-NEXT: uunpklo z0.d, z1.s ; CHECK-NEXT: st1h { z0.d }, p0, [z2.d] ; CHECK-NEXT: ret - %vals = load <2 x half>, <2 x half>* %a - %ptrs = load <2 x half*>, <2 x half*>* %b + %vals = load <2 x half>, ptr %a + %ptrs = load <2 x ptr>, ptr %b %mask = fcmp oeq <2 x half> %vals, zeroinitializer - call void @llvm.masked.scatter.v2f16(<2 x half> %vals, <2 x half*> %ptrs, i32 8, <2 x i1> %mask) + call void @llvm.masked.scatter.v2f16(<2 x half> %vals, <2 x ptr> %ptrs, i32 8, <2 x i1> %mask) ret void } -define void @masked_scatter_v4f16(<4 x half>* %a, <4 x half*>* %b) vscale_range(2,0) #0 { +define void @masked_scatter_v4f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_scatter_v4f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -573,14 +573,14 @@ define void @masked_scatter_v4f16(<4 x half>* %a, <4 x half*>* %b) vscale_range( ; CHECK-NEXT: cmpne p0.d, p0/z, z2.d, #0 ; CHECK-NEXT: st1h { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <4 x half>, <4 x half>* %a - %ptrs = load <4 x half*>, <4 x half*>* %b + %vals = load <4 x half>, ptr %a + %ptrs = load <4 x ptr>, ptr %b %mask = fcmp oeq <4 x half> %vals, zeroinitializer - call void @llvm.masked.scatter.v4f16(<4 x half> %vals, <4 x half*> %ptrs, i32 8, <4 x i1> %mask) + call void @llvm.masked.scatter.v4f16(<4 x half> %vals, <4 x ptr> %ptrs, i32 8, <4 x i1> %mask) ret void } -define void @masked_scatter_v8f16(<8 x half>* %a, <8 x half*>* %b) #0 { +define void @masked_scatter_v8f16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: masked_scatter_v8f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ldr q0, [x0] @@ -618,14 +618,14 @@ define void @masked_scatter_v8f16(<8 x half>* %a, <8 x half*>* %b) #0 { ; VBITS_GE_512-NEXT: cmpne p0.d, p0/z, z2.d, #0 ; VBITS_GE_512-NEXT: st1h { z0.d }, p0, [z1.d] ; VBITS_GE_512-NEXT: ret - %vals = load <8 x half>, <8 x half>* %a - %ptrs = load <8 x half*>, <8 x half*>* %b + %vals = load <8 x half>, ptr %a + %ptrs = load <8 x ptr>, ptr %b %mask = fcmp oeq <8 x half> %vals, zeroinitializer - call void @llvm.masked.scatter.v8f16(<8 x half> %vals, <8 x half*> %ptrs, i32 8, <8 x i1> %mask) + call void @llvm.masked.scatter.v8f16(<8 x half> %vals, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask) ret void } -define void @masked_scatter_v16f16(<16 x half>* %a, <16 x half*>* %b) vscale_range(8,0) #0 { +define void @masked_scatter_v16f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_scatter_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -639,14 +639,14 @@ define void @masked_scatter_v16f16(<16 x half>* %a, <16 x half*>* %b) vscale_ran ; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: st1h { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <16 x half>, <16 x half>* %a - %ptrs = load <16 x half*>, <16 x half*>* %b + %vals = load <16 x half>, ptr %a + %ptrs = load <16 x ptr>, ptr %b %mask = fcmp oeq <16 x half> %vals, zeroinitializer - call void @llvm.masked.scatter.v16f16(<16 x half> %vals, <16 x half*> %ptrs, i32 8, <16 x i1> %mask) + call void @llvm.masked.scatter.v16f16(<16 x half> %vals, <16 x ptr> %ptrs, i32 8, <16 x i1> %mask) ret void } -define void @masked_scatter_v32f16(<32 x half>* %a, <32 x half*>* %b) vscale_range(16,0) #0 { +define void @masked_scatter_v32f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_scatter_v32f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -660,10 +660,10 @@ define void @masked_scatter_v32f16(<32 x half>* %a, <32 x half*>* %b) vscale_ran ; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: st1h { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <32 x half>, <32 x half>* %a - %ptrs = load <32 x half*>, <32 x half*>* %b + %vals = load <32 x half>, ptr %a + %ptrs = load <32 x ptr>, ptr %b %mask = fcmp oeq <32 x half> %vals, zeroinitializer - call void @llvm.masked.scatter.v32f16(<32 x half> %vals, <32 x half*> %ptrs, i32 8, <32 x i1> %mask) + call void @llvm.masked.scatter.v32f16(<32 x half> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask) ret void } @@ -671,7 +671,7 @@ define void @masked_scatter_v32f16(<32 x half>* %a, <32 x half*>* %b) vscale_ran ; ST1W (float) ; -define void @masked_scatter_v2f32(<2 x float>* %a, <2 x float*>* %b) vscale_range(2,0) #0 { +define void @masked_scatter_v2f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_scatter_v2f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -683,14 +683,14 @@ define void @masked_scatter_v2f32(<2 x float>* %a, <2 x float*>* %b) vscale_rang ; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, #0 ; CHECK-NEXT: st1w { z0.d }, p0, [z2.d] ; CHECK-NEXT: ret - %vals = load <2 x float>, <2 x float>* %a - %ptrs = load <2 x float*>, <2 x float*>* %b + %vals = load <2 x float>, ptr %a + %ptrs = load <2 x ptr>, ptr %b %mask = fcmp oeq <2 x float> %vals, zeroinitializer - call void @llvm.masked.scatter.v2f32(<2 x float> %vals, <2 x float*> %ptrs, i32 8, <2 x i1> %mask) + call void @llvm.masked.scatter.v2f32(<2 x float> %vals, <2 x ptr> %ptrs, i32 8, <2 x i1> %mask) ret void } -define void @masked_scatter_v4f32(<4 x float>* %a, <4 x float*>* %b) vscale_range(2,0) #0 { +define void @masked_scatter_v4f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_scatter_v4f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -702,14 +702,14 @@ define void @masked_scatter_v4f32(<4 x float>* %a, <4 x float*>* %b) vscale_rang ; CHECK-NEXT: cmpne p0.d, p0/z, z2.d, #0 ; CHECK-NEXT: st1w { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <4 x float>, <4 x float>* %a - %ptrs = load <4 x float*>, <4 x float*>* %b + %vals = load <4 x float>, ptr %a + %ptrs = load <4 x ptr>, ptr %b %mask = fcmp oeq <4 x float> %vals, zeroinitializer - call void @llvm.masked.scatter.v4f32(<4 x float> %vals, <4 x float*> %ptrs, i32 8, <4 x i1> %mask) + call void @llvm.masked.scatter.v4f32(<4 x float> %vals, <4 x ptr> %ptrs, i32 8, <4 x i1> %mask) ret void } -define void @masked_scatter_v8f32(<8 x float>* %a, <8 x float*>* %b) #0 { +define void @masked_scatter_v8f32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: masked_scatter_v8f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: ptrue p0.s, vl8 @@ -743,14 +743,14 @@ define void @masked_scatter_v8f32(<8 x float>* %a, <8 x float*>* %b) #0 { ; VBITS_GE_512-NEXT: punpklo p0.h, p0.b ; VBITS_GE_512-NEXT: st1w { z0.d }, p0, [z1.d] ; VBITS_GE_512-NEXT: ret - %vals = load <8 x float>, <8 x float>* %a - %ptrs = load <8 x float*>, <8 x float*>* %b + %vals = load <8 x float>, ptr %a + %ptrs = load <8 x ptr>, ptr %b %mask = fcmp oeq <8 x float> %vals, zeroinitializer - call void @llvm.masked.scatter.v8f32(<8 x float> %vals, <8 x float*> %ptrs, i32 8, <8 x i1> %mask) + call void @llvm.masked.scatter.v8f32(<8 x float> %vals, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask) ret void } -define void @masked_scatter_v16f32(<16 x float>* %a, <16 x float*>* %b) vscale_range(8,0) #0 { +define void @masked_scatter_v16f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_scatter_v16f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -762,14 +762,14 @@ define void @masked_scatter_v16f32(<16 x float>* %a, <16 x float*>* %b) vscale_r ; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: st1w { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <16 x float>, <16 x float>* %a - %ptrs = load <16 x float*>, <16 x float*>* %b + %vals = load <16 x float>, ptr %a + %ptrs = load <16 x ptr>, ptr %b %mask = fcmp oeq <16 x float> %vals, zeroinitializer - call void @llvm.masked.scatter.v16f32(<16 x float> %vals, <16 x float*> %ptrs, i32 8, <16 x i1> %mask) + call void @llvm.masked.scatter.v16f32(<16 x float> %vals, <16 x ptr> %ptrs, i32 8, <16 x i1> %mask) ret void } -define void @masked_scatter_v32f32(<32 x float>* %a, <32 x float*>* %b) vscale_range(16,0) #0 { +define void @masked_scatter_v32f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_scatter_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -781,10 +781,10 @@ define void @masked_scatter_v32f32(<32 x float>* %a, <32 x float*>* %b) vscale_r ; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: st1w { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <32 x float>, <32 x float>* %a - %ptrs = load <32 x float*>, <32 x float*>* %b + %vals = load <32 x float>, ptr %a + %ptrs = load <32 x ptr>, ptr %b %mask = fcmp oeq <32 x float> %vals, zeroinitializer - call void @llvm.masked.scatter.v32f32(<32 x float> %vals, <32 x float*> %ptrs, i32 8, <32 x i1> %mask) + call void @llvm.masked.scatter.v32f32(<32 x float> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask) ret void } @@ -793,7 +793,7 @@ define void @masked_scatter_v32f32(<32 x float>* %a, <32 x float*>* %b) vscale_r ; ; Scalarize 1 x double scatters -define void @masked_scatter_v1f64(<1 x double>* %a, <1 x double*>* %b) vscale_range(8,0) #0 { +define void @masked_scatter_v1f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_scatter_v1f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -805,14 +805,14 @@ define void @masked_scatter_v1f64(<1 x double>* %a, <1 x double*>* %b) vscale_ra ; CHECK-NEXT: str d0, [x8] ; CHECK-NEXT: .LBB31_2: // %else ; CHECK-NEXT: ret - %vals = load <1 x double>, <1 x double>* %a - %ptrs = load <1 x double*>, <1 x double*>* %b + %vals = load <1 x double>, ptr %a + %ptrs = load <1 x ptr>, ptr %b %mask = fcmp oeq <1 x double> %vals, zeroinitializer - call void @llvm.masked.scatter.v1f64(<1 x double> %vals, <1 x double*> %ptrs, i32 8, <1 x i1> %mask) + call void @llvm.masked.scatter.v1f64(<1 x double> %vals, <1 x ptr> %ptrs, i32 8, <1 x i1> %mask) ret void } -define void @masked_scatter_v2f64(<2 x double>* %a, <2 x double*>* %b) vscale_range(2,0) #0 { +define void @masked_scatter_v2f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_scatter_v2f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -822,14 +822,14 @@ define void @masked_scatter_v2f64(<2 x double>* %a, <2 x double*>* %b) vscale_ra ; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, #0 ; CHECK-NEXT: st1d { z0.d }, p0, [z2.d] ; CHECK-NEXT: ret - %vals = load <2 x double>, <2 x double>* %a - %ptrs = load <2 x double*>, <2 x double*>* %b + %vals = load <2 x double>, ptr %a + %ptrs = load <2 x ptr>, ptr %b %mask = fcmp oeq <2 x double> %vals, zeroinitializer - call void @llvm.masked.scatter.v2f64(<2 x double> %vals, <2 x double*> %ptrs, i32 8, <2 x i1> %mask) + call void @llvm.masked.scatter.v2f64(<2 x double> %vals, <2 x ptr> %ptrs, i32 8, <2 x i1> %mask) ret void } -define void @masked_scatter_v4f64(<4 x double>* %a, <4 x double*>* %b) vscale_range(2,0) #0 { +define void @masked_scatter_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_scatter_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -838,14 +838,14 @@ define void @masked_scatter_v4f64(<4 x double>* %a, <4 x double*>* %b) vscale_ra ; CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, #0.0 ; CHECK-NEXT: st1d { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <4 x double>, <4 x double>* %a - %ptrs = load <4 x double*>, <4 x double*>* %b + %vals = load <4 x double>, ptr %a + %ptrs = load <4 x ptr>, ptr %b %mask = fcmp oeq <4 x double> %vals, zeroinitializer - call void @llvm.masked.scatter.v4f64(<4 x double> %vals, <4 x double*> %ptrs, i32 8, <4 x i1> %mask) + call void @llvm.masked.scatter.v4f64(<4 x double> %vals, <4 x ptr> %ptrs, i32 8, <4 x i1> %mask) ret void } -define void @masked_scatter_v8f64(<8 x double>* %a, <8 x double*>* %b) #0 { +define void @masked_scatter_v8f64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: masked_scatter_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -868,14 +868,14 @@ define void @masked_scatter_v8f64(<8 x double>* %a, <8 x double*>* %b) #0 { ; VBITS_GE_512-NEXT: fcmeq p0.d, p0/z, z0.d, #0.0 ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [z1.d] ; VBITS_GE_512-NEXT: ret - %vals = load <8 x double>, <8 x double>* %a - %ptrs = load <8 x double*>, <8 x double*>* %b + %vals = load <8 x double>, ptr %a + %ptrs = load <8 x ptr>, ptr %b %mask = fcmp oeq <8 x double> %vals, zeroinitializer - call void @llvm.masked.scatter.v8f64(<8 x double> %vals, <8 x double*> %ptrs, i32 8, <8 x i1> %mask) + call void @llvm.masked.scatter.v8f64(<8 x double> %vals, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask) ret void } -define void @masked_scatter_v16f64(<16 x double>* %a, <16 x double*>* %b) vscale_range(8,0) #0 { +define void @masked_scatter_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_scatter_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -884,14 +884,14 @@ define void @masked_scatter_v16f64(<16 x double>* %a, <16 x double*>* %b) vscale ; CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, #0.0 ; CHECK-NEXT: st1d { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <16 x double>, <16 x double>* %a - %ptrs = load <16 x double*>, <16 x double*>* %b + %vals = load <16 x double>, ptr %a + %ptrs = load <16 x ptr>, ptr %b %mask = fcmp oeq <16 x double> %vals, zeroinitializer - call void @llvm.masked.scatter.v16f64(<16 x double> %vals, <16 x double*> %ptrs, i32 8, <16 x i1> %mask) + call void @llvm.masked.scatter.v16f64(<16 x double> %vals, <16 x ptr> %ptrs, i32 8, <16 x i1> %mask) ret void } -define void @masked_scatter_v32f64(<32 x double>* %a, <32 x double*>* %b) vscale_range(16,0) #0 { +define void @masked_scatter_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_scatter_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -900,17 +900,17 @@ define void @masked_scatter_v32f64(<32 x double>* %a, <32 x double*>* %b) vscale ; CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, #0.0 ; CHECK-NEXT: st1d { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret - %vals = load <32 x double>, <32 x double>* %a - %ptrs = load <32 x double*>, <32 x double*>* %b + %vals = load <32 x double>, ptr %a + %ptrs = load <32 x ptr>, ptr %b %mask = fcmp oeq <32 x double> %vals, zeroinitializer - call void @llvm.masked.scatter.v32f64(<32 x double> %vals, <32 x double*> %ptrs, i32 8, <32 x i1> %mask) + call void @llvm.masked.scatter.v32f64(<32 x double> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask) ret void } ; The above tests test the types, the below tests check that the addressing ; modes still function -define void @masked_scatter_32b_scaled_sext_f16(<32 x half>* %a, <32 x i32>* %b, half* %base) vscale_range(16,0) #0 { +define void @masked_scatter_32b_scaled_sext_f16(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_scatter_32b_scaled_sext_f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -922,16 +922,16 @@ define void @masked_scatter_32b_scaled_sext_f16(<32 x half>* %a, <32 x i32>* %b, ; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: st1h { z0.s }, p0, [x2, z1.s, sxtw #1] ; CHECK-NEXT: ret - %vals = load <32 x half>, <32 x half>* %a - %idxs = load <32 x i32>, <32 x i32>* %b + %vals = load <32 x half>, ptr %a + %idxs = load <32 x i32>, ptr %b %ext = sext <32 x i32> %idxs to <32 x i64> - %ptrs = getelementptr half, half* %base, <32 x i64> %ext + %ptrs = getelementptr half, ptr %base, <32 x i64> %ext %mask = fcmp oeq <32 x half> %vals, zeroinitializer - call void @llvm.masked.scatter.v32f16(<32 x half> %vals, <32 x half*> %ptrs, i32 8, <32 x i1> %mask) + call void @llvm.masked.scatter.v32f16(<32 x half> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask) ret void } -define void @masked_scatter_32b_scaled_sext_f32(<32 x float>* %a, <32 x i32>* %b, float* %base) vscale_range(16,0) #0 { +define void @masked_scatter_32b_scaled_sext_f32(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_scatter_32b_scaled_sext_f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -940,16 +940,16 @@ define void @masked_scatter_32b_scaled_sext_f32(<32 x float>* %a, <32 x i32>* %b ; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0 ; CHECK-NEXT: st1w { z0.s }, p0, [x2, z1.s, sxtw #2] ; CHECK-NEXT: ret - %vals = load <32 x float>, <32 x float>* %a - %idxs = load <32 x i32>, <32 x i32>* %b + %vals = load <32 x float>, ptr %a + %idxs = load <32 x i32>, ptr %b %ext = sext <32 x i32> %idxs to <32 x i64> - %ptrs = getelementptr float, float* %base, <32 x i64> %ext + %ptrs = getelementptr float, ptr %base, <32 x i64> %ext %mask = fcmp oeq <32 x float> %vals, zeroinitializer - call void @llvm.masked.scatter.v32f32(<32 x float> %vals, <32 x float*> %ptrs, i32 8, <32 x i1> %mask) + call void @llvm.masked.scatter.v32f32(<32 x float> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask) ret void } -define void @masked_scatter_32b_scaled_sext_f64(<32 x double>* %a, <32 x i32>* %b, double* %base) vscale_range(16,0) #0 { +define void @masked_scatter_32b_scaled_sext_f64(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_scatter_32b_scaled_sext_f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -958,16 +958,16 @@ define void @masked_scatter_32b_scaled_sext_f64(<32 x double>* %a, <32 x i32>* % ; CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, #0.0 ; CHECK-NEXT: st1d { z0.d }, p0, [x2, z1.d, lsl #3] ; CHECK-NEXT: ret - %vals = load <32 x double>, <32 x double>* %a - %idxs = load <32 x i32>, <32 x i32>* %b + %vals = load <32 x double>, ptr %a + %idxs = load <32 x i32>, ptr %b %ext = sext <32 x i32> %idxs to <32 x i64> - %ptrs = getelementptr double, double* %base, <32 x i64> %ext + %ptrs = getelementptr double, ptr %base, <32 x i64> %ext %mask = fcmp oeq <32 x double> %vals, zeroinitializer - call void @llvm.masked.scatter.v32f64(<32 x double> %vals, <32 x double*> %ptrs, i32 8, <32 x i1> %mask) + call void @llvm.masked.scatter.v32f64(<32 x double> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask) ret void } -define void @masked_scatter_32b_scaled_zext(<32 x half>* %a, <32 x i32>* %b, half* %base) vscale_range(16,0) #0 { +define void @masked_scatter_32b_scaled_zext(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_scatter_32b_scaled_zext: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -979,16 +979,16 @@ define void @masked_scatter_32b_scaled_zext(<32 x half>* %a, <32 x i32>* %b, hal ; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: st1h { z0.s }, p0, [x2, z1.s, uxtw #1] ; CHECK-NEXT: ret - %vals = load <32 x half>, <32 x half>* %a - %idxs = load <32 x i32>, <32 x i32>* %b + %vals = load <32 x half>, ptr %a + %idxs = load <32 x i32>, ptr %b %ext = zext <32 x i32> %idxs to <32 x i64> - %ptrs = getelementptr half, half* %base, <32 x i64> %ext + %ptrs = getelementptr half, ptr %base, <32 x i64> %ext %mask = fcmp oeq <32 x half> %vals, zeroinitializer - call void @llvm.masked.scatter.v32f16(<32 x half> %vals, <32 x half*> %ptrs, i32 8, <32 x i1> %mask) + call void @llvm.masked.scatter.v32f16(<32 x half> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask) ret void } -define void @masked_scatter_32b_unscaled_sext(<32 x half>* %a, <32 x i32>* %b, i8* %base) vscale_range(16,0) #0 { +define void @masked_scatter_32b_unscaled_sext(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_scatter_32b_unscaled_sext: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -1000,17 +1000,17 @@ define void @masked_scatter_32b_unscaled_sext(<32 x half>* %a, <32 x i32>* %b, i ; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: st1h { z0.s }, p0, [x2, z1.s, sxtw] ; CHECK-NEXT: ret - %vals = load <32 x half>, <32 x half>* %a - %idxs = load <32 x i32>, <32 x i32>* %b + %vals = load <32 x half>, ptr %a + %idxs = load <32 x i32>, ptr %b %ext = sext <32 x i32> %idxs to <32 x i64> - %byte_ptrs = getelementptr i8, i8* %base, <32 x i64> %ext - %ptrs = bitcast <32 x i8*> %byte_ptrs to <32 x half*> + %byte_ptrs = getelementptr i8, ptr %base, <32 x i64> %ext + %ptrs = bitcast <32 x ptr> %byte_ptrs to <32 x ptr> %mask = fcmp oeq <32 x half> %vals, zeroinitializer - call void @llvm.masked.scatter.v32f16(<32 x half> %vals, <32 x half*> %ptrs, i32 8, <32 x i1> %mask) + call void @llvm.masked.scatter.v32f16(<32 x half> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask) ret void } -define void @masked_scatter_32b_unscaled_zext(<32 x half>* %a, <32 x i32>* %b, i8* %base) vscale_range(16,0) #0 { +define void @masked_scatter_32b_unscaled_zext(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_scatter_32b_unscaled_zext: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl32 @@ -1022,17 +1022,17 @@ define void @masked_scatter_32b_unscaled_zext(<32 x half>* %a, <32 x i32>* %b, i ; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: st1h { z0.s }, p0, [x2, z1.s, uxtw] ; CHECK-NEXT: ret - %vals = load <32 x half>, <32 x half>* %a - %idxs = load <32 x i32>, <32 x i32>* %b + %vals = load <32 x half>, ptr %a + %idxs = load <32 x i32>, ptr %b %ext = zext <32 x i32> %idxs to <32 x i64> - %byte_ptrs = getelementptr i8, i8* %base, <32 x i64> %ext - %ptrs = bitcast <32 x i8*> %byte_ptrs to <32 x half*> + %byte_ptrs = getelementptr i8, ptr %base, <32 x i64> %ext + %ptrs = bitcast <32 x ptr> %byte_ptrs to <32 x ptr> %mask = fcmp oeq <32 x half> %vals, zeroinitializer - call void @llvm.masked.scatter.v32f16(<32 x half> %vals, <32 x half*> %ptrs, i32 8, <32 x i1> %mask) + call void @llvm.masked.scatter.v32f16(<32 x half> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask) ret void } -define void @masked_scatter_64b_scaled(<32 x float>* %a, <32 x i64>* %b, float* %base) vscale_range(16,0) #0 { +define void @masked_scatter_64b_scaled(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_scatter_64b_scaled: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1044,15 +1044,15 @@ define void @masked_scatter_64b_scaled(<32 x float>* %a, <32 x i64>* %b, float* ; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: st1w { z0.d }, p0, [x2, z1.d, lsl #2] ; CHECK-NEXT: ret - %vals = load <32 x float>, <32 x float>* %a - %idxs = load <32 x i64>, <32 x i64>* %b - %ptrs = getelementptr float, float* %base, <32 x i64> %idxs + %vals = load <32 x float>, ptr %a + %idxs = load <32 x i64>, ptr %b + %ptrs = getelementptr float, ptr %base, <32 x i64> %idxs %mask = fcmp oeq <32 x float> %vals, zeroinitializer - call void @llvm.masked.scatter.v32f32(<32 x float> %vals, <32 x float*> %ptrs, i32 8, <32 x i1> %mask) + call void @llvm.masked.scatter.v32f32(<32 x float> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask) ret void } -define void @masked_scatter_64b_unscaled(<32 x float>* %a, <32 x i64>* %b, i8* %base) vscale_range(16,0) #0 { +define void @masked_scatter_64b_unscaled(ptr %a, ptr %b, ptr %base) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_scatter_64b_unscaled: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1064,16 +1064,16 @@ define void @masked_scatter_64b_unscaled(<32 x float>* %a, <32 x i64>* %b, i8* % ; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: st1w { z0.d }, p0, [x2, z1.d] ; CHECK-NEXT: ret - %vals = load <32 x float>, <32 x float>* %a - %idxs = load <32 x i64>, <32 x i64>* %b - %byte_ptrs = getelementptr i8, i8* %base, <32 x i64> %idxs - %ptrs = bitcast <32 x i8*> %byte_ptrs to <32 x float*> + %vals = load <32 x float>, ptr %a + %idxs = load <32 x i64>, ptr %b + %byte_ptrs = getelementptr i8, ptr %base, <32 x i64> %idxs + %ptrs = bitcast <32 x ptr> %byte_ptrs to <32 x ptr> %mask = fcmp oeq <32 x float> %vals, zeroinitializer - call void @llvm.masked.scatter.v32f32(<32 x float> %vals, <32 x float*> %ptrs, i32 8, <32 x i1> %mask) + call void @llvm.masked.scatter.v32f32(<32 x float> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask) ret void } -define void @masked_scatter_vec_plus_reg(<32 x float>* %a, <32 x i8*>* %b, i64 %off) vscale_range(16,0) #0 { +define void @masked_scatter_vec_plus_reg(ptr %a, ptr %b, i64 %off) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_scatter_vec_plus_reg: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1085,16 +1085,16 @@ define void @masked_scatter_vec_plus_reg(<32 x float>* %a, <32 x i8*>* %b, i64 % ; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: st1w { z0.d }, p0, [x2, z1.d] ; CHECK-NEXT: ret - %vals = load <32 x float>, <32 x float>* %a - %bases = load <32 x i8*>, <32 x i8*>* %b - %byte_ptrs = getelementptr i8, <32 x i8*> %bases, i64 %off - %ptrs = bitcast <32 x i8*> %byte_ptrs to <32 x float*> + %vals = load <32 x float>, ptr %a + %bases = load <32 x ptr>, ptr %b + %byte_ptrs = getelementptr i8, <32 x ptr> %bases, i64 %off + %ptrs = bitcast <32 x ptr> %byte_ptrs to <32 x ptr> %mask = fcmp oeq <32 x float> %vals, zeroinitializer - call void @llvm.masked.scatter.v32f32(<32 x float> %vals, <32 x float*> %ptrs, i32 8, <32 x i1> %mask) + call void @llvm.masked.scatter.v32f32(<32 x float> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask) ret void } -define void @masked_scatter_vec_plus_imm(<32 x float>* %a, <32 x i8*>* %b) vscale_range(16,0) #0 { +define void @masked_scatter_vec_plus_imm(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_scatter_vec_plus_imm: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -1106,12 +1106,12 @@ define void @masked_scatter_vec_plus_imm(<32 x float>* %a, <32 x i8*>* %b) vscal ; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: st1w { z0.d }, p0, [z1.d, #4] ; CHECK-NEXT: ret - %vals = load <32 x float>, <32 x float>* %a - %bases = load <32 x i8*>, <32 x i8*>* %b - %byte_ptrs = getelementptr i8, <32 x i8*> %bases, i64 4 - %ptrs = bitcast <32 x i8*> %byte_ptrs to <32 x float*> + %vals = load <32 x float>, ptr %a + %bases = load <32 x ptr>, ptr %b + %byte_ptrs = getelementptr i8, <32 x ptr> %bases, i64 4 + %ptrs = bitcast <32 x ptr> %byte_ptrs to <32 x ptr> %mask = fcmp oeq <32 x float> %vals, zeroinitializer - call void @llvm.masked.scatter.v32f32(<32 x float> %vals, <32 x float*> %ptrs, i32 8, <32 x i1> %mask) + call void @llvm.masked.scatter.v32f32(<32 x float> %vals, <32 x ptr> %ptrs, i32 8, <32 x i1> %mask) ret void } @@ -1123,7 +1123,7 @@ define void @masked_scatter_vec_plus_imm(<32 x float>* %a, <32 x i8*>* %b) vscal ; NOTE: For this test to function correctly it's critical for %vals to be in a ; different block to the scatter store. If not, the problematic bitcast will be ; removed before operation legalisation and thus not exercise the combine. -define void @masked_scatter_bitcast_infinite_loop(<8 x double>* %a, <8 x double*>* %b, i1 %cond) vscale_range(4,0) #0 { +define void @masked_scatter_bitcast_infinite_loop(ptr %a, ptr %b, i1 %cond) vscale_range(4,0) #0 { ; CHECK-LABEL: masked_scatter_bitcast_infinite_loop: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl8 @@ -1135,61 +1135,61 @@ define void @masked_scatter_bitcast_infinite_loop(<8 x double>* %a, <8 x double* ; CHECK-NEXT: st1d { z0.d }, p0, [z1.d] ; CHECK-NEXT: .LBB47_2: // %bb.2 ; CHECK-NEXT: ret - %vals = load volatile <8 x double>, <8 x double>* %a + %vals = load volatile <8 x double>, ptr %a br i1 %cond, label %bb.1, label %bb.2 bb.1: - %ptrs = load <8 x double*>, <8 x double*>* %b + %ptrs = load <8 x ptr>, ptr %b %mask = fcmp oeq <8 x double> %vals, zeroinitializer - call void @llvm.masked.scatter.v8f64(<8 x double> %vals, <8 x double*> %ptrs, i32 8, <8 x i1> %mask) + call void @llvm.masked.scatter.v8f64(<8 x double> %vals, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask) br label %bb.2 bb.2: ret void } -declare void @llvm.masked.scatter.v2i8(<2 x i8>, <2 x i8*>, i32, <2 x i1>) -declare void @llvm.masked.scatter.v4i8(<4 x i8>, <4 x i8*>, i32, <4 x i1>) -declare void @llvm.masked.scatter.v8i8(<8 x i8>, <8 x i8*>, i32, <8 x i1>) -declare void @llvm.masked.scatter.v16i8(<16 x i8>, <16 x i8*>, i32, <16 x i1>) -declare void @llvm.masked.scatter.v32i8(<32 x i8>, <32 x i8*>, i32, <32 x i1>) - -declare void @llvm.masked.scatter.v2i16(<2 x i16>, <2 x i16*>, i32, <2 x i1>) -declare void @llvm.masked.scatter.v4i16(<4 x i16>, <4 x i16*>, i32, <4 x i1>) -declare void @llvm.masked.scatter.v8i16(<8 x i16>, <8 x i16*>, i32, <8 x i1>) -declare void @llvm.masked.scatter.v16i16(<16 x i16>, <16 x i16*>, i32, <16 x i1>) -declare void @llvm.masked.scatter.v32i16(<32 x i16>, <32 x i16*>, i32, <32 x i1>) - -declare void @llvm.masked.scatter.v2i32(<2 x i32>, <2 x i32*>, i32, <2 x i1>) -declare void @llvm.masked.scatter.v4i32(<4 x i32>, <4 x i32*>, i32, <4 x i1>) -declare void @llvm.masked.scatter.v8i32(<8 x i32>, <8 x i32*>, i32, <8 x i1>) -declare void @llvm.masked.scatter.v16i32(<16 x i32>, <16 x i32*>, i32, <16 x i1>) -declare void @llvm.masked.scatter.v32i32(<32 x i32>, <32 x i32*>, i32, <32 x i1>) - -declare void @llvm.masked.scatter.v1i64(<1 x i64>, <1 x i64*>, i32, <1 x i1>) -declare void @llvm.masked.scatter.v2i64(<2 x i64>, <2 x i64*>, i32, <2 x i1>) -declare void @llvm.masked.scatter.v4i64(<4 x i64>, <4 x i64*>, i32, <4 x i1>) -declare void @llvm.masked.scatter.v8i64(<8 x i64>, <8 x i64*>, i32, <8 x i1>) -declare void @llvm.masked.scatter.v16i64(<16 x i64>, <16 x i64*>, i32, <16 x i1>) -declare void @llvm.masked.scatter.v32i64(<32 x i64>, <32 x i64*>, i32, <32 x i1>) - -declare void @llvm.masked.scatter.v2f16(<2 x half>, <2 x half*>, i32, <2 x i1>) -declare void @llvm.masked.scatter.v4f16(<4 x half>, <4 x half*>, i32, <4 x i1>) -declare void @llvm.masked.scatter.v8f16(<8 x half>, <8 x half*>, i32, <8 x i1>) -declare void @llvm.masked.scatter.v16f16(<16 x half>, <16 x half*>, i32, <16 x i1>) -declare void @llvm.masked.scatter.v32f16(<32 x half>, <32 x half*>, i32, <32 x i1>) - -declare void @llvm.masked.scatter.v2f32(<2 x float>, <2 x float*>, i32, <2 x i1>) -declare void @llvm.masked.scatter.v4f32(<4 x float>, <4 x float*>, i32, <4 x i1>) -declare void @llvm.masked.scatter.v8f32(<8 x float>, <8 x float*>, i32, <8 x i1>) -declare void @llvm.masked.scatter.v16f32(<16 x float>, <16 x float*>, i32, <16 x i1>) -declare void @llvm.masked.scatter.v32f32(<32 x float>, <32 x float*>, i32, <32 x i1>) - -declare void @llvm.masked.scatter.v1f64(<1 x double>, <1 x double*>, i32, <1 x i1>) -declare void @llvm.masked.scatter.v2f64(<2 x double>, <2 x double*>, i32, <2 x i1>) -declare void @llvm.masked.scatter.v4f64(<4 x double>, <4 x double*>, i32, <4 x i1>) -declare void @llvm.masked.scatter.v8f64(<8 x double>, <8 x double*>, i32, <8 x i1>) -declare void @llvm.masked.scatter.v16f64(<16 x double>, <16 x double*>, i32, <16 x i1>) -declare void @llvm.masked.scatter.v32f64(<32 x double>, <32 x double*>, i32, <32 x i1>) +declare void @llvm.masked.scatter.v2i8(<2 x i8>, <2 x ptr>, i32, <2 x i1>) +declare void @llvm.masked.scatter.v4i8(<4 x i8>, <4 x ptr>, i32, <4 x i1>) +declare void @llvm.masked.scatter.v8i8(<8 x i8>, <8 x ptr>, i32, <8 x i1>) +declare void @llvm.masked.scatter.v16i8(<16 x i8>, <16 x ptr>, i32, <16 x i1>) +declare void @llvm.masked.scatter.v32i8(<32 x i8>, <32 x ptr>, i32, <32 x i1>) + +declare void @llvm.masked.scatter.v2i16(<2 x i16>, <2 x ptr>, i32, <2 x i1>) +declare void @llvm.masked.scatter.v4i16(<4 x i16>, <4 x ptr>, i32, <4 x i1>) +declare void @llvm.masked.scatter.v8i16(<8 x i16>, <8 x ptr>, i32, <8 x i1>) +declare void @llvm.masked.scatter.v16i16(<16 x i16>, <16 x ptr>, i32, <16 x i1>) +declare void @llvm.masked.scatter.v32i16(<32 x i16>, <32 x ptr>, i32, <32 x i1>) + +declare void @llvm.masked.scatter.v2i32(<2 x i32>, <2 x ptr>, i32, <2 x i1>) +declare void @llvm.masked.scatter.v4i32(<4 x i32>, <4 x ptr>, i32, <4 x i1>) +declare void @llvm.masked.scatter.v8i32(<8 x i32>, <8 x ptr>, i32, <8 x i1>) +declare void @llvm.masked.scatter.v16i32(<16 x i32>, <16 x ptr>, i32, <16 x i1>) +declare void @llvm.masked.scatter.v32i32(<32 x i32>, <32 x ptr>, i32, <32 x i1>) + +declare void @llvm.masked.scatter.v1i64(<1 x i64>, <1 x ptr>, i32, <1 x i1>) +declare void @llvm.masked.scatter.v2i64(<2 x i64>, <2 x ptr>, i32, <2 x i1>) +declare void @llvm.masked.scatter.v4i64(<4 x i64>, <4 x ptr>, i32, <4 x i1>) +declare void @llvm.masked.scatter.v8i64(<8 x i64>, <8 x ptr>, i32, <8 x i1>) +declare void @llvm.masked.scatter.v16i64(<16 x i64>, <16 x ptr>, i32, <16 x i1>) +declare void @llvm.masked.scatter.v32i64(<32 x i64>, <32 x ptr>, i32, <32 x i1>) + +declare void @llvm.masked.scatter.v2f16(<2 x half>, <2 x ptr>, i32, <2 x i1>) +declare void @llvm.masked.scatter.v4f16(<4 x half>, <4 x ptr>, i32, <4 x i1>) +declare void @llvm.masked.scatter.v8f16(<8 x half>, <8 x ptr>, i32, <8 x i1>) +declare void @llvm.masked.scatter.v16f16(<16 x half>, <16 x ptr>, i32, <16 x i1>) +declare void @llvm.masked.scatter.v32f16(<32 x half>, <32 x ptr>, i32, <32 x i1>) + +declare void @llvm.masked.scatter.v2f32(<2 x float>, <2 x ptr>, i32, <2 x i1>) +declare void @llvm.masked.scatter.v4f32(<4 x float>, <4 x ptr>, i32, <4 x i1>) +declare void @llvm.masked.scatter.v8f32(<8 x float>, <8 x ptr>, i32, <8 x i1>) +declare void @llvm.masked.scatter.v16f32(<16 x float>, <16 x ptr>, i32, <16 x i1>) +declare void @llvm.masked.scatter.v32f32(<32 x float>, <32 x ptr>, i32, <32 x i1>) + +declare void @llvm.masked.scatter.v1f64(<1 x double>, <1 x ptr>, i32, <1 x i1>) +declare void @llvm.masked.scatter.v2f64(<2 x double>, <2 x ptr>, i32, <2 x i1>) +declare void @llvm.masked.scatter.v4f64(<4 x double>, <4 x ptr>, i32, <4 x i1>) +declare void @llvm.masked.scatter.v8f64(<8 x double>, <8 x ptr>, i32, <8 x i1>) +declare void @llvm.masked.scatter.v16f64(<16 x double>, <16 x ptr>, i32, <16 x i1>) +declare void @llvm.masked.scatter.v32f64(<32 x double>, <32 x ptr>, i32, <32 x i1>) attributes #0 = { "target-features"="+sve" } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll index 28dbe7c..4156da2 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll @@ -9,7 +9,7 @@ target triple = "aarch64-unknown-linux-gnu" ; Masked Stores ; -define void @masked_store_v2f16(<2 x half>* %ap, <2 x half>* %bp) vscale_range(2,0) #0 { +define void @masked_store_v2f16(ptr %ap, ptr %bp) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_store_v2f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr s1, [x0] @@ -27,14 +27,14 @@ define void @masked_store_v2f16(<2 x half>* %ap, <2 x half>* %bp) vscale_range(2 ; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #0 ; CHECK-NEXT: st1h { z1.h }, p0, [x1] ; CHECK-NEXT: ret - %a = load <2 x half>, <2 x half>* %ap - %b = load <2 x half>, <2 x half>* %bp + %a = load <2 x half>, ptr %ap + %b = load <2 x half>, ptr %bp %mask = fcmp oeq <2 x half> %a, %b - call void @llvm.masked.store.v2f16(<2 x half> %a, <2 x half>* %bp, i32 8, <2 x i1> %mask) + call void @llvm.masked.store.v2f16(<2 x half> %a, ptr %bp, i32 8, <2 x i1> %mask) ret void } -define void @masked_store_v2f32(<2 x float>* %ap, <2 x float>* %bp) vscale_range(2,0) #0 { +define void @masked_store_v2f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_store_v2f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -44,14 +44,14 @@ define void @masked_store_v2f32(<2 x float>* %ap, <2 x float>* %bp) vscale_range ; CHECK-NEXT: cmpne p0.s, p0/z, z1.s, #0 ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <2 x float>, <2 x float>* %ap - %b = load <2 x float>, <2 x float>* %bp + %a = load <2 x float>, ptr %ap + %b = load <2 x float>, ptr %bp %mask = fcmp oeq <2 x float> %a, %b - call void @llvm.masked.store.v2f32(<2 x float> %a, <2 x float>* %bp, i32 8, <2 x i1> %mask) + call void @llvm.masked.store.v2f32(<2 x float> %a, ptr %bp, i32 8, <2 x i1> %mask) ret void } -define void @masked_store_v4f32(<4 x float>* %ap, <4 x float>* %bp) vscale_range(2,0) #0 { +define void @masked_store_v4f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_store_v4f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -61,14 +61,14 @@ define void @masked_store_v4f32(<4 x float>* %ap, <4 x float>* %bp) vscale_range ; CHECK-NEXT: cmpne p0.s, p0/z, z1.s, #0 ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <4 x float>, <4 x float>* %ap - %b = load <4 x float>, <4 x float>* %bp + %a = load <4 x float>, ptr %ap + %b = load <4 x float>, ptr %bp %mask = fcmp oeq <4 x float> %a, %b - call void @llvm.masked.store.v4f32(<4 x float> %a, <4 x float>* %bp, i32 8, <4 x i1> %mask) + call void @llvm.masked.store.v4f32(<4 x float> %a, ptr %bp, i32 8, <4 x i1> %mask) ret void } -define void @masked_store_v8f32(<8 x float>* %ap, <8 x float>* %bp) vscale_range(2,0) #0 { +define void @masked_store_v8f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 { ; CHECK-LABEL: masked_store_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -77,14 +77,14 @@ define void @masked_store_v8f32(<8 x float>* %ap, <8 x float>* %bp) vscale_range ; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <8 x float>, <8 x float>* %ap - %b = load <8 x float>, <8 x float>* %bp + %a = load <8 x float>, ptr %ap + %b = load <8 x float>, ptr %bp %mask = fcmp oeq <8 x float> %a, %b - call void @llvm.masked.store.v8f32(<8 x float> %a, <8 x float>* %bp, i32 8, <8 x i1> %mask) + call void @llvm.masked.store.v8f32(<8 x float> %a, ptr %bp, i32 8, <8 x i1> %mask) ret void } -define void @masked_store_v16f32(<16 x float>* %ap, <16 x float>* %bp) #0 { +define void @masked_store_v16f32(ptr %ap, ptr %bp) #0 { ; VBITS_GE_256-LABEL: masked_store_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -107,14 +107,14 @@ define void @masked_store_v16f32(<16 x float>* %ap, <16 x float>* %bp) #0 { ; VBITS_GE_512-NEXT: fcmeq p0.s, p0/z, z0.s, z1.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %a = load <16 x float>, <16 x float>* %ap - %b = load <16 x float>, <16 x float>* %bp + %a = load <16 x float>, ptr %ap + %b = load <16 x float>, ptr %bp %mask = fcmp oeq <16 x float> %a, %b - call void @llvm.masked.store.v16f32(<16 x float> %a, <16 x float>* %ap, i32 8, <16 x i1> %mask) + call void @llvm.masked.store.v16f32(<16 x float> %a, ptr %ap, i32 8, <16 x i1> %mask) ret void } -define void @masked_store_v32f32(<32 x float>* %ap, <32 x float>* %bp) vscale_range(8,0) #0 { +define void @masked_store_v32f32(ptr %ap, ptr %bp) vscale_range(8,0) #0 { ; CHECK-LABEL: masked_store_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -123,14 +123,14 @@ define void @masked_store_v32f32(<32 x float>* %ap, <32 x float>* %bp) vscale_ra ; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %a = load <32 x float>, <32 x float>* %ap - %b = load <32 x float>, <32 x float>* %bp + %a = load <32 x float>, ptr %ap + %b = load <32 x float>, ptr %bp %mask = fcmp oeq <32 x float> %a, %b - call void @llvm.masked.store.v32f32(<32 x float> %a, <32 x float>* %ap, i32 8, <32 x i1> %mask) + call void @llvm.masked.store.v32f32(<32 x float> %a, ptr %ap, i32 8, <32 x i1> %mask) ret void } -define void @masked_store_v64f32(<64 x float>* %ap, <64 x float>* %bp) vscale_range(16,0) #0 { +define void @masked_store_v64f32(ptr %ap, ptr %bp) vscale_range(16,0) #0 { ; CHECK-LABEL: masked_store_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -139,14 +139,14 @@ define void @masked_store_v64f32(<64 x float>* %ap, <64 x float>* %bp) vscale_ra ; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %a = load <64 x float>, <64 x float>* %ap - %b = load <64 x float>, <64 x float>* %bp + %a = load <64 x float>, ptr %ap + %b = load <64 x float>, ptr %bp %mask = fcmp oeq <64 x float> %a, %b - call void @llvm.masked.store.v64f32(<64 x float> %a, <64 x float>* %ap, i32 8, <64 x i1> %mask) + call void @llvm.masked.store.v64f32(<64 x float> %a, ptr %ap, i32 8, <64 x i1> %mask) ret void } -define void @masked_store_trunc_v8i64i8(<8 x i64>* %ap, <8 x i64>* %bp, <8 x i8>* %dest) #0 { +define void @masked_store_trunc_v8i64i8(ptr %ap, ptr %bp, ptr %dest) #0 { ; VBITS_GE_256-LABEL: masked_store_trunc_v8i64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -179,15 +179,15 @@ define void @masked_store_trunc_v8i64i8(<8 x i64>* %ap, <8 x i64>* %bp, <8 x i8> ; VBITS_GE_512-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d ; VBITS_GE_512-NEXT: st1b { z0.d }, p0, [x2] ; VBITS_GE_512-NEXT: ret - %a = load <8 x i64>, <8 x i64>* %ap - %b = load <8 x i64>, <8 x i64>* %bp + %a = load <8 x i64>, ptr %ap + %b = load <8 x i64>, ptr %bp %mask = icmp eq <8 x i64> %a, %b %val = trunc <8 x i64> %a to <8 x i8> - call void @llvm.masked.store.v8i8(<8 x i8> %val, <8 x i8>* %dest, i32 8, <8 x i1> %mask) + call void @llvm.masked.store.v8i8(<8 x i8> %val, ptr %dest, i32 8, <8 x i1> %mask) ret void } -define void @masked_store_trunc_v8i64i16(<8 x i64>* %ap, <8 x i64>* %bp, <8 x i16>* %dest) #0 { +define void @masked_store_trunc_v8i64i16(ptr %ap, ptr %bp, ptr %dest) #0 { ; VBITS_GE_256-LABEL: masked_store_trunc_v8i64i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -223,15 +223,15 @@ define void @masked_store_trunc_v8i64i16(<8 x i64>* %ap, <8 x i64>* %bp, <8 x i1 ; VBITS_GE_512-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d ; VBITS_GE_512-NEXT: st1h { z0.d }, p0, [x2] ; VBITS_GE_512-NEXT: ret - %a = load <8 x i64>, <8 x i64>* %ap - %b = load <8 x i64>, <8 x i64>* %bp + %a = load <8 x i64>, ptr %ap + %b = load <8 x i64>, ptr %bp %mask = icmp eq <8 x i64> %a, %b %val = trunc <8 x i64> %a to <8 x i16> - call void @llvm.masked.store.v8i16(<8 x i16> %val, <8 x i16>* %dest, i32 8, <8 x i1> %mask) + call void @llvm.masked.store.v8i16(<8 x i16> %val, ptr %dest, i32 8, <8 x i1> %mask) ret void } -define void @masked_store_trunc_v8i64i32(<8 x i64>* %ap, <8 x i64>* %bp, <8 x i32>* %dest) #0 { +define void @masked_store_trunc_v8i64i32(ptr %ap, ptr %bp, ptr %dest) #0 { ; VBITS_GE_256-LABEL: masked_store_trunc_v8i64i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -264,15 +264,15 @@ define void @masked_store_trunc_v8i64i32(<8 x i64>* %ap, <8 x i64>* %bp, <8 x i3 ; VBITS_GE_512-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d ; VBITS_GE_512-NEXT: st1w { z0.d }, p0, [x2] ; VBITS_GE_512-NEXT: ret - %a = load <8 x i64>, <8 x i64>* %ap - %b = load <8 x i64>, <8 x i64>* %bp + %a = load <8 x i64>, ptr %ap + %b = load <8 x i64>, ptr %bp %mask = icmp eq <8 x i64> %a, %b %val = trunc <8 x i64> %a to <8 x i32> - call void @llvm.masked.store.v8i32(<8 x i32> %val, <8 x i32>* %dest, i32 8, <8 x i1> %mask) + call void @llvm.masked.store.v8i32(<8 x i32> %val, ptr %dest, i32 8, <8 x i1> %mask) ret void } -define void @masked_store_trunc_v16i32i8(<16 x i32>* %ap, <16 x i32>* %bp, <16 x i8>* %dest) #0 { +define void @masked_store_trunc_v16i32i8(ptr %ap, ptr %bp, ptr %dest) #0 { ; VBITS_GE_256-LABEL: masked_store_trunc_v16i32i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -308,15 +308,15 @@ define void @masked_store_trunc_v16i32i8(<16 x i32>* %ap, <16 x i32>* %bp, <16 x ; VBITS_GE_512-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s ; VBITS_GE_512-NEXT: st1b { z0.s }, p0, [x2] ; VBITS_GE_512-NEXT: ret - %a = load <16 x i32>, <16 x i32>* %ap - %b = load <16 x i32>, <16 x i32>* %bp + %a = load <16 x i32>, ptr %ap + %b = load <16 x i32>, ptr %bp %mask = icmp eq <16 x i32> %a, %b %val = trunc <16 x i32> %a to <16 x i8> - call void @llvm.masked.store.v16i8(<16 x i8> %val, <16 x i8>* %dest, i32 8, <16 x i1> %mask) + call void @llvm.masked.store.v16i8(<16 x i8> %val, ptr %dest, i32 8, <16 x i1> %mask) ret void } -define void @masked_store_trunc_v16i32i16(<16 x i32>* %ap, <16 x i32>* %bp, <16 x i16>* %dest) #0 { +define void @masked_store_trunc_v16i32i16(ptr %ap, ptr %bp, ptr %dest) #0 { ; VBITS_GE_256-LABEL: masked_store_trunc_v16i32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -352,15 +352,15 @@ define void @masked_store_trunc_v16i32i16(<16 x i32>* %ap, <16 x i32>* %bp, <16 ; VBITS_GE_512-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s ; VBITS_GE_512-NEXT: st1h { z0.s }, p0, [x2] ; VBITS_GE_512-NEXT: ret - %a = load <16 x i32>, <16 x i32>* %ap - %b = load <16 x i32>, <16 x i32>* %bp + %a = load <16 x i32>, ptr %ap + %b = load <16 x i32>, ptr %bp %mask = icmp eq <16 x i32> %a, %b %val = trunc <16 x i32> %a to <16 x i16> - call void @llvm.masked.store.v16i16(<16 x i16> %val, <16 x i16>* %dest, i32 8, <16 x i1> %mask) + call void @llvm.masked.store.v16i16(<16 x i16> %val, ptr %dest, i32 8, <16 x i1> %mask) ret void } -define void @masked_store_trunc_v32i16i8(<32 x i16>* %ap, <32 x i16>* %bp, <32 x i8>* %dest) #0 { +define void @masked_store_trunc_v32i16i8(ptr %ap, ptr %bp, ptr %dest) #0 { ; VBITS_GE_256-LABEL: masked_store_trunc_v32i16i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -393,27 +393,27 @@ define void @masked_store_trunc_v32i16i8(<32 x i16>* %ap, <32 x i16>* %bp, <32 x ; VBITS_GE_512-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h ; VBITS_GE_512-NEXT: st1b { z0.h }, p0, [x2] ; VBITS_GE_512-NEXT: ret - %a = load <32 x i16>, <32 x i16>* %ap - %b = load <32 x i16>, <32 x i16>* %bp + %a = load <32 x i16>, ptr %ap + %b = load <32 x i16>, ptr %bp %mask = icmp eq <32 x i16> %a, %b %val = trunc <32 x i16> %a to <32 x i8> - call void @llvm.masked.store.v32i8(<32 x i8> %val, <32 x i8>* %dest, i32 8, <32 x i1> %mask) + call void @llvm.masked.store.v32i8(<32 x i8> %val, ptr %dest, i32 8, <32 x i1> %mask) ret void } -declare void @llvm.masked.store.v2f16(<2 x half>, <2 x half>*, i32, <2 x i1>) -declare void @llvm.masked.store.v2f32(<2 x float>, <2 x float>*, i32, <2 x i1>) -declare void @llvm.masked.store.v4f32(<4 x float>, <4 x float>*, i32, <4 x i1>) -declare void @llvm.masked.store.v8f32(<8 x float>, <8 x float>*, i32, <8 x i1>) -declare void @llvm.masked.store.v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>) -declare void @llvm.masked.store.v32f32(<32 x float>, <32 x float>*, i32, <32 x i1>) -declare void @llvm.masked.store.v64f32(<64 x float>, <64 x float>*, i32, <64 x i1>) +declare void @llvm.masked.store.v2f16(<2 x half>, ptr, i32, <2 x i1>) +declare void @llvm.masked.store.v2f32(<2 x float>, ptr, i32, <2 x i1>) +declare void @llvm.masked.store.v4f32(<4 x float>, ptr, i32, <4 x i1>) +declare void @llvm.masked.store.v8f32(<8 x float>, ptr, i32, <8 x i1>) +declare void @llvm.masked.store.v16f32(<16 x float>, ptr, i32, <16 x i1>) +declare void @llvm.masked.store.v32f32(<32 x float>, ptr, i32, <32 x i1>) +declare void @llvm.masked.store.v64f32(<64 x float>, ptr, i32, <64 x i1>) -declare void @llvm.masked.store.v8i8(<8 x i8>, <8 x i8>*, i32, <8 x i1>) -declare void @llvm.masked.store.v8i16(<8 x i16>, <8 x i16>*, i32, <8 x i1>) -declare void @llvm.masked.store.v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>) -declare void @llvm.masked.store.v16i8(<16 x i8>, <16 x i8>*, i32, <16 x i1>) -declare void @llvm.masked.store.v16i16(<16 x i16>, <16 x i16>*, i32, <16 x i1>) -declare void @llvm.masked.store.v32i8(<32 x i8>, <32 x i8>*, i32, <32 x i1>) +declare void @llvm.masked.store.v8i8(<8 x i8>, ptr, i32, <8 x i1>) +declare void @llvm.masked.store.v8i16(<8 x i16>, ptr, i32, <8 x i1>) +declare void @llvm.masked.store.v8i32(<8 x i32>, ptr, i32, <8 x i1>) +declare void @llvm.masked.store.v16i8(<16 x i8>, ptr, i32, <16 x i1>) +declare void @llvm.masked.store.v16i16(<16 x i16>, ptr, i32, <16 x i1>) +declare void @llvm.masked.store.v32i8(<32 x i8>, ptr, i32, <32 x i1>) attributes #0 = { "target-features"="+sve" } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-optimize-ptrue.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-optimize-ptrue.ll index d7dad2d..1512f54 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-optimize-ptrue.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-optimize-ptrue.ll @@ -3,7 +3,7 @@ target triple = "aarch64-unknown-linux-gnu" -define void @add_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @add_v64i8(ptr %a, ptr %b) #0 { ; CHECK-LABEL: add_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b @@ -12,14 +12,14 @@ define void @add_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; CHECK-NEXT: add z0.b, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %res = add <64 x i8> %op1, %op2 - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @add_v32i16(<32 x i16>* %a, <32 x i16>* %b, <32 x i16>* %c) #0 { +define void @add_v32i16(ptr %a, ptr %b, ptr %c) #0 { ; CHECK-LABEL: add_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h @@ -28,14 +28,14 @@ define void @add_v32i16(<32 x i16>* %a, <32 x i16>* %b, <32 x i16>* %c) #0 { ; CHECK-NEXT: add z0.h, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %res = add <32 x i16> %op1, %op2 - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @abs_v16i32(<16 x i32>* %a) #0 { +define void @abs_v16i32(ptr %a) #0 { ; CHECK-LABEL: abs_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s @@ -43,13 +43,13 @@ define void @abs_v16i32(<16 x i32>* %a) #0 { ; CHECK-NEXT: abs z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %res = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %op1, i1 false) - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @abs_v8i64(<8 x i64>* %a) #0 { +define void @abs_v8i64(ptr %a) #0 { ; CHECK-LABEL: abs_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d @@ -57,13 +57,13 @@ define void @abs_v8i64(<8 x i64>* %a) #0 { ; CHECK-NEXT: abs z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %res = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %op1, i1 false) - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @fadd_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { +define void @fadd_v32f16(ptr %a, ptr %b) #0 { ; CHECK-LABEL: fadd_v32f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h @@ -72,14 +72,14 @@ define void @fadd_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { ; CHECK-NEXT: fadd z0.h, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a - %op2 = load <32 x half>, <32 x half>* %b + %op1 = load <32 x half>, ptr %a + %op2 = load <32 x half>, ptr %b %res = fadd <32 x half> %op1, %op2 - store <32 x half> %res, <32 x half>* %a + store <32 x half> %res, ptr %a ret void } -define void @fadd_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { +define void @fadd_v16f32(ptr %a, ptr %b) #0 { ; CHECK-LABEL: fadd_v16f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s @@ -88,14 +88,14 @@ define void @fadd_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { ; CHECK-NEXT: fadd z0.s, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a - %op2 = load <16 x float>, <16 x float>* %b + %op1 = load <16 x float>, ptr %a + %op2 = load <16 x float>, ptr %b %res = fadd <16 x float> %op1, %op2 - store <16 x float> %res, <16 x float>* %a + store <16 x float> %res, ptr %a ret void } -define void @fadd_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { +define void @fadd_v8f64(ptr %a, ptr %b) #0 { ; CHECK-LABEL: fadd_v8f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d @@ -104,10 +104,10 @@ define void @fadd_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { ; CHECK-NEXT: fadd z0.d, z0.d, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a - %op2 = load <8 x double>, <8 x double>* %b + %op1 = load <8 x double>, ptr %a + %op2 = load <8 x double>, ptr %b %res = fadd <8 x double> %op1, %op2 - store <8 x double> %res, <8 x double>* %a + store <8 x double> %res, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll index 27389a7..49b9b90 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll @@ -5,7 +5,7 @@ target triple = "aarch64-unknown-linux-gnu" ; REVB pattern for shuffle v32i8 -> v16i16 -define void @test_revbv16i16(<32 x i8>* %a) #0 { +define void @test_revbv16i16(ptr %a) #0 { ; CHECK-LABEL: test_revbv16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -14,14 +14,14 @@ define void @test_revbv16i16(<32 x i8>* %a) #0 { ; CHECK-NEXT: revb z0.h, p1/m, z0.h ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <32 x i8>, <32 x i8>* %a + %tmp1 = load <32 x i8>, ptr %a %tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> - store <32 x i8> %tmp2, <32 x i8>* %a + store <32 x i8> %tmp2, ptr %a ret void } ; REVB pattern for shuffle v32i8 -> v8i32 -define void @test_revbv8i32(<32 x i8>* %a) #0 { +define void @test_revbv8i32(ptr %a) #0 { ; CHECK-LABEL: test_revbv8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -30,14 +30,14 @@ define void @test_revbv8i32(<32 x i8>* %a) #0 { ; CHECK-NEXT: revb z0.s, p1/m, z0.s ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <32 x i8>, <32 x i8>* %a + %tmp1 = load <32 x i8>, ptr %a %tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> - store <32 x i8> %tmp2, <32 x i8>* %a + store <32 x i8> %tmp2, ptr %a ret void } ; REVB pattern for shuffle v32i8 -> v4i64 -define void @test_revbv4i64(<32 x i8>* %a) #0 { +define void @test_revbv4i64(ptr %a) #0 { ; CHECK-LABEL: test_revbv4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -46,14 +46,14 @@ define void @test_revbv4i64(<32 x i8>* %a) #0 { ; CHECK-NEXT: revb z0.d, p1/m, z0.d ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <32 x i8>, <32 x i8>* %a + %tmp1 = load <32 x i8>, ptr %a %tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> - store <32 x i8> %tmp2, <32 x i8>* %a + store <32 x i8> %tmp2, ptr %a ret void } ; REVH pattern for shuffle v16i16 -> v8i32 -define void @test_revhv8i32(<16 x i16>* %a) #0 { +define void @test_revhv8i32(ptr %a) #0 { ; CHECK-LABEL: test_revhv8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -62,14 +62,14 @@ define void @test_revhv8i32(<16 x i16>* %a) #0 { ; CHECK-NEXT: revh z0.s, p1/m, z0.s ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <16 x i16>, <16 x i16>* %a + %tmp1 = load <16 x i16>, ptr %a %tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <16 x i32> - store <16 x i16> %tmp2, <16 x i16>* %a + store <16 x i16> %tmp2, ptr %a ret void } ; REVH pattern for shuffle v16f16 -> v8f32 -define void @test_revhv8f32(<16 x half>* %a) #0 { +define void @test_revhv8f32(ptr %a) #0 { ; CHECK-LABEL: test_revhv8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -78,14 +78,14 @@ define void @test_revhv8f32(<16 x half>* %a) #0 { ; CHECK-NEXT: revh z0.s, p1/m, z0.s ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <16 x half>, <16 x half>* %a + %tmp1 = load <16 x half>, ptr %a %tmp2 = shufflevector <16 x half> %tmp1, <16 x half> undef, <16 x i32> - store <16 x half> %tmp2, <16 x half>* %a + store <16 x half> %tmp2, ptr %a ret void } ; REVH pattern for shuffle v16i16 -> v4i64 -define void @test_revhv4i64(<16 x i16>* %a) #0 { +define void @test_revhv4i64(ptr %a) #0 { ; CHECK-LABEL: test_revhv4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -94,14 +94,14 @@ define void @test_revhv4i64(<16 x i16>* %a) #0 { ; CHECK-NEXT: revh z0.d, p1/m, z0.d ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <16 x i16>, <16 x i16>* %a + %tmp1 = load <16 x i16>, ptr %a %tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <16 x i32> - store <16 x i16> %tmp2, <16 x i16>* %a + store <16 x i16> %tmp2, ptr %a ret void } ; REVW pattern for shuffle v8i32 -> v4i64 -define void @test_revwv4i64(<8 x i32>* %a) #0 { +define void @test_revwv4i64(ptr %a) #0 { ; CHECK-LABEL: test_revwv4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -110,14 +110,14 @@ define void @test_revwv4i64(<8 x i32>* %a) #0 { ; CHECK-NEXT: revw z0.d, p1/m, z0.d ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <8 x i32>, <8 x i32>* %a + %tmp1 = load <8 x i32>, ptr %a %tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> - store <8 x i32> %tmp2, <8 x i32>* %a + store <8 x i32> %tmp2, ptr %a ret void } ; REVW pattern for shuffle v8f32 -> v4f64 -define void @test_revwv4f64(<8 x float>* %a) #0 { +define void @test_revwv4f64(ptr %a) #0 { ; CHECK-LABEL: test_revwv4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -126,26 +126,26 @@ define void @test_revwv4f64(<8 x float>* %a) #0 { ; CHECK-NEXT: revw z0.d, p1/m, z0.d ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <8 x float>, <8 x float>* %a + %tmp1 = load <8 x float>, ptr %a %tmp2 = shufflevector <8 x float> %tmp1, <8 x float> undef, <8 x i32> - store <8 x float> %tmp2, <8 x float>* %a + store <8 x float> %tmp2, ptr %a ret void } ; Don't use SVE for 128-bit vectors -define <16 x i8> @test_revv16i8(<16 x i8>* %a) #0 { +define <16 x i8> @test_revv16i8(ptr %a) #0 { ; CHECK-LABEL: test_revv16i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: rev64 v0.16b, v0.16b ; CHECK-NEXT: ret - %tmp1 = load <16 x i8>, <16 x i8>* %a + %tmp1 = load <16 x i8>, ptr %a %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> ret <16 x i8> %tmp2 } ; REVW pattern for shuffle two v8i32 inputs with the second input available. -define void @test_revwv8i32v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 { +define void @test_revwv8i32v8i32(ptr %a, ptr %b) #0 { ; CHECK-LABEL: test_revwv8i32v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -154,15 +154,15 @@ define void @test_revwv8i32v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 { ; CHECK-NEXT: revw z0.d, p1/m, z0.d ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <8 x i32>, <8 x i32>* %a - %tmp2 = load <8 x i32>, <8 x i32>* %b + %tmp1 = load <8 x i32>, ptr %a + %tmp2 = load <8 x i32>, ptr %b %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> %tmp2, <8 x i32> - store <8 x i32> %tmp3, <8 x i32>* %a + store <8 x i32> %tmp3, ptr %a ret void } ; REVH pattern for shuffle v32i16 with 256 bits and 512 bits SVE. -define void @test_revhv32i16(<32 x i16>* %a) #0 { +define void @test_revhv32i16(ptr %a) #0 { ; VBITS_GE_256-LABEL: test_revhv32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -184,14 +184,14 @@ define void @test_revhv32i16(<32 x i16>* %a) #0 { ; VBITS_GE_512-NEXT: revh z0.d, p1/m, z0.d ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %tmp1 = load <32 x i16>, <32 x i16>* %a + %tmp1 = load <32 x i16>, ptr %a %tmp2 = shufflevector <32 x i16> %tmp1, <32 x i16> undef, <32 x i32> - store <32 x i16> %tmp2, <32 x i16>* %a + store <32 x i16> %tmp2, ptr %a ret void } ; Only support to reverse bytes / halfwords / words within elements -define void @test_rev_elts_fail(<4 x i64>* %a) #1 { +define void @test_rev_elts_fail(ptr %a) #1 { ; CHECK-LABEL: test_rev_elts_fail: ; CHECK: // %bb.0: ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill @@ -217,9 +217,9 @@ define void @test_rev_elts_fail(<4 x i64>* %a) #1 { ; CHECK-NEXT: mov sp, x29 ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ret - %tmp1 = load <4 x i64>, <4 x i64>* %a + %tmp1 = load <4 x i64>, ptr %a %tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> undef, <4 x i32> - store <4 x i64> %tmp2, <4 x i64>* %a + store <4 x i64> %tmp2, ptr %a ret void } @@ -228,7 +228,7 @@ define void @test_rev_elts_fail(<4 x i64>* %a) #1 { ; the correctness of generated REV instruction for shuffle pattern cannot be guaranteed. ; sve-vector-bits-min=256, sve-vector-bits-max is not set, REV inst can't be generated. -define void @test_revv8i32(<8 x i32>* %a) #0 { +define void @test_revv8i32(ptr %a) #0 { ; CHECK-LABEL: test_revv8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill @@ -262,14 +262,14 @@ define void @test_revv8i32(<8 x i32>* %a) #0 { ; CHECK-NEXT: mov sp, x29 ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ret - %tmp1 = load <8 x i32>, <8 x i32>* %a + %tmp1 = load <8 x i32>, ptr %a %tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> - store <8 x i32> %tmp2, <8 x i32>* %a + store <8 x i32> %tmp2, ptr %a ret void } ; REV pattern for v32i8 shuffle with vscale_range(2,2) -define void @test_revv32i8_vl256(<32 x i8>* %a) #1 { +define void @test_revv32i8_vl256(ptr %a) #1 { ; CHECK-LABEL: test_revv32i8_vl256: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b @@ -277,14 +277,14 @@ define void @test_revv32i8_vl256(<32 x i8>* %a) #1 { ; CHECK-NEXT: rev z0.b, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <32 x i8>, <32 x i8>* %a + %tmp1 = load <32 x i8>, ptr %a %tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> - store <32 x i8> %tmp2, <32 x i8>* %a + store <32 x i8> %tmp2, ptr %a ret void } ; REV pattern for v16i16 shuffle with vscale_range(2,2) -define void @test_revv16i16_vl256(<16 x i16>* %a) #1 { +define void @test_revv16i16_vl256(ptr %a) #1 { ; CHECK-LABEL: test_revv16i16_vl256: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h @@ -292,14 +292,14 @@ define void @test_revv16i16_vl256(<16 x i16>* %a) #1 { ; CHECK-NEXT: rev z0.h, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <16 x i16>, <16 x i16>* %a + %tmp1 = load <16 x i16>, ptr %a %tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <16 x i32> - store <16 x i16> %tmp2, <16 x i16>* %a + store <16 x i16> %tmp2, ptr %a ret void } ; REV pattern for v8f32 shuffle with vscale_range(2,2) -define void @test_revv8f32_vl256(<8 x float>* %a) #1 { +define void @test_revv8f32_vl256(ptr %a) #1 { ; CHECK-LABEL: test_revv8f32_vl256: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s @@ -307,14 +307,14 @@ define void @test_revv8f32_vl256(<8 x float>* %a) #1 { ; CHECK-NEXT: rev z0.s, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <8 x float>, <8 x float>* %a + %tmp1 = load <8 x float>, ptr %a %tmp2 = shufflevector <8 x float> %tmp1, <8 x float> undef, <8 x i32> - store <8 x float> %tmp2, <8 x float>* %a + store <8 x float> %tmp2, ptr %a ret void } ; REV pattern for v4f64 shuffle with vscale_range(2,2) -define void @test_revv4f64_vl256(<4 x double>* %a) #1 { +define void @test_revv4f64_vl256(ptr %a) #1 { ; CHECK-LABEL: test_revv4f64_vl256: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d @@ -322,14 +322,14 @@ define void @test_revv4f64_vl256(<4 x double>* %a) #1 { ; CHECK-NEXT: rev z0.d, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <4 x double>, <4 x double>* %a + %tmp1 = load <4 x double>, ptr %a %tmp2 = shufflevector <4 x double> %tmp1, <4 x double> undef, <4 x i32> - store <4 x double> %tmp2, <4 x double>* %a + store <4 x double> %tmp2, ptr %a ret void } ; REV pattern for shuffle two v8i32 inputs with the second input available, vscale_range(2,2). -define void @test_revv8i32v8i32(<8 x i32>* %a, <8 x i32>* %b) #1 { +define void @test_revv8i32v8i32(ptr %a, ptr %b) #1 { ; CHECK-LABEL: test_revv8i32v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s @@ -337,15 +337,15 @@ define void @test_revv8i32v8i32(<8 x i32>* %a, <8 x i32>* %b) #1 { ; CHECK-NEXT: rev z0.s, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <8 x i32>, <8 x i32>* %a - %tmp2 = load <8 x i32>, <8 x i32>* %b + %tmp1 = load <8 x i32>, ptr %a + %tmp2 = load <8 x i32>, ptr %b %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> %tmp2, <8 x i32> - store <8 x i32> %tmp3, <8 x i32>* %a + store <8 x i32> %tmp3, ptr %a ret void } ; Illegal REV pattern. -define void @test_rev_fail(<16 x i16>* %a) #1 { +define void @test_rev_fail(ptr %a) #1 { ; CHECK-LABEL: test_rev_fail: ; CHECK: // %bb.0: ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill @@ -403,14 +403,14 @@ define void @test_rev_fail(<16 x i16>* %a) #1 { ; CHECK-NEXT: mov sp, x29 ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ret - %tmp1 = load <16 x i16>, <16 x i16>* %a + %tmp1 = load <16 x i16>, ptr %a %tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <16 x i32> - store <16 x i16> %tmp2, <16 x i16>* %a + store <16 x i16> %tmp2, ptr %a ret void } ; Don't use SVE for 128-bit shuffle with two inputs -define void @test_revv8i16v8i16(<8 x i16>* %a, <8 x i16>* %b, <16 x i16>* %c) #1 { +define void @test_revv8i16v8i16(ptr %a, ptr %b, ptr %c) #1 { ; CHECK-LABEL: test_revv8i16v8i16: ; CHECK: // %bb.0: ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill @@ -463,10 +463,10 @@ define void @test_revv8i16v8i16(<8 x i16>* %a, <8 x i16>* %b, <16 x i16>* %c) #1 ; CHECK-NEXT: mov sp, x29 ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ret - %tmp1 = load <8 x i16>, <8 x i16>* %a - %tmp2 = load <8 x i16>, <8 x i16>* %b + %tmp1 = load <8 x i16>, ptr %a + %tmp2 = load <8 x i16>, ptr %b %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> - store <16 x i16> %tmp3, <16 x i16>* %c + store <16 x i16> %tmp3, ptr %c ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll index e497ad2..0946b77 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll @@ -4,7 +4,7 @@ target triple = "aarch64-unknown-linux-gnu" -define void @zip1_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 { +define void @zip1_v32i8(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: zip1_v32i8: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: ptrue p0.b @@ -22,14 +22,14 @@ define void @zip1_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 { ; VBITS_EQ_512-NEXT: zip1 z0.b, z0.b, z1.b ; VBITS_EQ_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_EQ_512-NEXT: ret - %tmp1 = load volatile <32 x i8>, <32 x i8>* %a - %tmp2 = load volatile <32 x i8>, <32 x i8>* %b + %tmp1 = load volatile <32 x i8>, ptr %a + %tmp2 = load volatile <32 x i8>, ptr %b %tmp3 = shufflevector <32 x i8> %tmp1, <32 x i8> %tmp2, <32 x i32> - store volatile <32 x i8> %tmp3, <32 x i8>* %a + store volatile <32 x i8> %tmp3, ptr %a ret void } -define void @zip_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @zip_v32i16(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: zip_v32i16: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: mov x8, #16 @@ -58,16 +58,16 @@ define void @zip_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_EQ_512-NEXT: add z0.h, z2.h, z0.h ; VBITS_EQ_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_EQ_512-NEXT: ret - %tmp1 = load <32 x i16>, <32 x i16>* %a - %tmp2 = load <32 x i16>, <32 x i16>* %b + %tmp1 = load <32 x i16>, ptr %a + %tmp2 = load <32 x i16>, ptr %b %tmp3 = shufflevector <32 x i16> %tmp1, <32 x i16> %tmp2, <32 x i32> %tmp4 = shufflevector <32 x i16> %tmp1, <32 x i16> %tmp2, <32 x i32> %tmp5 = add <32 x i16> %tmp3, %tmp4 - store <32 x i16> %tmp5, <32 x i16>* %a + store <32 x i16> %tmp5, ptr %a ret void } -define void @zip1_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { +define void @zip1_v16i16(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: zip1_v16i16: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: ptrue p0.h @@ -85,14 +85,14 @@ define void @zip1_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { ; VBITS_EQ_512-NEXT: zip1 z0.h, z0.h, z1.h ; VBITS_EQ_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_EQ_512-NEXT: ret - %tmp1 = load volatile <16 x i16>, <16 x i16>* %a - %tmp2 = load volatile <16 x i16>, <16 x i16>* %b + %tmp1 = load volatile <16 x i16>, ptr %a + %tmp2 = load volatile <16 x i16>, ptr %b %tmp3 = shufflevector <16 x i16> %tmp1, <16 x i16> %tmp2, <16 x i32> - store volatile <16 x i16> %tmp3, <16 x i16>* %a + store volatile <16 x i16> %tmp3, ptr %a ret void } -define void @zip1_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 { +define void @zip1_v8i32(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: zip1_v8i32: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: ptrue p0.s @@ -110,14 +110,14 @@ define void @zip1_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 { ; VBITS_EQ_512-NEXT: zip1 z0.s, z0.s, z1.s ; VBITS_EQ_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_EQ_512-NEXT: ret - %tmp1 = load volatile <8 x i32>, <8 x i32>* %a - %tmp2 = load volatile <8 x i32>, <8 x i32>* %b + %tmp1 = load volatile <8 x i32>, ptr %a + %tmp2 = load volatile <8 x i32>, ptr %b %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> %tmp2, <8 x i32> - store volatile <8 x i32> %tmp3, <8 x i32>* %a + store volatile <8 x i32> %tmp3, ptr %a ret void } -define void @zip_v4f64(<4 x double>* %a, <4 x double>* %b) #0 { +define void @zip_v4f64(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: zip_v4f64: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: ptrue p0.d @@ -155,17 +155,17 @@ define void @zip_v4f64(<4 x double>* %a, <4 x double>* %b) #0 { ; VBITS_EQ_512-NEXT: mov sp, x29 ; VBITS_EQ_512-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; VBITS_EQ_512-NEXT: ret - %tmp1 = load <4 x double>, <4 x double>* %a - %tmp2 = load <4 x double>, <4 x double>* %b + %tmp1 = load <4 x double>, ptr %a + %tmp2 = load <4 x double>, ptr %b %tmp3 = shufflevector <4 x double> %tmp1, <4 x double> %tmp2, <4 x i32> %tmp4 = shufflevector <4 x double> %tmp1, <4 x double> %tmp2, <4 x i32> %tmp5 = fadd <4 x double> %tmp3, %tmp4 - store <4 x double> %tmp5, <4 x double>* %a + store <4 x double> %tmp5, ptr %a ret void } ; Don't use SVE for 128-bit vectors -define void @zip_v4i32(<4 x i32>* %a, <4 x i32>* %b) #0 { +define void @zip_v4i32(ptr %a, ptr %b) #0 { ; CHECK-LABEL: zip_v4i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -175,16 +175,16 @@ define void @zip_v4i32(<4 x i32>* %a, <4 x i32>* %b) #0 { ; CHECK-NEXT: add v0.4s, v2.4s, v0.4s ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <4 x i32>, <4 x i32>* %a - %tmp2 = load <4 x i32>, <4 x i32>* %b + %tmp1 = load <4 x i32>, ptr %a + %tmp2 = load <4 x i32>, ptr %b %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> %tmp5 = add <4 x i32> %tmp3, %tmp4 - store <4 x i32> %tmp5, <4 x i32>* %a + store <4 x i32> %tmp5, ptr %a ret void } -define void @zip1_v8i32_undef(<8 x i32>* %a) #0 { +define void @zip1_v8i32_undef(ptr %a) #0 { ; VBITS_EQ_256-LABEL: zip1_v8i32_undef: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: ptrue p0.s @@ -200,13 +200,13 @@ define void @zip1_v8i32_undef(<8 x i32>* %a) #0 { ; VBITS_EQ_512-NEXT: zip1 z0.s, z0.s, z0.s ; VBITS_EQ_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_EQ_512-NEXT: ret - %tmp1 = load volatile <8 x i32>, <8 x i32>* %a + %tmp1 = load volatile <8 x i32>, ptr %a %tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> - store volatile <8 x i32> %tmp2, <8 x i32>* %a + store volatile <8 x i32> %tmp2, ptr %a ret void } -define void @trn_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 { +define void @trn_v32i8(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: trn_v32i8: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: ptrue p0.b @@ -228,16 +228,16 @@ define void @trn_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 { ; VBITS_EQ_512-NEXT: add z0.b, z2.b, z0.b ; VBITS_EQ_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_EQ_512-NEXT: ret - %tmp1 = load <32 x i8>, <32 x i8>* %a - %tmp2 = load <32 x i8>, <32 x i8>* %b + %tmp1 = load <32 x i8>, ptr %a + %tmp2 = load <32 x i8>, ptr %b %tmp3 = shufflevector <32 x i8> %tmp1, <32 x i8> %tmp2, <32 x i32> %tmp4 = shufflevector <32 x i8> %tmp1, <32 x i8> %tmp2, <32 x i32> %tmp5 = add <32 x i8> %tmp3, %tmp4 - store <32 x i8> %tmp5, <32 x i8>* %a + store <32 x i8> %tmp5, ptr %a ret void } -define void @trn_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @trn_v32i16(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: trn_v32i16: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: mov x8, #16 @@ -266,16 +266,16 @@ define void @trn_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_EQ_512-NEXT: add z0.h, z2.h, z0.h ; VBITS_EQ_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_EQ_512-NEXT: ret - %tmp1 = load <32 x i16>, <32 x i16>* %a - %tmp2 = load <32 x i16>, <32 x i16>* %b + %tmp1 = load <32 x i16>, ptr %a + %tmp2 = load <32 x i16>, ptr %b %tmp3 = shufflevector <32 x i16> %tmp1, <32 x i16> %tmp2, <32 x i32> %tmp4 = shufflevector <32 x i16> %tmp1, <32 x i16> %tmp2, <32 x i32> %tmp5 = add <32 x i16> %tmp3, %tmp4 - store <32 x i16> %tmp5, <32 x i16>* %a + store <32 x i16> %tmp5, ptr %a ret void } -define void @trn_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { +define void @trn_v16i16(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: trn_v16i16: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: ptrue p0.h @@ -297,16 +297,16 @@ define void @trn_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { ; VBITS_EQ_512-NEXT: add z0.h, z2.h, z0.h ; VBITS_EQ_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_EQ_512-NEXT: ret - %tmp1 = load <16 x i16>, <16 x i16>* %a - %tmp2 = load <16 x i16>, <16 x i16>* %b + %tmp1 = load <16 x i16>, ptr %a + %tmp2 = load <16 x i16>, ptr %b %tmp3 = shufflevector <16 x i16> %tmp1, <16 x i16> %tmp2, <16 x i32> %tmp4 = shufflevector <16 x i16> %tmp1, <16 x i16> %tmp2, <16 x i32> %tmp5 = add <16 x i16> %tmp3, %tmp4 - store <16 x i16> %tmp5, <16 x i16>* %a + store <16 x i16> %tmp5, ptr %a ret void } -define void @trn_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 { +define void @trn_v8i32(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: trn_v8i32: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: ptrue p0.s @@ -328,16 +328,16 @@ define void @trn_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 { ; VBITS_EQ_512-NEXT: add z0.s, z2.s, z0.s ; VBITS_EQ_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_EQ_512-NEXT: ret - %tmp1 = load <8 x i32>, <8 x i32>* %a - %tmp2 = load <8 x i32>, <8 x i32>* %b + %tmp1 = load <8 x i32>, ptr %a + %tmp2 = load <8 x i32>, ptr %b %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> %tmp2, <8 x i32> %tmp4 = shufflevector <8 x i32> %tmp1, <8 x i32> %tmp2, <8 x i32> %tmp5 = add <8 x i32> %tmp3, %tmp4 - store <8 x i32> %tmp5, <8 x i32>* %a + store <8 x i32> %tmp5, ptr %a ret void } -define void @trn_v4f64(<4 x double>* %a, <4 x double>* %b) #0 { +define void @trn_v4f64(ptr %a, ptr %b) #0 { ; VBITS_EQ_256-LABEL: trn_v4f64: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: ptrue p0.d @@ -359,17 +359,17 @@ define void @trn_v4f64(<4 x double>* %a, <4 x double>* %b) #0 { ; VBITS_EQ_512-NEXT: fadd z0.d, p0/m, z0.d, z2.d ; VBITS_EQ_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_EQ_512-NEXT: ret - %tmp1 = load <4 x double>, <4 x double>* %a - %tmp2 = load <4 x double>, <4 x double>* %b + %tmp1 = load <4 x double>, ptr %a + %tmp2 = load <4 x double>, ptr %b %tmp3 = shufflevector <4 x double> %tmp1, <4 x double> %tmp2, <4 x i32> %tmp4 = shufflevector <4 x double> %tmp1, <4 x double> %tmp2, <4 x i32> %tmp5 = fadd <4 x double> %tmp3, %tmp4 - store <4 x double> %tmp5, <4 x double>* %a + store <4 x double> %tmp5, ptr %a ret void } ; Don't use SVE for 128-bit vectors -define void @trn_v4f32(<4 x float>* %a, <4 x float>* %b) #0 { +define void @trn_v4f32(ptr %a, ptr %b) #0 { ; CHECK-LABEL: trn_v4f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -379,16 +379,16 @@ define void @trn_v4f32(<4 x float>* %a, <4 x float>* %b) #0 { ; CHECK-NEXT: fadd v0.4s, v2.4s, v0.4s ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <4 x float>, <4 x float>* %a - %tmp2 = load <4 x float>, <4 x float>* %b + %tmp1 = load <4 x float>, ptr %a + %tmp2 = load <4 x float>, ptr %b %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> %tmp5 = fadd <4 x float> %tmp3, %tmp4 - store <4 x float> %tmp5, <4 x float>* %a + store <4 x float> %tmp5, ptr %a ret void } -define void @trn_v8i32_undef(<8 x i32>* %a) #0 { +define void @trn_v8i32_undef(ptr %a) #0 { ; VBITS_EQ_256-LABEL: trn_v8i32_undef: ; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256-NEXT: ptrue p0.s @@ -408,17 +408,17 @@ define void @trn_v8i32_undef(<8 x i32>* %a) #0 { ; VBITS_EQ_512-NEXT: add z0.s, z1.s, z0.s ; VBITS_EQ_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_EQ_512-NEXT: ret - %tmp1 = load <8 x i32>, <8 x i32>* %a + %tmp1 = load <8 x i32>, ptr %a %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> %tmp4 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> %tmp5 = add <8 x i32> %tmp3, %tmp4 - store <8 x i32> %tmp5, <8 x i32>* %a + store <8 x i32> %tmp5, ptr %a ret void } ; Emit zip2 instruction for v32i8 shuffle with vscale_range(2,2), ; since the size of v32i8 is the same as the runtime vector length. -define void @zip2_v32i8(<32 x i8>* %a, <32 x i8>* %b) #1 { +define void @zip2_v32i8(ptr %a, ptr %b) #1 { ; CHECK-LABEL: zip2_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b @@ -427,16 +427,16 @@ define void @zip2_v32i8(<32 x i8>* %a, <32 x i8>* %b) #1 { ; CHECK-NEXT: zip2 z0.b, z0.b, z1.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load volatile <32 x i8>, <32 x i8>* %a - %tmp2 = load volatile <32 x i8>, <32 x i8>* %b + %tmp1 = load volatile <32 x i8>, ptr %a + %tmp2 = load volatile <32 x i8>, ptr %b %tmp3 = shufflevector <32 x i8> %tmp1, <32 x i8> %tmp2, <32 x i32> - store volatile <32 x i8> %tmp3, <32 x i8>* %a + store volatile <32 x i8> %tmp3, ptr %a ret void } ; Emit zip2 instruction for v16i16 shuffle with vscale_range(2,2), ; since the size of v16i16 is the same as the runtime vector length. -define void @zip2_v16i16(<16 x i16>* %a, <16 x i16>* %b) #1 { +define void @zip2_v16i16(ptr %a, ptr %b) #1 { ; CHECK-LABEL: zip2_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h @@ -445,16 +445,16 @@ define void @zip2_v16i16(<16 x i16>* %a, <16 x i16>* %b) #1 { ; CHECK-NEXT: zip2 z0.h, z0.h, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load volatile <16 x i16>, <16 x i16>* %a - %tmp2 = load volatile <16 x i16>, <16 x i16>* %b + %tmp1 = load volatile <16 x i16>, ptr %a + %tmp2 = load volatile <16 x i16>, ptr %b %tmp3 = shufflevector <16 x i16> %tmp1, <16 x i16> %tmp2, <16 x i32> - store volatile <16 x i16> %tmp3, <16 x i16>* %a + store volatile <16 x i16> %tmp3, ptr %a ret void } ; Emit zip2 instruction for v8i32 shuffle with vscale_range(2,2), ; since the size of v8i32 is the same as the runtime vector length. -define void @zip2_v8i32(<8 x i32>* %a, <8 x i32>* %b) #1 { +define void @zip2_v8i32(ptr %a, ptr %b) #1 { ; CHECK-LABEL: zip2_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s @@ -463,15 +463,15 @@ define void @zip2_v8i32(<8 x i32>* %a, <8 x i32>* %b) #1 { ; CHECK-NEXT: zip2 z0.s, z0.s, z1.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load volatile <8 x i32>, <8 x i32>* %a - %tmp2 = load volatile <8 x i32>, <8 x i32>* %b + %tmp1 = load volatile <8 x i32>, ptr %a + %tmp2 = load volatile <8 x i32>, ptr %b %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> %tmp2, <8 x i32> - store volatile <8 x i32> %tmp3, <8 x i32>* %a + store volatile <8 x i32> %tmp3, ptr %a ret void } ; Emit zip2 instruction for v8i32 and undef shuffle with vscale_range(2,2) -define void @zip2_v8i32_undef(<8 x i32>* %a) #1 { +define void @zip2_v8i32_undef(ptr %a) #1 { ; CHECK-LABEL: zip2_v8i32_undef: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s @@ -479,15 +479,15 @@ define void @zip2_v8i32_undef(<8 x i32>* %a) #1 { ; CHECK-NEXT: zip2 z0.s, z0.s, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load volatile <8 x i32>, <8 x i32>* %a + %tmp1 = load volatile <8 x i32>, ptr %a %tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> - store volatile <8 x i32> %tmp2, <8 x i32>* %a + store volatile <8 x i32> %tmp2, ptr %a ret void } ; Emit uzp1/2 instruction for v32i8 shuffle with vscale_range(2,2), ; since the size of v32i8 is the same as the runtime vector length. -define void @uzp_v32i8(<32 x i8>* %a, <32 x i8>* %b) #1 { +define void @uzp_v32i8(ptr %a, ptr %b) #1 { ; CHECK-LABEL: uzp_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b @@ -498,19 +498,19 @@ define void @uzp_v32i8(<32 x i8>* %a, <32 x i8>* %b) #1 { ; CHECK-NEXT: add z0.b, z2.b, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <32 x i8>, <32 x i8>* %a - %tmp2 = load <32 x i8>, <32 x i8>* %b + %tmp1 = load <32 x i8>, ptr %a + %tmp2 = load <32 x i8>, ptr %b %tmp3 = shufflevector <32 x i8> %tmp1, <32 x i8> %tmp2, <32 x i32> %tmp4 = shufflevector <32 x i8> %tmp1, <32 x i8> %tmp2, <32 x i32> %tmp5 = add <32 x i8> %tmp3, %tmp4 - store <32 x i8> %tmp5, <32 x i8>* %a + store <32 x i8> %tmp5, ptr %a ret void } ; Emit uzp1/2 instruction for v32i16 shuffle with vscale_range(2,2), ; v32i16 will be expanded into two v16i16, and the size of v16i16 is ; the same as the runtime vector length. -define void @uzp_v32i16(<32 x i16>* %a, <32 x i16>* %b) #1 { +define void @uzp_v32i16(ptr %a, ptr %b) #1 { ; CHECK-LABEL: uzp_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: mov x8, #16 @@ -528,18 +528,18 @@ define void @uzp_v32i16(<32 x i16>* %a, <32 x i16>* %b) #1 { ; CHECK-NEXT: st1h { z1.h }, p0, [x0, x8, lsl #1] ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <32 x i16>, <32 x i16>* %a - %tmp2 = load <32 x i16>, <32 x i16>* %b + %tmp1 = load <32 x i16>, ptr %a + %tmp2 = load <32 x i16>, ptr %b %tmp3 = shufflevector <32 x i16> %tmp1, <32 x i16> %tmp2, <32 x i32> %tmp4 = shufflevector <32 x i16> %tmp1, <32 x i16> %tmp2, <32 x i32> %tmp5 = add <32 x i16> %tmp3, %tmp4 - store <32 x i16> %tmp5, <32 x i16>* %a + store <32 x i16> %tmp5, ptr %a ret void } ; Emit uzp1/2 instruction for v16i16 shuffle with vscale_range(2,2), ; since the size of v16i16 is the same as the runtime vector length. -define void @uzp_v16i16(<16 x i16>* %a, <16 x i16>* %b) #1 { +define void @uzp_v16i16(ptr %a, ptr %b) #1 { ; CHECK-LABEL: uzp_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h @@ -550,18 +550,18 @@ define void @uzp_v16i16(<16 x i16>* %a, <16 x i16>* %b) #1 { ; CHECK-NEXT: add z0.h, z2.h, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <16 x i16>, <16 x i16>* %a - %tmp2 = load <16 x i16>, <16 x i16>* %b + %tmp1 = load <16 x i16>, ptr %a + %tmp2 = load <16 x i16>, ptr %b %tmp3 = shufflevector <16 x i16> %tmp1, <16 x i16> %tmp2, <16 x i32> %tmp4 = shufflevector <16 x i16> %tmp1, <16 x i16> %tmp2, <16 x i32> %tmp5 = add <16 x i16> %tmp3, %tmp4 - store <16 x i16> %tmp5, <16 x i16>* %a + store <16 x i16> %tmp5, ptr %a ret void } ; Emit uzp1/2 instruction for v8f32 shuffle with vscale_range(2,2), ; since the size of v8f32 is the same as the runtime vector length. -define void @uzp_v8f32(<8 x float>* %a, <8 x float>* %b) #1 { +define void @uzp_v8f32(ptr %a, ptr %b) #1 { ; CHECK-LABEL: uzp_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s @@ -572,18 +572,18 @@ define void @uzp_v8f32(<8 x float>* %a, <8 x float>* %b) #1 { ; CHECK-NEXT: fadd z0.s, z2.s, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <8 x float>, <8 x float>* %a - %tmp2 = load <8 x float>, <8 x float>* %b + %tmp1 = load <8 x float>, ptr %a + %tmp2 = load <8 x float>, ptr %b %tmp3 = shufflevector <8 x float> %tmp1, <8 x float> %tmp2, <8 x i32> %tmp4 = shufflevector <8 x float> %tmp1, <8 x float> %tmp2, <8 x i32> %tmp5 = fadd <8 x float> %tmp3, %tmp4 - store <8 x float> %tmp5, <8 x float>* %a + store <8 x float> %tmp5, ptr %a ret void } ; Emit uzp1/2 instruction for v4i64 shuffle with vscale_range(2,2), ; since the size of v4i64 is the same as the runtime vector length. -define void @uzp_v4i64(<4 x i64>* %a, <4 x i64>* %b) #1 { +define void @uzp_v4i64(ptr %a, ptr %b) #1 { ; CHECK-LABEL: uzp_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d @@ -594,17 +594,17 @@ define void @uzp_v4i64(<4 x i64>* %a, <4 x i64>* %b) #1 { ; CHECK-NEXT: add z0.d, z2.d, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <4 x i64>, <4 x i64>* %a - %tmp2 = load <4 x i64>, <4 x i64>* %b + %tmp1 = load <4 x i64>, ptr %a + %tmp2 = load <4 x i64>, ptr %b %tmp3 = shufflevector <4 x i64> %tmp1, <4 x i64> %tmp2, <4 x i32> %tmp4 = shufflevector <4 x i64> %tmp1, <4 x i64> %tmp2, <4 x i32> %tmp5 = add <4 x i64> %tmp3, %tmp4 - store <4 x i64> %tmp5, <4 x i64>* %a + store <4 x i64> %tmp5, ptr %a ret void } ; Don't use SVE for 128-bit vectors -define void @uzp_v8i16(<8 x i16>* %a, <8 x i16>* %b) #1 { +define void @uzp_v8i16(ptr %a, ptr %b) #1 { ; CHECK-LABEL: uzp_v8i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -614,17 +614,17 @@ define void @uzp_v8i16(<8 x i16>* %a, <8 x i16>* %b) #1 { ; CHECK-NEXT: add v0.8h, v2.8h, v0.8h ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <8 x i16>, <8 x i16>* %a - %tmp2 = load <8 x i16>, <8 x i16>* %b + %tmp1 = load <8 x i16>, ptr %a + %tmp2 = load <8 x i16>, ptr %b %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> %tmp5 = add <8 x i16> %tmp3, %tmp4 - store <8 x i16> %tmp5, <8 x i16>* %a + store <8 x i16> %tmp5, ptr %a ret void } ; Emit uzp1/2 instruction for v8i32 and undef shuffle with vscale_range(2,2) -define void @uzp_v8i32_undef(<8 x i32>* %a) #1 { +define void @uzp_v8i32_undef(ptr %a) #1 { ; CHECK-LABEL: uzp_v8i32_undef: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s @@ -634,18 +634,18 @@ define void @uzp_v8i32_undef(<8 x i32>* %a) #1 { ; CHECK-NEXT: add z0.s, z1.s, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <8 x i32>, <8 x i32>* %a + %tmp1 = load <8 x i32>, ptr %a %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> %tmp4 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> %tmp5 = add <8 x i32> %tmp3, %tmp4 - store <8 x i32> %tmp5, <8 x i32>* %a + store <8 x i32> %tmp5, ptr %a ret void } ; Only zip1 can be emitted safely with vscale_range(2,4). ; vscale_range(2,4) means different min/max vector sizes, zip2 relies on ; knowing which indices represent the high half of sve vector register. -define void @zip_vscale2_4(<4 x double>* %a, <4 x double>* %b) #2 { +define void @zip_vscale2_4(ptr %a, ptr %b) #2 { ; CHECK-LABEL: zip_vscale2_4: ; CHECK: // %bb.0: ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill @@ -672,12 +672,12 @@ define void @zip_vscale2_4(<4 x double>* %a, <4 x double>* %b) #2 { ; CHECK-NEXT: mov sp, x29 ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ret - %tmp1 = load <4 x double>, <4 x double>* %a - %tmp2 = load <4 x double>, <4 x double>* %b + %tmp1 = load <4 x double>, ptr %a + %tmp2 = load <4 x double>, ptr %b %tmp3 = shufflevector <4 x double> %tmp1, <4 x double> %tmp2, <4 x i32> %tmp4 = shufflevector <4 x double> %tmp1, <4 x double> %tmp2, <4 x i32> %tmp5 = fadd <4 x double> %tmp3, %tmp4 - store <4 x double> %tmp5, <4 x double>* %a + store <4 x double> %tmp5, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-ptest.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-ptest.ll index a19a512..614d4ff 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-ptest.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-ptest.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s -define i1 @ptest_v16i1_256bit_min_sve(float* %a, float * %b) vscale_range(2, 0) { +define i1 @ptest_v16i1_256bit_min_sve(ptr %a, ptr %b) vscale_range(2, 0) { ; CHECK-LABEL: ptest_v16i1_256bit_min_sve: ; CHECK: // %bb.0: ; CHECK-NEXT: mov x8, #8 @@ -22,14 +22,13 @@ define i1 @ptest_v16i1_256bit_min_sve(float* %a, float * %b) vscale_range(2, 0) ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: ret - %v0 = bitcast float* %a to <16 x float>* - %v1 = load <16 x float>, <16 x float>* %v0, align 4 + %v1 = load <16 x float>, ptr %a, align 4 %v2 = fcmp une <16 x float> %v1, zeroinitializer %v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2) ret i1 %v3 } -define i1 @ptest_v16i1_512bit_min_sve(float* %a, float * %b) vscale_range(4, 0) { +define i1 @ptest_v16i1_512bit_min_sve(ptr %a, ptr %b) vscale_range(4, 0) { ; CHECK-LABEL: ptest_v16i1_512bit_min_sve: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -43,14 +42,13 @@ define i1 @ptest_v16i1_512bit_min_sve(float* %a, float * %b) vscale_range(4, 0) ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: ret - %v0 = bitcast float* %a to <16 x float>* - %v1 = load <16 x float>, <16 x float>* %v0, align 4 + %v1 = load <16 x float>, ptr %a, align 4 %v2 = fcmp une <16 x float> %v1, zeroinitializer %v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2) ret i1 %v3 } -define i1 @ptest_v16i1_512bit_sve(float* %a, float * %b) vscale_range(4, 4) { +define i1 @ptest_v16i1_512bit_sve(ptr %a, ptr %b) vscale_range(4, 4) { ; CHECK-LABEL: ptest_v16i1_512bit_sve: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s @@ -64,14 +62,13 @@ define i1 @ptest_v16i1_512bit_sve(float* %a, float * %b) vscale_range(4, 4) { ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: ret - %v0 = bitcast float* %a to <16 x float>* - %v1 = load <16 x float>, <16 x float>* %v0, align 4 + %v1 = load <16 x float>, ptr %a, align 4 %v2 = fcmp une <16 x float> %v1, zeroinitializer %v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2) ret i1 %v3 } -define i1 @ptest_or_v16i1_512bit_min_sve(float* %a, float * %b) vscale_range(4, 0) { +define i1 @ptest_or_v16i1_512bit_min_sve(ptr %a, ptr %b) vscale_range(4, 0) { ; CHECK-LABEL: ptest_or_v16i1_512bit_min_sve: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -88,11 +85,9 @@ define i1 @ptest_or_v16i1_512bit_min_sve(float* %a, float * %b) vscale_range(4, ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: ret - %v0 = bitcast float* %a to <16 x float>* - %v1 = load <16 x float>, <16 x float>* %v0, align 4 + %v1 = load <16 x float>, ptr %a, align 4 %v2 = fcmp une <16 x float> %v1, zeroinitializer - %v3 = bitcast float* %b to <16 x float>* - %v4 = load <16 x float>, <16 x float>* %v3, align 4 + %v4 = load <16 x float>, ptr %b, align 4 %v5 = fcmp une <16 x float> %v4, zeroinitializer %v6 = or <16 x i1> %v2, %v5 %v7 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v6) @@ -105,7 +100,7 @@ declare i1 @llvm.vector.reduce.or.i1.v16i1(<16 x i1>) ; AND reduction. ; -define i1 @ptest_and_v16i1_512bit_sve(float* %a, float * %b) vscale_range(4, 4) { +define i1 @ptest_and_v16i1_512bit_sve(ptr %a, ptr %b) vscale_range(4, 4) { ; CHECK-LABEL: ptest_and_v16i1_512bit_sve: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s @@ -121,18 +116,16 @@ define i1 @ptest_and_v16i1_512bit_sve(float* %a, float * %b) vscale_range(4, 4) ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: ret - %v0 = bitcast float* %a to <16 x float>* - %v1 = load <16 x float>, <16 x float>* %v0, align 4 + %v1 = load <16 x float>, ptr %a, align 4 %v2 = fcmp une <16 x float> %v1, zeroinitializer - %v3 = bitcast float* %b to <16 x float>* - %v4 = load <16 x float>, <16 x float>* %v3, align 4 + %v4 = load <16 x float>, ptr %b, align 4 %v5 = fcmp une <16 x float> %v4, zeroinitializer %v6 = and <16 x i1> %v2, %v5 %v7 = call i1 @llvm.vector.reduce.and.i1.v16i1 (<16 x i1> %v6) ret i1 %v7 } -define i1 @ptest_and_v16i1_512bit_min_sve(float* %a, float * %b) vscale_range(4, 0) { +define i1 @ptest_and_v16i1_512bit_min_sve(ptr %a, ptr %b) vscale_range(4, 0) { ; CHECK-LABEL: ptest_and_v16i1_512bit_min_sve: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl16 @@ -149,11 +142,9 @@ define i1 @ptest_and_v16i1_512bit_min_sve(float* %a, float * %b) vscale_range(4, ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: ret - %v0 = bitcast float* %a to <16 x float>* - %v1 = load <16 x float>, <16 x float>* %v0, align 4 + %v1 = load <16 x float>, ptr %a, align 4 %v2 = fcmp une <16 x float> %v1, zeroinitializer - %v3 = bitcast float* %b to <16 x float>* - %v4 = load <16 x float>, <16 x float>* %v3, align 4 + %v4 = load <16 x float>, ptr %b, align 4 %v5 = fcmp une <16 x float> %v4, zeroinitializer %v6 = and <16 x i1> %v2, %v5 %v7 = call i1 @llvm.vector.reduce.and.i1.v16i1 (<16 x i1> %v6) diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll index 24d2095..020f458 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll @@ -33,7 +33,7 @@ define <16 x i8> @bitreverse_v16i8(<16 x i8> %op) vscale_range(2,0) #0 { ret <16 x i8> %res } -define void @bitreverse_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { +define void @bitreverse_v32i8(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: bitreverse_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -41,13 +41,13 @@ define void @bitreverse_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: rbit z0.b, p0/m, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x i8>, <32 x i8>* %a + %op = load <32 x i8>, ptr %a %res = call <32 x i8> @llvm.bitreverse.v32i8(<32 x i8> %op) - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @bitreverse_v64i8(<64 x i8>* %a) #0 { +define void @bitreverse_v64i8(ptr %a) #0 { ; VBITS_GE_256-LABEL: bitreverse_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -67,13 +67,13 @@ define void @bitreverse_v64i8(<64 x i8>* %a) #0 { ; VBITS_GE_512-NEXT: rbit z0.b, p0/m, z0.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <64 x i8>, <64 x i8>* %a + %op = load <64 x i8>, ptr %a %res = call <64 x i8> @llvm.bitreverse.v64i8(<64 x i8> %op) - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @bitreverse_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { +define void @bitreverse_v128i8(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: bitreverse_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -81,13 +81,13 @@ define void @bitreverse_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: rbit z0.b, p0/m, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x i8>, <128 x i8>* %a + %op = load <128 x i8>, ptr %a %res = call <128 x i8> @llvm.bitreverse.v128i8(<128 x i8> %op) - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @bitreverse_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { +define void @bitreverse_v256i8(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: bitreverse_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -95,9 +95,9 @@ define void @bitreverse_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: rbit z0.b, p0/m, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op = load <256 x i8>, <256 x i8>* %a + %op = load <256 x i8>, ptr %a %res = call <256 x i8> @llvm.bitreverse.v256i8(<256 x i8> %op) - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -125,7 +125,7 @@ define <8 x i16> @bitreverse_v8i16(<8 x i16> %op) vscale_range(2,0) #0 { ret <8 x i16> %res } -define void @bitreverse_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { +define void @bitreverse_v16i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: bitreverse_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -133,13 +133,13 @@ define void @bitreverse_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: rbit z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x i16>, <16 x i16>* %a + %op = load <16 x i16>, ptr %a %res = call <16 x i16> @llvm.bitreverse.v16i16(<16 x i16> %op) - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @bitreverse_v32i16(<32 x i16>* %a) #0 { +define void @bitreverse_v32i16(ptr %a) #0 { ; VBITS_GE_256-LABEL: bitreverse_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -159,13 +159,13 @@ define void @bitreverse_v32i16(<32 x i16>* %a) #0 { ; VBITS_GE_512-NEXT: rbit z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <32 x i16>, <32 x i16>* %a + %op = load <32 x i16>, ptr %a %res = call <32 x i16> @llvm.bitreverse.v32i16(<32 x i16> %op) - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @bitreverse_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { +define void @bitreverse_v64i16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: bitreverse_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -173,13 +173,13 @@ define void @bitreverse_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: rbit z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x i16>, <64 x i16>* %a + %op = load <64 x i16>, ptr %a %res = call <64 x i16> @llvm.bitreverse.v64i16(<64 x i16> %op) - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @bitreverse_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { +define void @bitreverse_v128i16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: bitreverse_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -187,9 +187,9 @@ define void @bitreverse_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: rbit z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x i16>, <128 x i16>* %a + %op = load <128 x i16>, ptr %a %res = call <128 x i16> @llvm.bitreverse.v128i16(<128 x i16> %op) - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -217,7 +217,7 @@ define <4 x i32> @bitreverse_v4i32(<4 x i32> %op) vscale_range(2,0) #0 { ret <4 x i32> %res } -define void @bitreverse_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { +define void @bitreverse_v8i32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: bitreverse_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -225,13 +225,13 @@ define void @bitreverse_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: rbit z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <8 x i32>, <8 x i32>* %a + %op = load <8 x i32>, ptr %a %res = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %op) - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @bitreverse_v16i32(<16 x i32>* %a) #0 { +define void @bitreverse_v16i32(ptr %a) #0 { ; VBITS_GE_256-LABEL: bitreverse_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -251,13 +251,13 @@ define void @bitreverse_v16i32(<16 x i32>* %a) #0 { ; VBITS_GE_512-NEXT: rbit z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <16 x i32>, <16 x i32>* %a + %op = load <16 x i32>, ptr %a %res = call <16 x i32> @llvm.bitreverse.v16i32(<16 x i32> %op) - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @bitreverse_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { +define void @bitreverse_v32i32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: bitreverse_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -265,13 +265,13 @@ define void @bitreverse_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: rbit z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x i32>, <32 x i32>* %a + %op = load <32 x i32>, ptr %a %res = call <32 x i32> @llvm.bitreverse.v32i32(<32 x i32> %op) - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @bitreverse_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { +define void @bitreverse_v64i32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: bitreverse_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -279,9 +279,9 @@ define void @bitreverse_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: rbit z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x i32>, <64 x i32>* %a + %op = load <64 x i32>, ptr %a %res = call <64 x i32> @llvm.bitreverse.v64i32(<64 x i32> %op) - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -309,7 +309,7 @@ define <2 x i64> @bitreverse_v2i64(<2 x i64> %op) vscale_range(2,0) #0 { ret <2 x i64> %res } -define void @bitreverse_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { +define void @bitreverse_v4i64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: bitreverse_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -317,13 +317,13 @@ define void @bitreverse_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: rbit z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <4 x i64>, <4 x i64>* %a + %op = load <4 x i64>, ptr %a %res = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> %op) - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @bitreverse_v8i64(<8 x i64>* %a) #0 { +define void @bitreverse_v8i64(ptr %a) #0 { ; VBITS_GE_256-LABEL: bitreverse_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -343,13 +343,13 @@ define void @bitreverse_v8i64(<8 x i64>* %a) #0 { ; VBITS_GE_512-NEXT: rbit z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <8 x i64>, <8 x i64>* %a + %op = load <8 x i64>, ptr %a %res = call <8 x i64> @llvm.bitreverse.v8i64(<8 x i64> %op) - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @bitreverse_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { +define void @bitreverse_v16i64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: bitreverse_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -357,13 +357,13 @@ define void @bitreverse_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: rbit z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x i64>, <16 x i64>* %a + %op = load <16 x i64>, ptr %a %res = call <16 x i64> @llvm.bitreverse.v16i64(<16 x i64> %op) - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @bitreverse_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { +define void @bitreverse_v32i64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: bitreverse_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -371,9 +371,9 @@ define void @bitreverse_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: rbit z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x i64>, <32 x i64>* %a + %op = load <32 x i64>, ptr %a %res = call <32 x i64> @llvm.bitreverse.v32i64(<32 x i64> %op) - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } @@ -401,7 +401,7 @@ define <8 x i16> @bswap_v8i16(<8 x i16> %op) vscale_range(2,0) #0 { ret <8 x i16> %res } -define void @bswap_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { +define void @bswap_v16i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: bswap_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -409,13 +409,13 @@ define void @bswap_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: revb z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x i16>, <16 x i16>* %a + %op = load <16 x i16>, ptr %a %res = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %op) - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @bswap_v32i16(<32 x i16>* %a) #0 { +define void @bswap_v32i16(ptr %a) #0 { ; VBITS_GE_256-LABEL: bswap_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -435,13 +435,13 @@ define void @bswap_v32i16(<32 x i16>* %a) #0 { ; VBITS_GE_512-NEXT: revb z0.h, p0/m, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <32 x i16>, <32 x i16>* %a + %op = load <32 x i16>, ptr %a %res = call <32 x i16> @llvm.bswap.v32i16(<32 x i16> %op) - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @bswap_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { +define void @bswap_v64i16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: bswap_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -449,13 +449,13 @@ define void @bswap_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: revb z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x i16>, <64 x i16>* %a + %op = load <64 x i16>, ptr %a %res = call <64 x i16> @llvm.bswap.v64i16(<64 x i16> %op) - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @bswap_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { +define void @bswap_v128i16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: bswap_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -463,9 +463,9 @@ define void @bswap_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: revb z0.h, p0/m, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op = load <128 x i16>, <128 x i16>* %a + %op = load <128 x i16>, ptr %a %res = call <128 x i16> @llvm.bswap.v128i16(<128 x i16> %op) - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -489,7 +489,7 @@ define <4 x i32> @bswap_v4i32(<4 x i32> %op) vscale_range(2,0) #0 { ret <4 x i32> %res } -define void @bswap_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { +define void @bswap_v8i32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: bswap_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -497,13 +497,13 @@ define void @bswap_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: revb z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <8 x i32>, <8 x i32>* %a + %op = load <8 x i32>, ptr %a %res = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %op) - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @bswap_v16i32(<16 x i32>* %a) #0 { +define void @bswap_v16i32(ptr %a) #0 { ; VBITS_GE_256-LABEL: bswap_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -523,13 +523,13 @@ define void @bswap_v16i32(<16 x i32>* %a) #0 { ; VBITS_GE_512-NEXT: revb z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <16 x i32>, <16 x i32>* %a + %op = load <16 x i32>, ptr %a %res = call <16 x i32> @llvm.bswap.v16i32(<16 x i32> %op) - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @bswap_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { +define void @bswap_v32i32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: bswap_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -537,13 +537,13 @@ define void @bswap_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: revb z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x i32>, <32 x i32>* %a + %op = load <32 x i32>, ptr %a %res = call <32 x i32> @llvm.bswap.v32i32(<32 x i32> %op) - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @bswap_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { +define void @bswap_v64i32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: bswap_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -551,9 +551,9 @@ define void @bswap_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: revb z0.s, p0/m, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op = load <64 x i32>, <64 x i32>* %a + %op = load <64 x i32>, ptr %a %res = call <64 x i32> @llvm.bswap.v64i32(<64 x i32> %op) - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -577,7 +577,7 @@ define <2 x i64> @bswap_v2i64(<2 x i64> %op) vscale_range(2,0) #0 { ret <2 x i64> %res } -define void @bswap_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { +define void @bswap_v4i64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: bswap_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -585,13 +585,13 @@ define void @bswap_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: revb z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <4 x i64>, <4 x i64>* %a + %op = load <4 x i64>, ptr %a %res = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %op) - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @bswap_v8i64(<8 x i64>* %a) #0 { +define void @bswap_v8i64(ptr %a) #0 { ; VBITS_GE_256-LABEL: bswap_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -611,13 +611,13 @@ define void @bswap_v8i64(<8 x i64>* %a) #0 { ; VBITS_GE_512-NEXT: revb z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op = load <8 x i64>, <8 x i64>* %a + %op = load <8 x i64>, ptr %a %res = call <8 x i64> @llvm.bswap.v8i64(<8 x i64> %op) - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @bswap_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { +define void @bswap_v16i64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: bswap_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -625,13 +625,13 @@ define void @bswap_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: revb z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <16 x i64>, <16 x i64>* %a + %op = load <16 x i64>, ptr %a %res = call <16 x i64> @llvm.bswap.v16i64(<16 x i64> %op) - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @bswap_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { +define void @bswap_v32i64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: bswap_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -639,9 +639,9 @@ define void @bswap_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: revb z0.d, p0/m, z0.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op = load <32 x i64>, <32 x i64>* %a + %op = load <32 x i64>, ptr %a %res = call <32 x i64> @llvm.bswap.v32i64(<32 x i64> %op) - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll index e62cbcd..108d41f 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll @@ -29,7 +29,7 @@ define <16 x i8> @sdiv_v16i8(<16 x i8> %op1) vscale_range(2,0) #0 { ret <16 x i8> %res } -define void @sdiv_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { +define void @sdiv_v32i8(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: sdiv_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -37,13 +37,13 @@ define void @sdiv_v32i8(<32 x i8>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #5 ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a + %op1 = load <32 x i8>, ptr %a %res = sdiv <32 x i8> %op1, shufflevector (<32 x i8> insertelement (<32 x i8> poison, i8 32, i32 0), <32 x i8> poison, <32 x i32> zeroinitializer) - store <32 x i8> %res, <32 x i8>* %a + store <32 x i8> %res, ptr %a ret void } -define void @sdiv_v64i8(<64 x i8>* %a) #0 { +define void @sdiv_v64i8(ptr %a) #0 { ; VBITS_GE_256-LABEL: sdiv_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -63,13 +63,13 @@ define void @sdiv_v64i8(<64 x i8>* %a) #0 { ; VBITS_GE_512-NEXT: asrd z0.b, p0/m, z0.b, #5 ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a + %op1 = load <64 x i8>, ptr %a %res = sdiv <64 x i8> %op1, shufflevector (<64 x i8> insertelement (<64 x i8> poison, i8 32, i32 0), <64 x i8> poison, <64 x i32> zeroinitializer) - store <64 x i8> %res, <64 x i8>* %a + store <64 x i8> %res, ptr %a ret void } -define void @sdiv_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { +define void @sdiv_v128i8(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: sdiv_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -77,13 +77,13 @@ define void @sdiv_v128i8(<128 x i8>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #5 ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a + %op1 = load <128 x i8>, ptr %a %res = sdiv <128 x i8> %op1, shufflevector (<128 x i8> insertelement (<128 x i8> poison, i8 32, i32 0), <128 x i8> poison, <128 x i32> zeroinitializer) - store <128 x i8> %res, <128 x i8>* %a + store <128 x i8> %res, ptr %a ret void } -define void @sdiv_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { +define void @sdiv_v256i8(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: sdiv_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -91,9 +91,9 @@ define void @sdiv_v256i8(<256 x i8>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #5 ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a + %op1 = load <256 x i8>, ptr %a %res = sdiv <256 x i8> %op1, shufflevector (<256 x i8> insertelement (<256 x i8> poison, i8 32, i32 0), <256 x i8> poison, <256 x i32> zeroinitializer) - store <256 x i8> %res, <256 x i8>* %a + store <256 x i8> %res, ptr %a ret void } @@ -121,7 +121,7 @@ define <8 x i16> @sdiv_v8i16(<8 x i16> %op1) vscale_range(2,0) #0 { ret <8 x i16> %res } -define void @sdiv_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { +define void @sdiv_v16i16(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: sdiv_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -129,13 +129,13 @@ define void @sdiv_v16i16(<16 x i16>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #5 ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a + %op1 = load <16 x i16>, ptr %a %res = sdiv <16 x i16> %op1, shufflevector (<16 x i16> insertelement (<16 x i16> poison, i16 32, i32 0), <16 x i16> poison, <16 x i32> zeroinitializer) - store <16 x i16> %res, <16 x i16>* %a + store <16 x i16> %res, ptr %a ret void } -define void @sdiv_v32i16(<32 x i16>* %a) #0 { +define void @sdiv_v32i16(ptr %a) #0 { ; VBITS_GE_256-LABEL: sdiv_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -155,13 +155,13 @@ define void @sdiv_v32i16(<32 x i16>* %a) #0 { ; VBITS_GE_512-NEXT: asrd z0.h, p0/m, z0.h, #5 ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a + %op1 = load <32 x i16>, ptr %a %res = sdiv <32 x i16> %op1, shufflevector (<32 x i16> insertelement (<32 x i16> poison, i16 32, i32 0), <32 x i16> poison, <32 x i32> zeroinitializer) - store <32 x i16> %res, <32 x i16>* %a + store <32 x i16> %res, ptr %a ret void } -define void @sdiv_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { +define void @sdiv_v64i16(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: sdiv_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -169,13 +169,13 @@ define void @sdiv_v64i16(<64 x i16>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #5 ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a + %op1 = load <64 x i16>, ptr %a %res = sdiv <64 x i16> %op1, shufflevector (<64 x i16> insertelement (<64 x i16> poison, i16 32, i32 0), <64 x i16> poison, <64 x i32> zeroinitializer) - store <64 x i16> %res, <64 x i16>* %a + store <64 x i16> %res, ptr %a ret void } -define void @sdiv_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { +define void @sdiv_v128i16(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: sdiv_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -183,9 +183,9 @@ define void @sdiv_v128i16(<128 x i16>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #5 ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a + %op1 = load <128 x i16>, ptr %a %res = sdiv <128 x i16> %op1, shufflevector (<128 x i16> insertelement (<128 x i16> poison, i16 32, i32 0), <128 x i16> poison, <128 x i32> zeroinitializer) - store <128 x i16> %res, <128 x i16>* %a + store <128 x i16> %res, ptr %a ret void } @@ -213,7 +213,7 @@ define <4 x i32> @sdiv_v4i32(<4 x i32> %op1) vscale_range(2,0) #0 { ret <4 x i32> %res } -define void @sdiv_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { +define void @sdiv_v8i32(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: sdiv_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -221,13 +221,13 @@ define void @sdiv_v8i32(<8 x i32>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #5 ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a + %op1 = load <8 x i32>, ptr %a %res = sdiv <8 x i32> %op1, shufflevector (<8 x i32> insertelement (<8 x i32> poison, i32 32, i32 0), <8 x i32> poison, <8 x i32> zeroinitializer) - store <8 x i32> %res, <8 x i32>* %a + store <8 x i32> %res, ptr %a ret void } -define void @sdiv_v16i32(<16 x i32>* %a) #0 { +define void @sdiv_v16i32(ptr %a) #0 { ; VBITS_GE_256-LABEL: sdiv_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -247,13 +247,13 @@ define void @sdiv_v16i32(<16 x i32>* %a) #0 { ; VBITS_GE_512-NEXT: asrd z0.s, p0/m, z0.s, #5 ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a + %op1 = load <16 x i32>, ptr %a %res = sdiv <16 x i32> %op1, shufflevector (<16 x i32> insertelement (<16 x i32> poison, i32 32, i32 0), <16 x i32> poison, <16 x i32> zeroinitializer) - store <16 x i32> %res, <16 x i32>* %a + store <16 x i32> %res, ptr %a ret void } -define void @sdiv_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { +define void @sdiv_v32i32(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: sdiv_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -261,13 +261,13 @@ define void @sdiv_v32i32(<32 x i32>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #5 ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a + %op1 = load <32 x i32>, ptr %a %res = sdiv <32 x i32> %op1, shufflevector (<32 x i32> insertelement (<32 x i32> poison, i32 32, i32 0), <32 x i32> poison, <32 x i32> zeroinitializer) - store <32 x i32> %res, <32 x i32>* %a + store <32 x i32> %res, ptr %a ret void } -define void @sdiv_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { +define void @sdiv_v64i32(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: sdiv_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -275,9 +275,9 @@ define void @sdiv_v64i32(<64 x i32>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #5 ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a + %op1 = load <64 x i32>, ptr %a %res = sdiv <64 x i32> %op1, shufflevector (<64 x i32> insertelement (<64 x i32> poison, i32 32, i32 0), <64 x i32> poison, <64 x i32> zeroinitializer) - store <64 x i32> %res, <64 x i32>* %a + store <64 x i32> %res, ptr %a ret void } @@ -306,7 +306,7 @@ define <2 x i64> @sdiv_v2i64(<2 x i64> %op1) vscale_range(2,0) #0 { ret <2 x i64> %res } -define void @sdiv_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { +define void @sdiv_v4i64(ptr %a) vscale_range(2,0) #0 { ; CHECK-LABEL: sdiv_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -314,13 +314,13 @@ define void @sdiv_v4i64(<4 x i64>* %a) vscale_range(2,0) #0 { ; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #5 ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a + %op1 = load <4 x i64>, ptr %a %res = sdiv <4 x i64> %op1, shufflevector (<4 x i64> insertelement (<4 x i64> poison, i64 32, i32 0), <4 x i64> poison, <4 x i32> zeroinitializer) - store <4 x i64> %res, <4 x i64>* %a + store <4 x i64> %res, ptr %a ret void } -define void @sdiv_v8i64(<8 x i64>* %a) #0 { +define void @sdiv_v8i64(ptr %a) #0 { ; VBITS_GE_256-LABEL: sdiv_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -340,13 +340,13 @@ define void @sdiv_v8i64(<8 x i64>* %a) #0 { ; VBITS_GE_512-NEXT: asrd z0.d, p0/m, z0.d, #5 ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a + %op1 = load <8 x i64>, ptr %a %res = sdiv <8 x i64> %op1, shufflevector (<8 x i64> insertelement (<8 x i64> poison, i64 32, i32 0), <8 x i64> poison, <8 x i32> zeroinitializer) - store <8 x i64> %res, <8 x i64>* %a + store <8 x i64> %res, ptr %a ret void } -define void @sdiv_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { +define void @sdiv_v16i64(ptr %a) vscale_range(8,0) #0 { ; CHECK-LABEL: sdiv_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -354,13 +354,13 @@ define void @sdiv_v16i64(<16 x i64>* %a) vscale_range(8,0) #0 { ; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #5 ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a + %op1 = load <16 x i64>, ptr %a %res = sdiv <16 x i64> %op1, shufflevector (<16 x i64> insertelement (<16 x i64> poison, i64 32, i32 0), <16 x i64> poison, <16 x i32> zeroinitializer) - store <16 x i64> %res, <16 x i64>* %a + store <16 x i64> %res, ptr %a ret void } -define void @sdiv_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { +define void @sdiv_v32i64(ptr %a) vscale_range(16,0) #0 { ; CHECK-LABEL: sdiv_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -368,9 +368,9 @@ define void @sdiv_v32i64(<32 x i64>* %a) vscale_range(16,0) #0 { ; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #5 ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a + %op1 = load <32 x i64>, ptr %a %res = sdiv <32 x i64> %op1, shufflevector (<32 x i64> insertelement (<32 x i64> poison, i64 32, i32 0), <32 x i64> poison, <32 x i32> zeroinitializer) - store <32 x i64> %res, <32 x i64>* %a + store <32 x i64> %res, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll index 33877e1..a4d37ca 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll @@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu" ; bigger than NEON. However, having no support opens us up to a code generator ; hang when expanding BUILD_VECTOR. Here we just validate the promblematic case ; successfully exits code generation. -define void @hang_when_merging_stores_after_legalisation(<8 x i32>* %a, <2 x i32> %b) vscale_range(2,2) #0 { +define void @hang_when_merging_stores_after_legalisation(ptr %a, <2 x i32> %b) vscale_range(2,2) #0 { ; CHECK-LABEL: hang_when_merging_stores_after_legalisation: ; CHECK: // %bb.0: ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill @@ -33,12 +33,12 @@ define void @hang_when_merging_stores_after_legalisation(<8 x i32>* %a, <2 x i32 ; CHECK-NEXT: ret %splat = shufflevector <2 x i32> %b, <2 x i32> undef, <8 x i32> zeroinitializer %interleaved.vec = shufflevector <8 x i32> %splat, <8 x i32> undef, <8 x i32> - store <8 x i32> %interleaved.vec, <8 x i32>* %a, align 4 + store <8 x i32> %interleaved.vec, ptr %a, align 4 ret void } ; Ensure we don't crash when trying to lower a shuffle via an extract -define void @crash_when_lowering_extract_shuffle(<32 x i32>* %dst, i1 %cond) vscale_range(2,2) #0 { +define void @crash_when_lowering_extract_shuffle(ptr %dst, i1 %cond) vscale_range(2,2) #0 { ; CHECK-LABEL: crash_when_lowering_extract_shuffle: ; CHECK: // %bb.0: ; CHECK-NEXT: tbnz w1, #0, .LBB1_2 @@ -123,9 +123,9 @@ define void @crash_when_lowering_extract_shuffle(<32 x i32>* %dst, i1 %cond) vsc br i1 %cond, label %exit, label %vector.body vector.body: - %1 = load <32 x i32>, <32 x i32>* %dst, align 16 + %1 = load <32 x i32>, ptr %dst, align 16 %predphi = select <32 x i1> %broadcast.splat, <32 x i32> zeroinitializer, <32 x i32> %1 - store <32 x i32> %predphi, <32 x i32>* %dst, align 16 + store <32 x i32> %predphi, ptr %dst, align 16 br label %exit exit: diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll index 50d0941..8542736 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll @@ -31,7 +31,7 @@ define <16 x i8> @splat_v16i8(i8 %a) vscale_range(2,0) #0 { ret <16 x i8> %splat } -define void @splat_v32i8(i8 %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @splat_v32i8(i8 %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: splat_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -40,11 +40,11 @@ define void @splat_v32i8(i8 %a, <32 x i8>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <32 x i8> undef, i8 %a, i64 0 %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer - store <32 x i8> %splat, <32 x i8>* %b + store <32 x i8> %splat, ptr %b ret void } -define void @splat_v64i8(i8 %a, <64 x i8>* %b) #0 { +define void @splat_v64i8(i8 %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: splat_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -62,11 +62,11 @@ define void @splat_v64i8(i8 %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: ret %insert = insertelement <64 x i8> undef, i8 %a, i64 0 %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer - store <64 x i8> %splat, <64 x i8>* %b + store <64 x i8> %splat, ptr %b ret void } -define void @splat_v128i8(i8 %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @splat_v128i8(i8 %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: splat_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -75,11 +75,11 @@ define void @splat_v128i8(i8 %a, <128 x i8>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <128 x i8> undef, i8 %a, i64 0 %splat = shufflevector <128 x i8> %insert, <128 x i8> undef, <128 x i32> zeroinitializer - store <128 x i8> %splat, <128 x i8>* %b + store <128 x i8> %splat, ptr %b ret void } -define void @splat_v256i8(i8 %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @splat_v256i8(i8 %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: splat_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -88,7 +88,7 @@ define void @splat_v256i8(i8 %a, <256 x i8>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <256 x i8> undef, i8 %a, i64 0 %splat = shufflevector <256 x i8> %insert, <256 x i8> undef, <256 x i32> zeroinitializer - store <256 x i8> %splat, <256 x i8>* %b + store <256 x i8> %splat, ptr %b ret void } @@ -114,7 +114,7 @@ define <8 x i16> @splat_v8i16(i16 %a) vscale_range(2,0) #0 { ret <8 x i16> %splat } -define void @splat_v16i16(i16 %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @splat_v16i16(i16 %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: splat_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -123,11 +123,11 @@ define void @splat_v16i16(i16 %a, <16 x i16>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <16 x i16> undef, i16 %a, i64 0 %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer - store <16 x i16> %splat, <16 x i16>* %b + store <16 x i16> %splat, ptr %b ret void } -define void @splat_v32i16(i16 %a, <32 x i16>* %b) #0 { +define void @splat_v32i16(i16 %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: splat_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -145,11 +145,11 @@ define void @splat_v32i16(i16 %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: ret %insert = insertelement <32 x i16> undef, i16 %a, i64 0 %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer - store <32 x i16> %splat, <32 x i16>* %b + store <32 x i16> %splat, ptr %b ret void } -define void @splat_v64i16(i16 %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @splat_v64i16(i16 %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: splat_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -158,11 +158,11 @@ define void @splat_v64i16(i16 %a, <64 x i16>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <64 x i16> undef, i16 %a, i64 0 %splat = shufflevector <64 x i16> %insert, <64 x i16> undef, <64 x i32> zeroinitializer - store <64 x i16> %splat, <64 x i16>* %b + store <64 x i16> %splat, ptr %b ret void } -define void @splat_v128i16(i16 %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @splat_v128i16(i16 %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: splat_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -171,7 +171,7 @@ define void @splat_v128i16(i16 %a, <128 x i16>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <128 x i16> undef, i16 %a, i64 0 %splat = shufflevector <128 x i16> %insert, <128 x i16> undef, <128 x i32> zeroinitializer - store <128 x i16> %splat, <128 x i16>* %b + store <128 x i16> %splat, ptr %b ret void } @@ -197,7 +197,7 @@ define <4 x i32> @splat_v4i32(i32 %a) vscale_range(2,0) #0 { ret <4 x i32> %splat } -define void @splat_v8i32(i32 %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @splat_v8i32(i32 %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: splat_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -206,11 +206,11 @@ define void @splat_v8i32(i32 %a, <8 x i32>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <8 x i32> undef, i32 %a, i64 0 %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer - store <8 x i32> %splat, <8 x i32>* %b + store <8 x i32> %splat, ptr %b ret void } -define void @splat_v16i32(i32 %a, <16 x i32>* %b) #0 { +define void @splat_v16i32(i32 %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: splat_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -228,11 +228,11 @@ define void @splat_v16i32(i32 %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: ret %insert = insertelement <16 x i32> undef, i32 %a, i64 0 %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer - store <16 x i32> %splat, <16 x i32>* %b + store <16 x i32> %splat, ptr %b ret void } -define void @splat_v32i32(i32 %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @splat_v32i32(i32 %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: splat_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -241,11 +241,11 @@ define void @splat_v32i32(i32 %a, <32 x i32>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <32 x i32> undef, i32 %a, i64 0 %splat = shufflevector <32 x i32> %insert, <32 x i32> undef, <32 x i32> zeroinitializer - store <32 x i32> %splat, <32 x i32>* %b + store <32 x i32> %splat, ptr %b ret void } -define void @splat_v64i32(i32 %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @splat_v64i32(i32 %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: splat_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -254,7 +254,7 @@ define void @splat_v64i32(i32 %a, <64 x i32>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <64 x i32> undef, i32 %a, i64 0 %splat = shufflevector <64 x i32> %insert, <64 x i32> undef, <64 x i32> zeroinitializer - store <64 x i32> %splat, <64 x i32>* %b + store <64 x i32> %splat, ptr %b ret void } @@ -280,7 +280,7 @@ define <2 x i64> @splat_v2i64(i64 %a) vscale_range(2,0) #0 { ret <2 x i64> %splat } -define void @splat_v4i64(i64 %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @splat_v4i64(i64 %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: splat_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -289,11 +289,11 @@ define void @splat_v4i64(i64 %a, <4 x i64>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <4 x i64> undef, i64 %a, i64 0 %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer - store <4 x i64> %splat, <4 x i64>* %b + store <4 x i64> %splat, ptr %b ret void } -define void @splat_v8i64(i64 %a, <8 x i64>* %b) #0 { +define void @splat_v8i64(i64 %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: splat_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -311,11 +311,11 @@ define void @splat_v8i64(i64 %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: ret %insert = insertelement <8 x i64> undef, i64 %a, i64 0 %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer - store <8 x i64> %splat, <8 x i64>* %b + store <8 x i64> %splat, ptr %b ret void } -define void @splat_v16i64(i64 %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @splat_v16i64(i64 %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: splat_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -324,11 +324,11 @@ define void @splat_v16i64(i64 %a, <16 x i64>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <16 x i64> undef, i64 %a, i64 0 %splat = shufflevector <16 x i64> %insert, <16 x i64> undef, <16 x i32> zeroinitializer - store <16 x i64> %splat, <16 x i64>* %b + store <16 x i64> %splat, ptr %b ret void } -define void @splat_v32i64(i64 %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @splat_v32i64(i64 %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: splat_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -337,7 +337,7 @@ define void @splat_v32i64(i64 %a, <32 x i64>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <32 x i64> undef, i64 %a, i64 0 %splat = shufflevector <32 x i64> %insert, <32 x i64> undef, <32 x i32> zeroinitializer - store <32 x i64> %splat, <32 x i64>* %b + store <32 x i64> %splat, ptr %b ret void } @@ -369,7 +369,7 @@ define <8 x half> @splat_v8f16(half %a) vscale_range(2,0) #0 { ret <8 x half> %splat } -define void @splat_v16f16(half %a, <16 x half>* %b) vscale_range(2,0) #0 { +define void @splat_v16f16(half %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: splat_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0 @@ -379,11 +379,11 @@ define void @splat_v16f16(half %a, <16 x half>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <16 x half> undef, half %a, i64 0 %splat = shufflevector <16 x half> %insert, <16 x half> undef, <16 x i32> zeroinitializer - store <16 x half> %splat, <16 x half>* %b + store <16 x half> %splat, ptr %b ret void } -define void @splat_v32f16(half %a, <32 x half>* %b) #0 { +define void @splat_v32f16(half %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: splat_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -403,11 +403,11 @@ define void @splat_v32f16(half %a, <32 x half>* %b) #0 { ; VBITS_GE_512-NEXT: ret %insert = insertelement <32 x half> undef, half %a, i64 0 %splat = shufflevector <32 x half> %insert, <32 x half> undef, <32 x i32> zeroinitializer - store <32 x half> %splat, <32 x half>* %b + store <32 x half> %splat, ptr %b ret void } -define void @splat_v64f16(half %a, <64 x half>* %b) vscale_range(8,0) #0 { +define void @splat_v64f16(half %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: splat_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0 @@ -417,11 +417,11 @@ define void @splat_v64f16(half %a, <64 x half>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <64 x half> undef, half %a, i64 0 %splat = shufflevector <64 x half> %insert, <64 x half> undef, <64 x i32> zeroinitializer - store <64 x half> %splat, <64 x half>* %b + store <64 x half> %splat, ptr %b ret void } -define void @splat_v128f16(half %a, <128 x half>* %b) vscale_range(16,0) #0 { +define void @splat_v128f16(half %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: splat_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0 @@ -431,7 +431,7 @@ define void @splat_v128f16(half %a, <128 x half>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <128 x half> undef, half %a, i64 0 %splat = shufflevector <128 x half> %insert, <128 x half> undef, <128 x i32> zeroinitializer - store <128 x half> %splat, <128 x half>* %b + store <128 x half> %splat, ptr %b ret void } @@ -459,7 +459,7 @@ define <4 x float> @splat_v4f32(float %a, <4 x float> %op2) vscale_range(2,0) #0 ret <4 x float> %splat } -define void @splat_v8f32(float %a, <8 x float>* %b) vscale_range(2,0) #0 { +define void @splat_v8f32(float %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: splat_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0 @@ -469,11 +469,11 @@ define void @splat_v8f32(float %a, <8 x float>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <8 x float> undef, float %a, i64 0 %splat = shufflevector <8 x float> %insert, <8 x float> undef, <8 x i32> zeroinitializer - store <8 x float> %splat, <8 x float>* %b + store <8 x float> %splat, ptr %b ret void } -define void @splat_v16f32(float %a, <16 x float>* %b) #0 { +define void @splat_v16f32(float %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: splat_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -493,11 +493,11 @@ define void @splat_v16f32(float %a, <16 x float>* %b) #0 { ; VBITS_GE_512-NEXT: ret %insert = insertelement <16 x float> undef, float %a, i64 0 %splat = shufflevector <16 x float> %insert, <16 x float> undef, <16 x i32> zeroinitializer - store <16 x float> %splat, <16 x float>* %b + store <16 x float> %splat, ptr %b ret void } -define void @splat_v32f32(float %a, <32 x float>* %b) vscale_range(8,0) #0 { +define void @splat_v32f32(float %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: splat_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0 @@ -507,11 +507,11 @@ define void @splat_v32f32(float %a, <32 x float>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <32 x float> undef, float %a, i64 0 %splat = shufflevector <32 x float> %insert, <32 x float> undef, <32 x i32> zeroinitializer - store <32 x float> %splat, <32 x float>* %b + store <32 x float> %splat, ptr %b ret void } -define void @splat_v64f32(float %a, <64 x float>* %b) vscale_range(16,0) #0 { +define void @splat_v64f32(float %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: splat_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0 @@ -521,7 +521,7 @@ define void @splat_v64f32(float %a, <64 x float>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <64 x float> undef, float %a, i64 0 %splat = shufflevector <64 x float> %insert, <64 x float> undef, <64 x i32> zeroinitializer - store <64 x float> %splat, <64 x float>* %b + store <64 x float> %splat, ptr %b ret void } @@ -547,7 +547,7 @@ define <2 x double> @splat_v2f64(double %a, <2 x double> %op2) vscale_range(2,0) ret <2 x double> %splat } -define void @splat_v4f64(double %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @splat_v4f64(double %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: splat_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 @@ -557,11 +557,11 @@ define void @splat_v4f64(double %a, <4 x double>* %b) vscale_range(2,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <4 x double> undef, double %a, i64 0 %splat = shufflevector <4 x double> %insert, <4 x double> undef, <4 x i32> zeroinitializer - store <4 x double> %splat, <4 x double>* %b + store <4 x double> %splat, ptr %b ret void } -define void @splat_v8f64(double %a, <8 x double>* %b) #0 { +define void @splat_v8f64(double %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: splat_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -581,11 +581,11 @@ define void @splat_v8f64(double %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: ret %insert = insertelement <8 x double> undef, double %a, i64 0 %splat = shufflevector <8 x double> %insert, <8 x double> undef, <8 x i32> zeroinitializer - store <8 x double> %splat, <8 x double>* %b + store <8 x double> %splat, ptr %b ret void } -define void @splat_v16f64(double %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @splat_v16f64(double %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: splat_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 @@ -595,11 +595,11 @@ define void @splat_v16f64(double %a, <16 x double>* %b) vscale_range(8,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <16 x double> undef, double %a, i64 0 %splat = shufflevector <16 x double> %insert, <16 x double> undef, <16 x i32> zeroinitializer - store <16 x double> %splat, <16 x double>* %b + store <16 x double> %splat, ptr %b ret void } -define void @splat_v32f64(double %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @splat_v32f64(double %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: splat_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 @@ -609,7 +609,7 @@ define void @splat_v32f64(double %a, <32 x double>* %b) vscale_range(16,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <32 x double> undef, double %a, i64 0 %splat = shufflevector <32 x double> %insert, <32 x double> undef, <32 x i32> zeroinitializer - store <32 x double> %splat, <32 x double>* %b + store <32 x double> %splat, ptr %b ret void } @@ -617,7 +617,7 @@ define void @splat_v32f64(double %a, <32 x double>* %b) vscale_range(16,0) #0 { ; DUP (integer immediate) ; -define void @splat_imm_v64i8(<64 x i8>* %a) vscale_range(4,0) #0 { +define void @splat_imm_v64i8(ptr %a) vscale_range(4,0) #0 { ; CHECK-LABEL: splat_imm_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: mov z0.b, #1 // =0x1 @@ -626,11 +626,11 @@ define void @splat_imm_v64i8(<64 x i8>* %a) vscale_range(4,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <64 x i8> undef, i8 1, i64 0 %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer - store <64 x i8> %splat, <64 x i8>* %a + store <64 x i8> %splat, ptr %a ret void } -define void @splat_imm_v32i16(<32 x i16>* %a) vscale_range(4,0) #0 { +define void @splat_imm_v32i16(ptr %a) vscale_range(4,0) #0 { ; CHECK-LABEL: splat_imm_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: mov z0.h, #2 // =0x2 @@ -639,11 +639,11 @@ define void @splat_imm_v32i16(<32 x i16>* %a) vscale_range(4,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <32 x i16> undef, i16 2, i64 0 %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer - store <32 x i16> %splat, <32 x i16>* %a + store <32 x i16> %splat, ptr %a ret void } -define void @splat_imm_v16i32(<16 x i32>* %a) vscale_range(4,0) #0 { +define void @splat_imm_v16i32(ptr %a) vscale_range(4,0) #0 { ; CHECK-LABEL: splat_imm_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: mov z0.s, #3 // =0x3 @@ -652,11 +652,11 @@ define void @splat_imm_v16i32(<16 x i32>* %a) vscale_range(4,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <16 x i32> undef, i32 3, i64 0 %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer - store <16 x i32> %splat, <16 x i32>* %a + store <16 x i32> %splat, ptr %a ret void } -define void @splat_imm_v8i64(<8 x i64>* %a) vscale_range(4,0) #0 { +define void @splat_imm_v8i64(ptr %a) vscale_range(4,0) #0 { ; CHECK-LABEL: splat_imm_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: mov z0.d, #4 // =0x4 @@ -665,7 +665,7 @@ define void @splat_imm_v8i64(<8 x i64>* %a) vscale_range(4,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <8 x i64> undef, i64 4, i64 0 %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer - store <8 x i64> %splat, <8 x i64>* %a + store <8 x i64> %splat, ptr %a ret void } @@ -673,7 +673,7 @@ define void @splat_imm_v8i64(<8 x i64>* %a) vscale_range(4,0) #0 { ; DUP (floating-point immediate) ; -define void @splat_imm_v32f16(<32 x half>* %a) vscale_range(4,0) #0 { +define void @splat_imm_v32f16(ptr %a) vscale_range(4,0) #0 { ; CHECK-LABEL: splat_imm_v32f16: ; CHECK: // %bb.0: ; CHECK-NEXT: fmov z0.h, #5.00000000 @@ -682,11 +682,11 @@ define void @splat_imm_v32f16(<32 x half>* %a) vscale_range(4,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <32 x half> undef, half 5.0, i64 0 %splat = shufflevector <32 x half> %insert, <32 x half> undef, <32 x i32> zeroinitializer - store <32 x half> %splat, <32 x half>* %a + store <32 x half> %splat, ptr %a ret void } -define void @splat_imm_v16f32(<16 x float>* %a) vscale_range(4,0) #0 { +define void @splat_imm_v16f32(ptr %a) vscale_range(4,0) #0 { ; CHECK-LABEL: splat_imm_v16f32: ; CHECK: // %bb.0: ; CHECK-NEXT: fmov z0.s, #6.00000000 @@ -695,11 +695,11 @@ define void @splat_imm_v16f32(<16 x float>* %a) vscale_range(4,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <16 x float> undef, float 6.0, i64 0 %splat = shufflevector <16 x float> %insert, <16 x float> undef, <16 x i32> zeroinitializer - store <16 x float> %splat, <16 x float>* %a + store <16 x float> %splat, ptr %a ret void } -define void @splat_imm_v8f64(<8 x double>* %a) vscale_range(4,0) #0 { +define void @splat_imm_v8f64(ptr %a) vscale_range(4,0) #0 { ; CHECK-LABEL: splat_imm_v8f64: ; CHECK: // %bb.0: ; CHECK-NEXT: fmov z0.d, #7.00000000 @@ -708,7 +708,7 @@ define void @splat_imm_v8f64(<8 x double>* %a) vscale_range(4,0) #0 { ; CHECK-NEXT: ret %insert = insertelement <8 x double> undef, double 7.0, i64 0 %splat = shufflevector <8 x double> %insert, <8 x double> undef, <8 x i32> zeroinitializer - store <8 x double> %splat, <8 x double>* %a + store <8 x double> %splat, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-stores.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-stores.ll index 0b4c08d..0acdc8d 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-stores.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-stores.ll @@ -19,37 +19,37 @@ target triple = "aarch64-unknown-linux-gnu" ; Don't use SVE for 64-bit vectors. -define void @store_v2f32(<2 x float>* %a) #0 { +define void @store_v2f32(ptr %a) #0 { ; CHECK-LABEL: store_v2f32: ; CHECK: // %bb.0: ; CHECK-NEXT: str xzr, [x0] ; CHECK-NEXT: ret - store <2 x float> zeroinitializer, <2 x float>* %a + store <2 x float> zeroinitializer, ptr %a ret void } ; Don't use SVE for 128-bit vectors. -define void @store_v4f32(<4 x float>* %a) #0 { +define void @store_v4f32(ptr %a) #0 { ; CHECK-LABEL: store_v4f32: ; CHECK: // %bb.0: ; CHECK-NEXT: stp xzr, xzr, [x0] ; CHECK-NEXT: ret - store <4 x float> zeroinitializer, <4 x float>* %a + store <4 x float> zeroinitializer, ptr %a ret void } -define void @store_v8f32(<8 x float>* %a) #0 { +define void @store_v8f32(ptr %a) #0 { ; CHECK-LABEL: store_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 ; CHECK-NEXT: mov z0.s, #0 // =0x0 ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret - store <8 x float> zeroinitializer, <8 x float>* %a + store <8 x float> zeroinitializer, ptr %a ret void } -define void @store_v16f32(<16 x float>* %a) #0 { +define void @store_v16f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: store_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -79,11 +79,11 @@ define void @store_v16f32(<16 x float>* %a) #0 { ; VBITS_GE_2048-NEXT: mov z0.s, #0 // =0x0 ; VBITS_GE_2048-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_2048-NEXT: ret - store <16 x float> zeroinitializer, <16 x float>* %a + store <16 x float> zeroinitializer, ptr %a ret void } -define void @store_v32f32(<32 x float>* %a) #0 { +define void @store_v32f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: store_v32f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #24 @@ -119,11 +119,11 @@ define void @store_v32f32(<32 x float>* %a) #0 { ; VBITS_GE_2048-NEXT: mov z0.s, #0 // =0x0 ; VBITS_GE_2048-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_2048-NEXT: ret - store <32 x float> zeroinitializer, <32 x float>* %a + store <32 x float> zeroinitializer, ptr %a ret void } -define void @store_v64f32(<64 x float>* %a) #0 { +define void @store_v64f32(ptr %a) #0 { ; VBITS_GE_256-LABEL: store_v64f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #56 @@ -173,7 +173,7 @@ define void @store_v64f32(<64 x float>* %a) #0 { ; VBITS_GE_2048-NEXT: mov z0.s, #0 // =0x0 ; VBITS_GE_2048-NEXT: st1w { z0.s }, p0, [x0] ; VBITS_GE_2048-NEXT: ret - store <64 x float> zeroinitializer, <64 x float>* %a + store <64 x float> zeroinitializer, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll index 2ce5a2d..6093a2c 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll @@ -14,36 +14,36 @@ target triple = "aarch64-unknown-linux-gnu" -define void @subvector_v8i16(<8 x i16> *%in, <8 x i16>* %out) vscale_range(2,0) #0 { +define void @subvector_v8i16(ptr %in, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: subvector_v8i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %a = load <8 x i16>, <8 x i16>* %in + %a = load <8 x i16>, ptr %in br label %bb1 bb1: - store <8 x i16> %a, <8 x i16>* %out + store <8 x i16> %a, ptr %out ret void } -define void @subvector_v16i16(<16 x i16> *%in, <16 x i16>* %out) vscale_range(2,0) #0 { +define void @subvector_v16i16(ptr %in, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: subvector_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %a = load <16 x i16>, <16 x i16>* %in + %a = load <16 x i16>, ptr %in br label %bb1 bb1: - store <16 x i16> %a, <16 x i16>* %out + store <16 x i16> %a, ptr %out ret void } -define void @subvector_v32i16(<32 x i16> *%in, <32 x i16>* %out) #0 { +define void @subvector_v32i16(ptr %in, ptr %out) #0 { ; VBITS_GE_256-LABEL: subvector_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -60,45 +60,45 @@ define void @subvector_v32i16(<32 x i16> *%in, <32 x i16>* %out) #0 { ; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0] ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <32 x i16>, <32 x i16>* %in + %a = load <32 x i16>, ptr %in br label %bb1 bb1: - store <32 x i16> %a, <32 x i16>* %out + store <32 x i16> %a, ptr %out ret void } -define void @subvector_v64i16(<64 x i16> *%in, <64 x i16>* %out) vscale_range(8,0) #0 { +define void @subvector_v64i16(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: subvector_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %a = load <64 x i16>, <64 x i16>* %in + %a = load <64 x i16>, ptr %in br label %bb1 bb1: - store <64 x i16> %a, <64 x i16>* %out + store <64 x i16> %a, ptr %out ret void } -define void @subvector_v8i32(<8 x i32> *%in, <8 x i32>* %out) vscale_range(2,0) #0 { +define void @subvector_v8i32(ptr %in, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: subvector_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <8 x i32>, <8 x i32>* %in + %a = load <8 x i32>, ptr %in br label %bb1 bb1: - store <8 x i32> %a, <8 x i32>* %out + store <8 x i32> %a, ptr %out ret void } -define void @subvector_v16i32(<16 x i32> *%in, <16 x i32>* %out) #0 { +define void @subvector_v16i32(ptr %in, ptr %out) #0 { ; VBITS_GE_256-LABEL: subvector_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -115,46 +115,46 @@ define void @subvector_v16i32(<16 x i32> *%in, <16 x i32>* %out) #0 { ; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0] ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <16 x i32>, <16 x i32>* %in + %a = load <16 x i32>, ptr %in br label %bb1 bb1: - store <16 x i32> %a, <16 x i32>* %out + store <16 x i32> %a, ptr %out ret void } -define void @subvector_v32i32(<32 x i32> *%in, <32 x i32>* %out) vscale_range(8,0) #0 { +define void @subvector_v32i32(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: subvector_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x i32>, <32 x i32>* %in + %a = load <32 x i32>, ptr %in br label %bb1 bb1: - store <32 x i32> %a, <32 x i32>* %out + store <32 x i32> %a, ptr %out ret void } -define void @subvector_v64i32(<64 x i32> *%in, <64 x i32>* %out) vscale_range(16,0) #0 { +define void @subvector_v64i32(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: subvector_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <64 x i32>, <64 x i32>* %in + %a = load <64 x i32>, ptr %in br label %bb1 bb1: - store <64 x i32> %a, <64 x i32>* %out + store <64 x i32> %a, ptr %out ret void } -define void @subvector_v8i64(<8 x i64> *%in, <8 x i64>* %out) vscale_range(2,0) #0 { +define void @subvector_v8i64(ptr %in, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: subvector_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: mov x8, #4 @@ -164,74 +164,74 @@ define void @subvector_v8i64(<8 x i64> *%in, <8 x i64>* %out) vscale_range(2,0) ; CHECK-NEXT: st1d { z0.d }, p0, [x1, x8, lsl #3] ; CHECK-NEXT: st1d { z1.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <8 x i64>, <8 x i64>* %in + %a = load <8 x i64>, ptr %in br label %bb1 bb1: - store <8 x i64> %a, <8 x i64>* %out + store <8 x i64> %a, ptr %out ret void } -define void @subvector_v16i64(<16 x i64> *%in, <16 x i64>* %out) vscale_range(8,0) #0 { +define void @subvector_v16i64(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: subvector_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <16 x i64>, <16 x i64>* %in + %a = load <16 x i64>, ptr %in br label %bb1 bb1: - store <16 x i64> %a, <16 x i64>* %out + store <16 x i64> %a, ptr %out ret void } -define void @subvector_v32i64(<32 x i64> *%in, <32 x i64>* %out) vscale_range(16,0) #0 { +define void @subvector_v32i64(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: subvector_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x i64>, <32 x i64>* %in + %a = load <32 x i64>, ptr %in br label %bb1 bb1: - store <32 x i64> %a, <32 x i64>* %out + store <32 x i64> %a, ptr %out ret void } -define void @subvector_v8f16(<8 x half> *%in, <8 x half>* %out) vscale_range(2,0) #0 { +define void @subvector_v8f16(ptr %in, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: subvector_v8f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %a = load <8 x half>, <8 x half>* %in + %a = load <8 x half>, ptr %in br label %bb1 bb1: - store <8 x half> %a, <8 x half>* %out + store <8 x half> %a, ptr %out ret void } -define void @subvector_v16f16(<16 x half> *%in, <16 x half>* %out) vscale_range(2,0) #0 { +define void @subvector_v16f16(ptr %in, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: subvector_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %a = load <16 x half>, <16 x half>* %in + %a = load <16 x half>, ptr %in br label %bb1 bb1: - store <16 x half> %a, <16 x half>* %out + store <16 x half> %a, ptr %out ret void } -define void @subvector_v32f16(<32 x half> *%in, <32 x half>* %out) #0 { +define void @subvector_v32f16(ptr %in, ptr %out) #0 { ; VBITS_GE_256-LABEL: subvector_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -248,45 +248,45 @@ define void @subvector_v32f16(<32 x half> *%in, <32 x half>* %out) #0 { ; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0] ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <32 x half>, <32 x half>* %in + %a = load <32 x half>, ptr %in br label %bb1 bb1: - store <32 x half> %a, <32 x half>* %out + store <32 x half> %a, ptr %out ret void } -define void @subvector_v64f16(<64 x half> *%in, <64 x half>* %out) vscale_range(8,0) #0 { +define void @subvector_v64f16(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: subvector_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %a = load <64 x half>, <64 x half>* %in + %a = load <64 x half>, ptr %in br label %bb1 bb1: - store <64 x half> %a, <64 x half>* %out + store <64 x half> %a, ptr %out ret void } -define void @subvector_v8f32(<8 x float> *%in, <8 x float>* %out) vscale_range(2,0) #0 { +define void @subvector_v8f32(ptr %in, ptr %out) vscale_range(2,0) #0 { ; CHECK-LABEL: subvector_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <8 x float>, <8 x float>* %in + %a = load <8 x float>, ptr %in br label %bb1 bb1: - store <8 x float> %a, <8 x float>* %out + store <8 x float> %a, ptr %out ret void } -define void @subvector_v16f32(<16 x float> *%in, <16 x float>* %out) #0 { +define void @subvector_v16f32(ptr %in, ptr %out) #0 { ; VBITS_GE_256-LABEL: subvector_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -303,44 +303,44 @@ define void @subvector_v16f32(<16 x float> *%in, <16 x float>* %out) #0 { ; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0] ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <16 x float>, <16 x float>* %in + %a = load <16 x float>, ptr %in br label %bb1 bb1: - store <16 x float> %a, <16 x float>* %out + store <16 x float> %a, ptr %out ret void } -define void @subvector_v32f32(<32 x float> *%in, <32 x float>* %out) vscale_range(8,0) #0 { +define void @subvector_v32f32(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: subvector_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x float>, <32 x float>* %in + %a = load <32 x float>, ptr %in br label %bb1 bb1: - store <32 x float> %a, <32 x float>* %out + store <32 x float> %a, ptr %out ret void } -define void @subvector_v64f32(<64 x float> *%in, <64 x float>* %out) vscale_range(16,0) #0 { +define void @subvector_v64f32(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: subvector_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <64 x float>, <64 x float>* %in + %a = load <64 x float>, ptr %in br label %bb1 bb1: - store <64 x float> %a, <64 x float>* %out + store <64 x float> %a, ptr %out ret void } -define void @subvector_v8f64(<8 x double> *%in, <8 x double>* %out) #0 { +define void @subvector_v8f64(ptr %in, ptr %out) #0 { ; VBITS_GE_256-LABEL: subvector_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -357,45 +357,45 @@ define void @subvector_v8f64(<8 x double> *%in, <8 x double>* %out) #0 { ; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <8 x double>, <8 x double>* %in + %a = load <8 x double>, ptr %in br label %bb1 bb1: - store <8 x double> %a, <8 x double>* %out + store <8 x double> %a, ptr %out ret void } -define void @subvector_v16f64(<16 x double> *%in, <16 x double>* %out) vscale_range(8,0) #0 { +define void @subvector_v16f64(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: subvector_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <16 x double>, <16 x double>* %in + %a = load <16 x double>, ptr %in br label %bb1 bb1: - store <16 x double> %a, <16 x double>* %out + store <16 x double> %a, ptr %out ret void } -define void @subvector_v32f64(<32 x double> *%in, <32 x double>* %out) vscale_range(16,0) #0 { +define void @subvector_v32f64(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: subvector_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x double>, <32 x double>* %in + %a = load <32 x double>, ptr %in br label %bb1 bb1: - store <32 x double> %a, <32 x double>* %out + store <32 x double> %a, ptr %out ret void } -define <8 x i1> @no_warn_dropped_scalable(<8 x i32>* %in) #0 { +define <8 x i1> @no_warn_dropped_scalable(ptr %in) #0 { ; CHECK-LABEL: no_warn_dropped_scalable: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -406,7 +406,7 @@ define <8 x i1> @no_warn_dropped_scalable(<8 x i32>* %in) #0 { ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %a = load <8 x i32>, <8 x i32>* %in + %a = load <8 x i32>, ptr %in br label %bb1 bb1: @@ -418,7 +418,7 @@ bb1: ; combines remove redundant subvector operations. This test ensures it's not ; performed when the input idiom is the result of operation legalisation. When ; not prevented the test triggers infinite combine->legalise->combine->... -define void @no_subvector_binop_hang(<8 x i32>* %in, <8 x i32>* %out, i1 %cond) #0 { +define void @no_subvector_binop_hang(ptr %in, ptr %out, i1 %cond) #0 { ; CHECK-LABEL: no_subvector_binop_hang: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -430,13 +430,13 @@ define void @no_subvector_binop_hang(<8 x i32>* %in, <8 x i32>* %out, i1 %cond) ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: .LBB23_2: // %bb.2 ; CHECK-NEXT: ret - %a = load <8 x i32>, <8 x i32>* %in - %b = load <8 x i32>, <8 x i32>* %out + %a = load <8 x i32>, ptr %in + %b = load <8 x i32>, ptr %out br i1 %cond, label %bb.1, label %bb.2 bb.1: %or = or <8 x i32> %a, %b - store <8 x i32> %or, <8 x i32>* %out + store <8 x i32> %or, ptr %out br label %bb.2 bb.2: diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll index 9b56968..6f7220a 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll @@ -5,33 +5,33 @@ target triple = "aarch64-unknown-linux-gnu" -define void @store_trunc_v2i64i8(<2 x i64>* %ap, <2 x i8>* %dest) vscale_range(2,0) #0 { +define void @store_trunc_v2i64i8(ptr %ap, ptr %dest) vscale_range(2,0) #0 { ; CHECK-LABEL: store_trunc_v2i64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ptrue p0.d, vl2 ; CHECK-NEXT: st1b { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <2 x i64>, <2 x i64>* %ap + %a = load <2 x i64>, ptr %ap %val = trunc <2 x i64> %a to <2 x i8> - store <2 x i8> %val, <2 x i8>* %dest + store <2 x i8> %val, ptr %dest ret void } -define void @store_trunc_v4i64i8(<4 x i64>* %ap, <4 x i8>* %dest) vscale_range(2,0) #0 { +define void @store_trunc_v4i64i8(ptr %ap, ptr %dest) vscale_range(2,0) #0 { ; CHECK-LABEL: store_trunc_v4i64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: st1b { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <4 x i64>, <4 x i64>* %ap + %a = load <4 x i64>, ptr %ap %val = trunc <4 x i64> %a to <4 x i8> - store <4 x i8> %val, <4 x i8>* %dest + store <4 x i8> %val, ptr %dest ret void } -define void @store_trunc_v8i64i8(<8 x i64>* %ap, <8 x i8>* %dest) #0 { +define void @store_trunc_v8i64i8(ptr %ap, ptr %dest) #0 { ; VBITS_GE_256-LABEL: store_trunc_v8i64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -52,39 +52,39 @@ define void @store_trunc_v8i64i8(<8 x i64>* %ap, <8 x i8>* %dest) #0 { ; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0] ; VBITS_GE_512-NEXT: st1b { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <8 x i64>, <8 x i64>* %ap + %a = load <8 x i64>, ptr %ap %val = trunc <8 x i64> %a to <8 x i8> - store <8 x i8> %val, <8 x i8>* %dest + store <8 x i8> %val, ptr %dest ret void } -define void @store_trunc_v16i64i8(<16 x i64>* %ap, <16 x i8>* %dest) vscale_range(8,0) #0 { +define void @store_trunc_v16i64i8(ptr %ap, ptr %dest) vscale_range(8,0) #0 { ; CHECK-LABEL: store_trunc_v16i64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: st1b { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <16 x i64>, <16 x i64>* %ap + %a = load <16 x i64>, ptr %ap %val = trunc <16 x i64> %a to <16 x i8> - store <16 x i8> %val, <16 x i8>* %dest + store <16 x i8> %val, ptr %dest ret void } -define void @store_trunc_v32i64i8(<32 x i64>* %ap, <32 x i8>* %dest) vscale_range(16,0) #0 { +define void @store_trunc_v32i64i8(ptr %ap, ptr %dest) vscale_range(16,0) #0 { ; CHECK-LABEL: store_trunc_v32i64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: st1b { z0.d }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x i64>, <32 x i64>* %ap + %a = load <32 x i64>, ptr %ap %val = trunc <32 x i64> %a to <32 x i8> - store <32 x i8> %val, <32 x i8>* %dest + store <32 x i8> %val, ptr %dest ret void } -define void @store_trunc_v8i64i16(<8 x i64>* %ap, <8 x i16>* %dest) #0 { +define void @store_trunc_v8i64i16(ptr %ap, ptr %dest) #0 { ; Currently does not use the truncating store ; VBITS_GE_256-LABEL: store_trunc_v8i64i16: ; VBITS_GE_256: // %bb.0: @@ -106,13 +106,13 @@ define void @store_trunc_v8i64i16(<8 x i64>* %ap, <8 x i16>* %dest) #0 { ; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0] ; VBITS_GE_512-NEXT: st1h { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <8 x i64>, <8 x i64>* %ap + %a = load <8 x i64>, ptr %ap %val = trunc <8 x i64> %a to <8 x i16> - store <8 x i16> %val, <8 x i16>* %dest + store <8 x i16> %val, ptr %dest ret void } -define void @store_trunc_v8i64i32(<8 x i64>* %ap, <8 x i32>* %dest) #0 { +define void @store_trunc_v8i64i32(ptr %ap, ptr %dest) #0 { ; VBITS_GE_256-LABEL: store_trunc_v8i64i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -133,13 +133,13 @@ define void @store_trunc_v8i64i32(<8 x i64>* %ap, <8 x i32>* %dest) #0 { ; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0] ; VBITS_GE_512-NEXT: st1w { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <8 x i64>, <8 x i64>* %ap + %a = load <8 x i64>, ptr %ap %val = trunc <8 x i64> %a to <8 x i32> - store <8 x i32> %val, <8 x i32>* %dest + store <8 x i32> %val, ptr %dest ret void } -define void @store_trunc_v16i32i8(<16 x i32>* %ap, <16 x i8>* %dest) #0 { +define void @store_trunc_v16i32i8(ptr %ap, ptr %dest) #0 { ; Currently does not use the truncating store ; VBITS_GE_256-LABEL: store_trunc_v16i32i8: ; VBITS_GE_256: // %bb.0: @@ -161,13 +161,13 @@ define void @store_trunc_v16i32i8(<16 x i32>* %ap, <16 x i8>* %dest) #0 { ; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0] ; VBITS_GE_512-NEXT: st1b { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <16 x i32>, <16 x i32>* %ap + %a = load <16 x i32>, ptr %ap %val = trunc <16 x i32> %a to <16 x i8> - store <16 x i8> %val, <16 x i8>* %dest + store <16 x i8> %val, ptr %dest ret void } -define void @store_trunc_v16i32i16(<16 x i32>* %ap, <16 x i16>* %dest) #0 { +define void @store_trunc_v16i32i16(ptr %ap, ptr %dest) #0 { ; VBITS_GE_256-LABEL: store_trunc_v16i32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -188,13 +188,13 @@ define void @store_trunc_v16i32i16(<16 x i32>* %ap, <16 x i16>* %dest) #0 { ; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0] ; VBITS_GE_512-NEXT: st1h { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <16 x i32>, <16 x i32>* %ap + %a = load <16 x i32>, ptr %ap %val = trunc <16 x i32> %a to <16 x i16> - store <16 x i16> %val, <16 x i16>* %dest + store <16 x i16> %val, ptr %dest ret void } -define void @store_trunc_v32i16i8(<32 x i16>* %ap, <32 x i8>* %dest) #0 { +define void @store_trunc_v32i16i8(ptr %ap, ptr %dest) #0 { ; VBITS_GE_256-LABEL: store_trunc_v32i16i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -215,9 +215,9 @@ define void @store_trunc_v32i16i8(<32 x i16>* %ap, <32 x i8>* %dest) #0 { ; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0] ; VBITS_GE_512-NEXT: st1b { z0.h }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <32 x i16>, <32 x i16>* %ap + %a = load <32 x i16>, ptr %ap %val = trunc <32 x i16> %a to <32 x i8> - store <32 x i8> %val, <32 x i8>* %dest + store <32 x i8> %val, ptr %dest ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-trunc.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-trunc.ll index 8850bd4..c94d07d 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-trunc.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-trunc.ll @@ -9,7 +9,7 @@ target triple = "aarch64-unknown-linux-gnu" ; truncate i16 -> i8 ; -define <16 x i8> @trunc_v16i16_v16i8(<16 x i16>* %in) vscale_range(2,0) #0 { +define <16 x i8> @trunc_v16i16_v16i8(ptr %in) vscale_range(2,0) #0 { ; CHECK-LABEL: trunc_v16i16_v16i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -17,13 +17,13 @@ define <16 x i8> @trunc_v16i16_v16i8(<16 x i16>* %in) vscale_range(2,0) #0 { ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret - %a = load <16 x i16>, <16 x i16>* %in + %a = load <16 x i16>, ptr %in %b = trunc <16 x i16> %a to <16 x i8> ret <16 x i8> %b } ; NOTE: Extra 'add' is to prevent the truncate being combined with the store. -define void @trunc_v32i16_v32i8(<32 x i16>* %in, <32 x i8>* %out) #0 { +define void @trunc_v32i16_v32i8(ptr %in, ptr %out) #0 { ; VBITS_GE_256-LABEL: trunc_v32i16_v32i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -48,15 +48,15 @@ define void @trunc_v32i16_v32i8(<32 x i16>* %in, <32 x i8>* %out) #0 { ; VBITS_GE_512-NEXT: add z0.b, z0.b, z0.b ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <32 x i16>, <32 x i16>* %in + %a = load <32 x i16>, ptr %in %b = trunc <32 x i16> %a to <32 x i8> %c = add <32 x i8> %b, %b - store <32 x i8> %c, <32 x i8>* %out + store <32 x i8> %c, ptr %out ret void } ; NOTE: Extra 'add' is to prevent the truncate being combined with the store. -define void @trunc_v64i16_v64i8(<64 x i16>* %in, <64 x i8>* %out) vscale_range(8,0) #0 { +define void @trunc_v64i16_v64i8(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: trunc_v64i16_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -66,15 +66,15 @@ define void @trunc_v64i16_v64i8(<64 x i16>* %in, <64 x i8>* %out) vscale_range(8 ; CHECK-NEXT: add z0.b, z0.b, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x1] ; CHECK-NEXT: ret - %a = load <64 x i16>, <64 x i16>* %in + %a = load <64 x i16>, ptr %in %b = trunc <64 x i16> %a to <64 x i8> %c = add <64 x i8> %b, %b - store <64 x i8> %c, <64 x i8>* %out + store <64 x i8> %c, ptr %out ret void } ; NOTE: Extra 'add' is to prevent the truncate being combined with the store. -define void @trunc_v128i16_v128i8(<128 x i16>* %in, <128 x i8>* %out) vscale_range(16,0) #0 { +define void @trunc_v128i16_v128i8(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: trunc_v128i16_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -84,10 +84,10 @@ define void @trunc_v128i16_v128i8(<128 x i16>* %in, <128 x i8>* %out) vscale_ran ; CHECK-NEXT: add z0.b, z0.b, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x1] ; CHECK-NEXT: ret - %a = load <128 x i16>, <128 x i16>* %in + %a = load <128 x i16>, ptr %in %b = trunc <128 x i16> %a to <128 x i8> %c = add <128 x i8> %b, %b - store <128 x i8> %c, <128 x i8>* %out + store <128 x i8> %c, ptr %out ret void } @@ -95,7 +95,7 @@ define void @trunc_v128i16_v128i8(<128 x i16>* %in, <128 x i8>* %out) vscale_ran ; truncate i32 -> i8 ; -define <8 x i8> @trunc_v8i32_v8i8(<8 x i32>* %in) vscale_range(2,0) #0 { +define <8 x i8> @trunc_v8i32_v8i8(ptr %in) vscale_range(2,0) #0 { ; CHECK-LABEL: trunc_v8i32_v8i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -104,12 +104,12 @@ define <8 x i8> @trunc_v8i32_v8i8(<8 x i32>* %in) vscale_range(2,0) #0 { ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %a = load <8 x i32>, <8 x i32>* %in + %a = load <8 x i32>, ptr %in %b = trunc <8 x i32> %a to <8 x i8> ret <8 x i8> %b } -define <16 x i8> @trunc_v16i32_v16i8(<16 x i32>* %in) #0 { +define <16 x i8> @trunc_v16i32_v16i8(ptr %in) #0 { ; VBITS_GE_256-LABEL: trunc_v16i32_v16i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -132,13 +132,13 @@ define <16 x i8> @trunc_v16i32_v16i8(<16 x i32>* %in) #0 { ; VBITS_GE_512-NEXT: uzp1 z0.b, z0.b, z0.b ; VBITS_GE_512-NEXT: // kill: def $q0 killed $q0 killed $z0 ; VBITS_GE_512-NEXT: ret - %a = load <16 x i32>, <16 x i32>* %in + %a = load <16 x i32>, ptr %in %b = trunc <16 x i32> %a to <16 x i8> ret <16 x i8> %b } ; NOTE: Extra 'add' is to prevent the truncate being combined with the store. -define void @trunc_v32i32_v32i8(<32 x i32>* %in, <32 x i8>* %out) vscale_range(8,0) #0 { +define void @trunc_v32i32_v32i8(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: trunc_v32i32_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -149,15 +149,15 @@ define void @trunc_v32i32_v32i8(<32 x i32>* %in, <32 x i8>* %out) vscale_range(8 ; CHECK-NEXT: add z0.b, z0.b, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x i32>, <32 x i32>* %in + %a = load <32 x i32>, ptr %in %b = trunc <32 x i32> %a to <32 x i8> %c = add <32 x i8> %b, %b - store <32 x i8> %c, <32 x i8>* %out + store <32 x i8> %c, ptr %out ret void } ; NOTE: Extra 'add' is to prevent the truncate being combined with the store. -define void @trunc_v64i32_v64i8(<64 x i32>* %in, <64 x i8>* %out) vscale_range(16,0) #0 { +define void @trunc_v64i32_v64i8(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: trunc_v64i32_v64i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -168,10 +168,10 @@ define void @trunc_v64i32_v64i8(<64 x i32>* %in, <64 x i8>* %out) vscale_range(1 ; CHECK-NEXT: add z0.b, z0.b, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x1] ; CHECK-NEXT: ret - %a = load <64 x i32>, <64 x i32>* %in + %a = load <64 x i32>, ptr %in %b = trunc <64 x i32> %a to <64 x i8> %c = add <64 x i8> %b, %b - store <64 x i8> %c, <64 x i8>* %out + store <64 x i8> %c, ptr %out ret void } @@ -179,7 +179,7 @@ define void @trunc_v64i32_v64i8(<64 x i32>* %in, <64 x i8>* %out) vscale_range(1 ; truncate i32 -> i16 ; -define <8 x i16> @trunc_v8i32_v8i16(<8 x i32>* %in) vscale_range(2,0) #0 { +define <8 x i16> @trunc_v8i32_v8i16(ptr %in) vscale_range(2,0) #0 { ; CHECK-LABEL: trunc_v8i32_v8i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -187,13 +187,13 @@ define <8 x i16> @trunc_v8i32_v8i16(<8 x i32>* %in) vscale_range(2,0) #0 { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret - %a = load <8 x i32>, <8 x i32>* %in + %a = load <8 x i32>, ptr %in %b = trunc <8 x i32> %a to <8 x i16> ret <8 x i16> %b } ; NOTE: Extra 'add' is to prevent the truncate being combined with the store. -define void @trunc_v16i32_v16i16(<16 x i32>* %in, <16 x i16>* %out) #0 { +define void @trunc_v16i32_v16i16(ptr %in, ptr %out) #0 { ; VBITS_GE_256-LABEL: trunc_v16i32_v16i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -218,15 +218,15 @@ define void @trunc_v16i32_v16i16(<16 x i32>* %in, <16 x i16>* %out) #0 { ; VBITS_GE_512-NEXT: add z0.h, z0.h, z0.h ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <16 x i32>, <16 x i32>* %in + %a = load <16 x i32>, ptr %in %b = trunc <16 x i32> %a to <16 x i16> %c = add <16 x i16> %b, %b - store <16 x i16> %c, <16 x i16>* %out + store <16 x i16> %c, ptr %out ret void } ; NOTE: Extra 'add' is to prevent the truncate being combined with the store. -define void @trunc_v32i32_v32i16(<32 x i32>* %in, <32 x i16>* %out) vscale_range(8,0) #0 { +define void @trunc_v32i32_v32i16(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: trunc_v32i32_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -236,15 +236,15 @@ define void @trunc_v32i32_v32i16(<32 x i32>* %in, <32 x i16>* %out) vscale_range ; CHECK-NEXT: add z0.h, z0.h, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x i32>, <32 x i32>* %in + %a = load <32 x i32>, ptr %in %b = trunc <32 x i32> %a to <32 x i16> %c = add <32 x i16> %b, %b - store <32 x i16> %c, <32 x i16>* %out + store <32 x i16> %c, ptr %out ret void } ; NOTE: Extra 'add' is to prevent the truncate being combined with the store. -define void @trunc_v64i32_v64i16(<64 x i32>* %in, <64 x i16>* %out) vscale_range(16,0) #0 { +define void @trunc_v64i32_v64i16(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: trunc_v64i32_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -254,10 +254,10 @@ define void @trunc_v64i32_v64i16(<64 x i32>* %in, <64 x i16>* %out) vscale_range ; CHECK-NEXT: add z0.h, z0.h, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %a = load <64 x i32>, <64 x i32>* %in + %a = load <64 x i32>, ptr %in %b = trunc <64 x i32> %a to <64 x i16> %c = add <64 x i16> %b, %b - store <64 x i16> %c, <64 x i16>* %out + store <64 x i16> %c, ptr %out ret void } @@ -266,7 +266,7 @@ define void @trunc_v64i32_v64i16(<64 x i32>* %in, <64 x i16>* %out) vscale_range ; ; NOTE: v4i8 is not legal so result i8 elements are held within i16 containers. -define <4 x i8> @trunc_v4i64_v4i8(<4 x i64>* %in) vscale_range(2,0) #0 { +define <4 x i8> @trunc_v4i64_v4i8(ptr %in) vscale_range(2,0) #0 { ; CHECK-LABEL: trunc_v4i64_v4i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -275,12 +275,12 @@ define <4 x i8> @trunc_v4i64_v4i8(<4 x i64>* %in) vscale_range(2,0) #0 { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %a = load <4 x i64>, <4 x i64>* %in + %a = load <4 x i64>, ptr %in %b = trunc <4 x i64> %a to <4 x i8> ret <4 x i8> %b } -define <8 x i8> @trunc_v8i64_v8i8(<8 x i64>* %in) #0 { +define <8 x i8> @trunc_v8i64_v8i8(ptr %in) #0 { ; VBITS_GE_256-LABEL: trunc_v8i64_v8i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -305,12 +305,12 @@ define <8 x i8> @trunc_v8i64_v8i8(<8 x i64>* %in) #0 { ; VBITS_GE_512-NEXT: uzp1 z0.b, z0.b, z0.b ; VBITS_GE_512-NEXT: // kill: def $d0 killed $d0 killed $z0 ; VBITS_GE_512-NEXT: ret - %a = load <8 x i64>, <8 x i64>* %in + %a = load <8 x i64>, ptr %in %b = trunc <8 x i64> %a to <8 x i8> ret <8 x i8> %b } -define <16 x i8> @trunc_v16i64_v16i8(<16 x i64>* %in) vscale_range(8,0) #0 { +define <16 x i8> @trunc_v16i64_v16i8(ptr %in) vscale_range(8,0) #0 { ; CHECK-LABEL: trunc_v16i64_v16i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -320,13 +320,13 @@ define <16 x i8> @trunc_v16i64_v16i8(<16 x i64>* %in) vscale_range(8,0) #0 { ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret - %a = load <16 x i64>, <16 x i64>* %in + %a = load <16 x i64>, ptr %in %b = trunc <16 x i64> %a to <16 x i8> ret <16 x i8> %b } ; NOTE: Extra 'add' is to prevent the truncate being combined with the store. -define void @trunc_v32i64_v32i8(<32 x i64>* %in, <32 x i8>* %out) vscale_range(16,0) #0 { +define void @trunc_v32i64_v32i8(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: trunc_v32i64_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -338,10 +338,10 @@ define void @trunc_v32i64_v32i8(<32 x i64>* %in, <32 x i8>* %out) vscale_range(1 ; CHECK-NEXT: add z0.b, z0.b, z0.b ; CHECK-NEXT: st1b { z0.b }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x i64>, <32 x i64>* %in + %a = load <32 x i64>, ptr %in %b = trunc <32 x i64> %a to <32 x i8> %c = add <32 x i8> %b, %b - store <32 x i8> %c, <32 x i8>* %out + store <32 x i8> %c, ptr %out ret void } @@ -349,7 +349,7 @@ define void @trunc_v32i64_v32i8(<32 x i64>* %in, <32 x i8>* %out) vscale_range(1 ; truncate i64 -> i16 ; -define <4 x i16> @trunc_v4i64_v4i16(<4 x i64>* %in) vscale_range(2,0) #0 { +define <4 x i16> @trunc_v4i64_v4i16(ptr %in) vscale_range(2,0) #0 { ; CHECK-LABEL: trunc_v4i64_v4i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -358,12 +358,12 @@ define <4 x i16> @trunc_v4i64_v4i16(<4 x i64>* %in) vscale_range(2,0) #0 { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret - %a = load <4 x i64>, <4 x i64>* %in + %a = load <4 x i64>, ptr %in %b = trunc <4 x i64> %a to <4 x i16> ret <4 x i16> %b } -define <8 x i16> @trunc_v8i64_v8i16(<8 x i64>* %in) #0 { +define <8 x i16> @trunc_v8i64_v8i16(ptr %in) #0 { ; VBITS_GE_256-LABEL: trunc_v8i64_v8i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -386,13 +386,13 @@ define <8 x i16> @trunc_v8i64_v8i16(<8 x i64>* %in) #0 { ; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h ; VBITS_GE_512-NEXT: // kill: def $q0 killed $q0 killed $z0 ; VBITS_GE_512-NEXT: ret - %a = load <8 x i64>, <8 x i64>* %in + %a = load <8 x i64>, ptr %in %b = trunc <8 x i64> %a to <8 x i16> ret <8 x i16> %b } ; NOTE: Extra 'add' is to prevent the truncate being combined with the store. -define void @trunc_v16i64_v16i16(<16 x i64>* %in, <16 x i16>* %out) vscale_range(8,0) #0 { +define void @trunc_v16i64_v16i16(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: trunc_v16i64_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -403,15 +403,15 @@ define void @trunc_v16i64_v16i16(<16 x i64>* %in, <16 x i16>* %out) vscale_range ; CHECK-NEXT: add z0.h, z0.h, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %a = load <16 x i64>, <16 x i64>* %in + %a = load <16 x i64>, ptr %in %b = trunc <16 x i64> %a to <16 x i16> %c = add <16 x i16> %b, %b - store <16 x i16> %c, <16 x i16>* %out + store <16 x i16> %c, ptr %out ret void } ; NOTE: Extra 'add' is to prevent the truncate being combined with the store. -define void @trunc_v32i64_v32i16(<32 x i64>* %in, <32 x i16>* %out) vscale_range(16,0) #0 { +define void @trunc_v32i64_v32i16(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: trunc_v32i64_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -422,10 +422,10 @@ define void @trunc_v32i64_v32i16(<32 x i64>* %in, <32 x i16>* %out) vscale_range ; CHECK-NEXT: add z0.h, z0.h, z0.h ; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x i64>, <32 x i64>* %in + %a = load <32 x i64>, ptr %in %b = trunc <32 x i64> %a to <32 x i16> %c = add <32 x i16> %b, %b - store <32 x i16> %c, <32 x i16>* %out + store <32 x i16> %c, ptr %out ret void } @@ -433,7 +433,7 @@ define void @trunc_v32i64_v32i16(<32 x i64>* %in, <32 x i16>* %out) vscale_range ; truncate i64 -> i32 ; -define <4 x i32> @trunc_v4i64_v4i32(<4 x i64>* %in) vscale_range(2,0) #0 { +define <4 x i32> @trunc_v4i64_v4i32(ptr %in) vscale_range(2,0) #0 { ; CHECK-LABEL: trunc_v4i64_v4i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -441,13 +441,13 @@ define <4 x i32> @trunc_v4i64_v4i32(<4 x i64>* %in) vscale_range(2,0) #0 { ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret - %a = load <4 x i64>, <4 x i64>* %in + %a = load <4 x i64>, ptr %in %b = trunc <4 x i64> %a to <4 x i32> ret <4 x i32> %b } ; NOTE: Extra 'add' is to prevent the truncate being combined with the store. -define void @trunc_v8i64_v8i32(<8 x i64>* %in, <8 x i32>* %out) #0 { +define void @trunc_v8i64_v8i32(ptr %in, ptr %out) #0 { ; VBITS_GE_256-LABEL: trunc_v8i64_v8i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -472,15 +472,15 @@ define void @trunc_v8i64_v8i32(<8 x i64>* %in, <8 x i32>* %out) #0 { ; VBITS_GE_512-NEXT: add z0.s, z0.s, z0.s ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: ret - %a = load <8 x i64>, <8 x i64>* %in + %a = load <8 x i64>, ptr %in %b = trunc <8 x i64> %a to <8 x i32> %c = add <8 x i32> %b, %b - store <8 x i32> %c, <8 x i32>* %out + store <8 x i32> %c, ptr %out ret void } ; NOTE: Extra 'add' is to prevent the truncate being combined with the store. -define void @trunc_v16i64_v16i32(<16 x i64>* %in, <16 x i32>* %out) vscale_range(8,0) #0 { +define void @trunc_v16i64_v16i32(ptr %in, ptr %out) vscale_range(8,0) #0 { ; CHECK-LABEL: trunc_v16i64_v16i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -490,15 +490,15 @@ define void @trunc_v16i64_v16i32(<16 x i64>* %in, <16 x i32>* %out) vscale_range ; CHECK-NEXT: add z0.s, z0.s, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <16 x i64>, <16 x i64>* %in + %a = load <16 x i64>, ptr %in %b = trunc <16 x i64> %a to <16 x i32> %c = add <16 x i32> %b, %b - store <16 x i32> %c, <16 x i32>* %out + store <16 x i32> %c, ptr %out ret void } ; NOTE: Extra 'add' is to prevent the truncate being combined with the store. -define void @trunc_v32i64_v32i32(<32 x i64>* %in, <32 x i32>* %out) vscale_range(16,0) #0 { +define void @trunc_v32i64_v32i32(ptr %in, ptr %out) vscale_range(16,0) #0 { ; CHECK-LABEL: trunc_v32i64_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -508,10 +508,10 @@ define void @trunc_v32i64_v32i32(<32 x i64>* %in, <32 x i32>* %out) vscale_range ; CHECK-NEXT: add z0.s, z0.s, z0.s ; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: ret - %a = load <32 x i64>, <32 x i64>* %in + %a = load <32 x i64>, ptr %in %b = trunc <32 x i64> %a to <32 x i32> %c = add <32 x i32> %b, %b - store <32 x i32> %c, <32 x i32>* %out + store <32 x i32> %c, ptr %out ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll index fff1e50..3df909f 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll @@ -26,7 +26,7 @@ define <16 x i8> @shuffle_ext_byone_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale ret <16 x i8> %ret } -define void @shuffle_ext_byone_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range(2,0) #0 { +define void @shuffle_ext_byone_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl32 @@ -37,17 +37,17 @@ define void @shuffle_ext_byone_v32i8(<32 x i8>* %a, <32 x i8>* %b) vscale_range( ; CHECK-NEXT: insr z1.b, w8 ; CHECK-NEXT: st1b { z1.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, <32 x i8>* %a - %op2 = load <32 x i8>, <32 x i8>* %b + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b %ret = shufflevector <32 x i8> %op1, <32 x i8> %op2, <32 x i32> - store <32 x i8> %ret, <32 x i8>* %a + store <32 x i8> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { +define void @shuffle_ext_byone_v64i8(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: shuffle_ext_byone_v64i8: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov w8, #32 @@ -75,8 +75,8 @@ define void @shuffle_ext_byone_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { ; VBITS_GE_512-NEXT: insr z1.b, w8 ; VBITS_GE_512-NEXT: st1b { z1.b }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <64 x i8>, <64 x i8>* %a - %op2 = load <64 x i8>, <64 x i8>* %b + %op1 = load <64 x i8>, ptr %a + %op2 = load <64 x i8>, ptr %b %ret = shufflevector <64 x i8> %op1, <64 x i8> %op2, <64 x i32> * %a, <64 x i8>* %b) #0 { i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126> - store <64 x i8> %ret, <64 x i8>* %a + store <64 x i8> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_range(8,0) #0 { +define void @shuffle_ext_byone_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v128i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl128 @@ -101,8 +101,8 @@ define void @shuffle_ext_byone_v128i8(<128 x i8>* %a, <128 x i8>* %b) vscale_ran ; CHECK-NEXT: insr z1.b, w8 ; CHECK-NEXT: st1b { z1.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i8>, <128 x i8>* %a - %op2 = load <128 x i8>, <128 x i8>* %b + %op1 = load <128 x i8>, ptr %a + %op2 = load <128 x i8>, ptr %b %ret = shufflevector <128 x i8> %op1, <128 x i8> %op2, <128 x i32> * %a, <128 x i8>* %b) vscale_ran i32 231, i32 232, i32 233, i32 234, i32 235, i32 236, i32 237, i32 238, i32 239, i32 240, i32 241, i32 242, i32 243, i32 244, i32 245, i32 246, i32 247, i32 248, i32 249, i32 250, i32 251, i32 252, i32 253, i32 254> - store <128 x i8> %ret, <128 x i8>* %a + store <128 x i8> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_range(16,0) #0 { +define void @shuffle_ext_byone_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v256i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b, vl256 @@ -135,8 +135,8 @@ define void @shuffle_ext_byone_v256i8(<256 x i8>* %a, <256 x i8>* %b) vscale_ran ; CHECK-NEXT: insr z1.b, w8 ; CHECK-NEXT: st1b { z1.b }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <256 x i8>, <256 x i8>* %a - %op2 = load <256 x i8>, <256 x i8>* %b + %op1 = load <256 x i8>, ptr %a + %op2 = load <256 x i8>, ptr %b %ret = shufflevector <256 x i8> %op1, <256 x i8> %op2, <256 x i32> * %a, <256 x i8>* %b) vscale_ran i32 487, i32 488, i32 489, i32 490, i32 491, i32 492, i32 493, i32 494, i32 495, i32 496, i32 497, i32 498, i32 499, i32 500, i32 501, i32 502, i32 503, i32 504, i32 505, i32 506, i32 507, i32 508, i32 509, i32 510> - store <256 x i8> %ret, <256 x i8>* %a + store <256 x i8> %ret, ptr %a ret void } @@ -193,7 +193,7 @@ define <8 x i16> @shuffle_ext_byone_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale ret <8 x i16> %ret } -define void @shuffle_ext_byone_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_range(2,0) #0 { +define void @shuffle_ext_byone_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -204,15 +204,15 @@ define void @shuffle_ext_byone_v16i16(<16 x i16>* %a, <16 x i16>* %b) vscale_ran ; CHECK-NEXT: insr z1.h, w8 ; CHECK-NEXT: st1h { z1.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, <16 x i16>* %a - %op2 = load <16 x i16>, <16 x i16>* %b + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b %ret = shufflevector <16 x i16> %op1, <16 x i16> %op2, <16 x i32> - store <16 x i16> %ret, <16 x i16>* %a + store <16 x i16> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +define void @shuffle_ext_byone_v32i16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: shuffle_ext_byone_v32i16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -240,17 +240,17 @@ define void @shuffle_ext_byone_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; VBITS_GE_512-NEXT: insr z1.h, w8 ; VBITS_GE_512-NEXT: st1h { z1.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x i16>, <32 x i16>* %a - %op2 = load <32 x i16>, <32 x i16>* %b + %op1 = load <32 x i16>, ptr %a + %op2 = load <32 x i16>, ptr %b %ret = shufflevector <32 x i16> %op1, <32 x i16> %op2, <32 x i32> - store <32 x i16> %ret, <32 x i16>* %a + store <32 x i16> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_range(8,0) #0 { +define void @shuffle_ext_byone_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v64i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -262,8 +262,8 @@ define void @shuffle_ext_byone_v64i16(<64 x i16>* %a, <64 x i16>* %b) vscale_ran ; CHECK-NEXT: insr z1.h, w8 ; CHECK-NEXT: st1h { z1.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i16>, <64 x i16>* %a - %op2 = load <64 x i16>, <64 x i16>* %b + %op1 = load <64 x i16>, ptr %a + %op2 = load <64 x i16>, ptr %b %ret = shufflevector <64 x i16> %op1, <64 x i16> %op2, <64 x i32> * %a, <64 x i16>* %b) vscale_ran i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126> - store <64 x i16> %ret, <64 x i16>* %a + store <64 x i16> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_range(16,0) #0 { +define void @shuffle_ext_byone_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v128i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -288,8 +288,8 @@ define void @shuffle_ext_byone_v128i16(<128 x i16>* %a, <128 x i16>* %b) vscale_ ; CHECK-NEXT: insr z1.h, w8 ; CHECK-NEXT: st1h { z1.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x i16>, <128 x i16>* %a - %op2 = load <128 x i16>, <128 x i16>* %b + %op1 = load <128 x i16>, ptr %a + %op2 = load <128 x i16>, ptr %b %ret = shufflevector <128 x i16> %op1, <128 x i16> %op2, <128 x i32> * %a, <128 x i16>* %b) vscale_ i32 231, i32 232, i32 233, i32 234, i32 235, i32 236, i32 237, i32 238, i32 239, i32 240, i32 241, i32 242, i32 243, i32 244, i32 245, i32 246, i32 247, i32 248, i32 249, i32 250, i32 251, i32 252, i32 253, i32 254> - store <128 x i16> %ret, <128 x i16>* %a + store <128 x i16> %ret, ptr %a ret void } @@ -330,7 +330,7 @@ define <4 x i32> @shuffle_ext_byone_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale ret <4 x i32> %ret } -define void @shuffle_ext_byone_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range(2,0) #0 { +define void @shuffle_ext_byone_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -341,14 +341,14 @@ define void @shuffle_ext_byone_v8i32(<8 x i32>* %a, <8 x i32>* %b) vscale_range( ; CHECK-NEXT: insr z1.s, w8 ; CHECK-NEXT: st1w { z1.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, <8 x i32>* %a - %op2 = load <8 x i32>, <8 x i32>* %b + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b %ret = shufflevector <8 x i32> %op1, <8 x i32> %op2, <8 x i32> - store <8 x i32> %ret, <8 x i32>* %a + store <8 x i32> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { +define void @shuffle_ext_byone_v16i32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: shuffle_ext_byone_v16i32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -376,15 +376,15 @@ define void @shuffle_ext_byone_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { ; VBITS_GE_512-NEXT: insr z1.s, w8 ; VBITS_GE_512-NEXT: st1w { z1.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x i32>, <16 x i32>* %a - %op2 = load <16 x i32>, <16 x i32>* %b + %op1 = load <16 x i32>, ptr %a + %op2 = load <16 x i32>, ptr %b %ret = shufflevector <16 x i32> %op1, <16 x i32> %op2, <16 x i32> - store <16 x i32> %ret, <16 x i32>* %a + store <16 x i32> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_range(8,0) #0 { +define void @shuffle_ext_byone_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v32i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -396,17 +396,17 @@ define void @shuffle_ext_byone_v32i32(<32 x i32>* %a, <32 x i32>* %b) vscale_ran ; CHECK-NEXT: insr z1.s, w8 ; CHECK-NEXT: st1w { z1.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i32>, <32 x i32>* %a - %op2 = load <32 x i32>, <32 x i32>* %b + %op1 = load <32 x i32>, ptr %a + %op2 = load <32 x i32>, ptr %b %ret = shufflevector <32 x i32> %op1, <32 x i32> %op2, <32 x i32> - store <32 x i32> %ret, <32 x i32>* %a + store <32 x i32> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_range(16,0) #0 { +define void @shuffle_ext_byone_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v64i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -418,8 +418,8 @@ define void @shuffle_ext_byone_v64i32(<64 x i32>* %a, <64 x i32>* %b) vscale_ran ; CHECK-NEXT: insr z1.s, w8 ; CHECK-NEXT: st1w { z1.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x i32>, <64 x i32>* %a - %op2 = load <64 x i32>, <64 x i32>* %b + %op1 = load <64 x i32>, ptr %a + %op2 = load <64 x i32>, ptr %b %ret = shufflevector <64 x i32> %op1, <64 x i32> %op2, <64 x i32> * %a, <64 x i32>* %b) vscale_ran i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126> - store <64 x i32> %ret, <64 x i32>* %a + store <64 x i32> %ret, ptr %a ret void } @@ -442,7 +442,7 @@ define <2 x i64> @shuffle_ext_byone_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale ret <2 x i64> %ret } -define void @shuffle_ext_byone_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { +define void @shuffle_ext_byone_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -453,14 +453,14 @@ define void @shuffle_ext_byone_v4i64(<4 x i64>* %a, <4 x i64>* %b) vscale_range( ; CHECK-NEXT: insr z1.d, x8 ; CHECK-NEXT: st1d { z1.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, <4 x i64>* %a - %op2 = load <4 x i64>, <4 x i64>* %b + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b %ret = shufflevector <4 x i64> %op1, <4 x i64> %op2, <4 x i32> - store <4 x i64> %ret, <4 x i64>* %a + store <4 x i64> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { +define void @shuffle_ext_byone_v8i64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: shuffle_ext_byone_v8i64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -488,14 +488,14 @@ define void @shuffle_ext_byone_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { ; VBITS_GE_512-NEXT: insr z1.d, x8 ; VBITS_GE_512-NEXT: st1d { z1.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x i64>, <8 x i64>* %a - %op2 = load <8 x i64>, <8 x i64>* %b + %op1 = load <8 x i64>, ptr %a + %op2 = load <8 x i64>, ptr %b %ret = shufflevector <8 x i64> %op1, <8 x i64> %op2, <8 x i32> - store <8 x i64> %ret, <8 x i64>* %a + store <8 x i64> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { +define void @shuffle_ext_byone_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -507,15 +507,15 @@ define void @shuffle_ext_byone_v16i64(<16 x i64>* %a, <16 x i64>* %b) vscale_ran ; CHECK-NEXT: insr z1.d, x8 ; CHECK-NEXT: st1d { z1.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i64>, <16 x i64>* %a - %op2 = load <16 x i64>, <16 x i64>* %b + %op1 = load <16 x i64>, ptr %a + %op2 = load <16 x i64>, ptr %b %ret = shufflevector <16 x i64> %op1, <16 x i64> %op2, <16 x i32> - store <16 x i64> %ret, <16 x i64>* %a + store <16 x i64> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_range(16,0) #0 { +define void @shuffle_ext_byone_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v32i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -527,13 +527,13 @@ define void @shuffle_ext_byone_v32i64(<32 x i64>* %a, <32 x i64>* %b) vscale_ran ; CHECK-NEXT: insr z1.d, x8 ; CHECK-NEXT: st1d { z1.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i64>, <32 x i64>* %a - %op2 = load <32 x i64>, <32 x i64>* %b + %op1 = load <32 x i64>, ptr %a + %op2 = load <32 x i64>, ptr %b %ret = shufflevector <32 x i64> %op1, <32 x i64> %op2, <32 x i32> - store <32 x i64> %ret, <32 x i64>* %a + store <32 x i64> %ret, ptr %a ret void } @@ -557,7 +557,7 @@ define <8 x half> @shuffle_ext_byone_v8f16(<8 x half> %op1, <8 x half> %op2) vsc ret <8 x half> %ret } -define void @shuffle_ext_byone_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_range(2,0) #0 { +define void @shuffle_ext_byone_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl16 @@ -567,15 +567,15 @@ define void @shuffle_ext_byone_v16f16(<16 x half>* %a, <16 x half>* %b) vscale_r ; CHECK-NEXT: insr z1.h, h0 ; CHECK-NEXT: st1h { z1.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x half>, <16 x half>* %a - %op2 = load <16 x half>, <16 x half>* %b + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b %ret = shufflevector <16 x half> %op1, <16 x half> %op2, <16 x i32> - store <16 x half> %ret, <16 x half>* %a + store <16 x half> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { +define void @shuffle_ext_byone_v32f16(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: shuffle_ext_byone_v32f16: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #16 @@ -600,17 +600,17 @@ define void @shuffle_ext_byone_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { ; VBITS_GE_512-NEXT: insr z1.h, h0 ; VBITS_GE_512-NEXT: st1h { z1.h }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <32 x half>, <32 x half>* %a - %op2 = load <32 x half>, <32 x half>* %b + %op1 = load <32 x half>, ptr %a + %op2 = load <32 x half>, ptr %b %ret = shufflevector <32 x half> %op1, <32 x half> %op2, <32 x i32> - store <32 x half> %ret, <32 x half>* %a + store <32 x half> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_range(8,0) #0 { +define void @shuffle_ext_byone_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v64f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl64 @@ -622,8 +622,8 @@ define void @shuffle_ext_byone_v64f16(<64 x half>* %a, <64 x half>* %b) vscale_r ; CHECK-NEXT: insr z1.h, h0 ; CHECK-NEXT: st1h { z1.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x half>, <64 x half>* %a - %op2 = load <64 x half>, <64 x half>* %b + %op1 = load <64 x half>, ptr %a + %op2 = load <64 x half>, ptr %b %ret = shufflevector <64 x half> %op1, <64 x half> %op2, <64 x i32> * %a, <64 x half>* %b) vscale_r i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126> - store <64 x half> %ret, <64 x half>* %a + store <64 x half> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v128f16(<128 x half>* %a, <128 x half>* %b) vscale_range(16,0) #0 { +define void @shuffle_ext_byone_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v128f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h, vl128 @@ -648,8 +648,8 @@ define void @shuffle_ext_byone_v128f16(<128 x half>* %a, <128 x half>* %b) vscal ; CHECK-NEXT: insr z1.h, h0 ; CHECK-NEXT: st1h { z1.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <128 x half>, <128 x half>* %a - %op2 = load <128 x half>, <128 x half>* %b + %op1 = load <128 x half>, ptr %a + %op2 = load <128 x half>, ptr %b %ret = shufflevector <128 x half> %op1, <128 x half> %op2, <128 x i32> * %a, <128 x half>* %b) vscal i32 231, i32 232, i32 233, i32 234, i32 235, i32 236, i32 237, i32 238, i32 239, i32 240, i32 241, i32 242, i32 243, i32 244, i32 245, i32 246, i32 247, i32 248, i32 249, i32 250, i32 251, i32 252, i32 253, i32 254> - store <128 x half> %ret, <128 x half>* %a + store <128 x half> %ret, ptr %a ret void } @@ -690,7 +690,7 @@ define <4 x float> @shuffle_ext_byone_v4f32(<4 x float> %op1, <4 x float> %op2) ret <4 x float> %ret } -define void @shuffle_ext_byone_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_range(2,0) #0 { +define void @shuffle_ext_byone_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl8 @@ -700,14 +700,14 @@ define void @shuffle_ext_byone_v8f32(<8 x float>* %a, <8 x float>* %b) vscale_ra ; CHECK-NEXT: insr z1.s, s0 ; CHECK-NEXT: st1w { z1.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x float>, <8 x float>* %a - %op2 = load <8 x float>, <8 x float>* %b + %op1 = load <8 x float>, ptr %a + %op2 = load <8 x float>, ptr %b %ret = shufflevector <8 x float> %op1, <8 x float> %op2, <8 x i32> - store <8 x float> %ret, <8 x float>* %a + store <8 x float> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { +define void @shuffle_ext_byone_v16f32(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: shuffle_ext_byone_v16f32: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #8 @@ -732,15 +732,15 @@ define void @shuffle_ext_byone_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { ; VBITS_GE_512-NEXT: insr z1.s, s0 ; VBITS_GE_512-NEXT: st1w { z1.s }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <16 x float>, <16 x float>* %a - %op2 = load <16 x float>, <16 x float>* %b + %op1 = load <16 x float>, ptr %a + %op2 = load <16 x float>, ptr %b %ret = shufflevector <16 x float> %op1, <16 x float> %op2, <16 x i32> - store <16 x float> %ret, <16 x float>* %a + store <16 x float> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v32f32(<32 x float>* %a, <32 x float>* %b) vscale_range(8,0) #0 { +define void @shuffle_ext_byone_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v32f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl32 @@ -752,17 +752,17 @@ define void @shuffle_ext_byone_v32f32(<32 x float>* %a, <32 x float>* %b) vscale ; CHECK-NEXT: insr z1.s, s0 ; CHECK-NEXT: st1w { z1.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x float>, <32 x float>* %a - %op2 = load <32 x float>, <32 x float>* %b + %op1 = load <32 x float>, ptr %a + %op2 = load <32 x float>, ptr %b %ret = shufflevector <32 x float> %op1, <32 x float> %op2, <32 x i32> - store <32 x float> %ret, <32 x float>* %a + store <32 x float> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v64f32(<64 x float>* %a, <64 x float>* %b) vscale_range(16,0) #0 { +define void @shuffle_ext_byone_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v64f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s, vl64 @@ -774,8 +774,8 @@ define void @shuffle_ext_byone_v64f32(<64 x float>* %a, <64 x float>* %b) vscale ; CHECK-NEXT: insr z1.s, s0 ; CHECK-NEXT: st1w { z1.s }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <64 x float>, <64 x float>* %a - %op2 = load <64 x float>, <64 x float>* %b + %op1 = load <64 x float>, ptr %a + %op2 = load <64 x float>, ptr %b %ret = shufflevector <64 x float> %op1, <64 x float> %op2, <64 x i32> * %a, <64 x float>* %b) vscale i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126> - store <64 x float> %ret, <64 x float>* %a + store <64 x float> %ret, ptr %a ret void } @@ -798,7 +798,7 @@ define <2 x double> @shuffle_ext_byone_v2f64(<2 x double> %op1, <2 x double> %op ret <2 x double> %ret } -define void @shuffle_ext_byone_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @shuffle_ext_byone_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -808,14 +808,14 @@ define void @shuffle_ext_byone_v4f64(<4 x double>* %a, <4 x double>* %b) vscale_ ; CHECK-NEXT: insr z1.d, d0 ; CHECK-NEXT: st1d { z1.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a - %op2 = load <4 x double>, <4 x double>* %b + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> - store <4 x double> %ret, <4 x double>* %a + store <4 x double> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { +define void @shuffle_ext_byone_v8f64(ptr %a, ptr %b) #0 { ; VBITS_GE_256-LABEL: shuffle_ext_byone_v8f64: ; VBITS_GE_256: // %bb.0: ; VBITS_GE_256-NEXT: mov x8, #4 @@ -840,14 +840,14 @@ define void @shuffle_ext_byone_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { ; VBITS_GE_512-NEXT: insr z1.d, d0 ; VBITS_GE_512-NEXT: st1d { z1.d }, p0, [x0] ; VBITS_GE_512-NEXT: ret - %op1 = load <8 x double>, <8 x double>* %a - %op2 = load <8 x double>, <8 x double>* %b + %op1 = load <8 x double>, ptr %a + %op2 = load <8 x double>, ptr %b %ret = shufflevector <8 x double> %op1, <8 x double> %op2, <8 x i32> - store <8 x double> %ret, <8 x double>* %a + store <8 x double> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v16f64(<16 x double>* %a, <16 x double>* %b) vscale_range(8,0) #0 { +define void @shuffle_ext_byone_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v16f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl16 @@ -859,15 +859,15 @@ define void @shuffle_ext_byone_v16f64(<16 x double>* %a, <16 x double>* %b) vsca ; CHECK-NEXT: insr z1.d, d0 ; CHECK-NEXT: st1d { z1.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x double>, <16 x double>* %a - %op2 = load <16 x double>, <16 x double>* %b + %op1 = load <16 x double>, ptr %a + %op2 = load <16 x double>, ptr %b %ret = shufflevector <16 x double> %op1, <16 x double> %op2, <16 x i32> - store <16 x double> %ret, <16 x double>* %a + store <16 x double> %ret, ptr %a ret void } -define void @shuffle_ext_byone_v32f64(<32 x double>* %a, <32 x double>* %b) vscale_range(16,0) #0 { +define void @shuffle_ext_byone_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_v32f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl32 @@ -879,17 +879,17 @@ define void @shuffle_ext_byone_v32f64(<32 x double>* %a, <32 x double>* %b) vsca ; CHECK-NEXT: insr z1.d, d0 ; CHECK-NEXT: st1d { z1.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x double>, <32 x double>* %a - %op2 = load <32 x double>, <32 x double>* %b + %op1 = load <32 x double>, ptr %a + %op2 = load <32 x double>, ptr %b %ret = shufflevector <32 x double> %op1, <32 x double> %op2, <32 x i32> - store <32 x double> %ret, <32 x double>* %a + store <32 x double> %ret, ptr %a ret void } -define void @shuffle_ext_byone_reverse(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @shuffle_ext_byone_reverse(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: shuffle_ext_byone_reverse: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d, vl4 @@ -899,14 +899,14 @@ define void @shuffle_ext_byone_reverse(<4 x double>* %a, <4 x double>* %b) vscal ; CHECK-NEXT: insr z0.d, d1 ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a - %op2 = load <4 x double>, <4 x double>* %b + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> - store <4 x double> %ret, <4 x double>* %a + store <4 x double> %ret, ptr %a ret void } -define void @shuffle_ext_invalid(<4 x double>* %a, <4 x double>* %b) vscale_range(2,0) #0 { +define void @shuffle_ext_invalid(ptr %a, ptr %b) vscale_range(2,0) #0 { ; CHECK-LABEL: shuffle_ext_invalid: ; CHECK: // %bb.0: ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill @@ -930,10 +930,10 @@ define void @shuffle_ext_invalid(<4 x double>* %a, <4 x double>* %b) vscale_rang ; CHECK-NEXT: mov sp, x29 ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ret - %op1 = load <4 x double>, <4 x double>* %a - %op2 = load <4 x double>, <4 x double>* %b + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> - store <4 x double> %ret, <4 x double>* %a + store <4 x double> %ret, ptr %a ret void } -- 2.7.4