From 0dc0c27989d3c26e677f3975d4911ffe72bdd8c1 Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Wed, 17 May 2023 07:35:47 -0700 Subject: [PATCH] [TLI] Add IsZero parameter to storeOfVectorConstantIsCheap [nfc] Make the decision to consider zero constant stores cheap target specific. Will be used in an upcoming change for RISCV. --- llvm/include/llvm/CodeGen/TargetLowering.h | 8 ++++---- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 +++----- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 2 +- llvm/lib/Target/X86/X86ISelLowering.h | 4 ++-- 5 files changed, 11 insertions(+), 13 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index 074a485..dded1e5 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -608,13 +608,13 @@ public: return isLoadBitCastBeneficial(StoreVT, BitcastVT, DAG, MMO); } - /// Return true if it is expected to be cheaper to do a store of a non-zero - /// vector constant with the given size and type for the address space than to + /// Return true if it is expected to be cheaper to do a store of vector + /// constant with the given size and type for the address space than to /// store the individual scalar element constants. - virtual bool storeOfVectorConstantIsCheap(EVT MemVT, + virtual bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AddrSpace) const { - return false; + return IsZero; } /// Allow store merging for the specified type after legalization in addition diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 85da5f4..75b6d86 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -19782,11 +19782,9 @@ bool DAGCombiner::tryStoreMergeOfConstants( } } - // We only use vectors if the constant is known to be zero or the - // target allows it and the function is not marked with the - // noimplicitfloat attribute. - if ((!NonZero || - TLI.storeOfVectorConstantIsCheap(MemVT, i + 1, FirstStoreAS)) && + // We only use vectors if the target allows it and the function is not + // marked with the noimplicitfloat attribute. + if (TLI.storeOfVectorConstantIsCheap(!NonZero, MemVT, i + 1, FirstStoreAS) && AllowVectors) { // Find a legal type for the vector store. unsigned Elts = (i + 1) * NumMemElts; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index e7a7b20..82e5393 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -869,7 +869,7 @@ bool AMDGPUTargetLowering::isFNegFree(EVT VT) const { return VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f16; } -bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT, +bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AS) const { return true; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h index 84dfc37..5b2b469 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h @@ -200,7 +200,7 @@ public: bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const final; - bool storeOfVectorConstantIsCheap(EVT MemVT, + bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AS) const override; bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override; diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index 4eb079f..9a06502 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -1439,11 +1439,11 @@ namespace llvm { bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override; - bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, + bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AddrSpace) const override { // If we can replace more than 2 scalar stores, there will be a reduction // in instructions even after we add a vector constant load. - return NumElem > 2; + return IsZero || NumElem > 2; } bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, -- 2.7.4