From 0dac17af0ab4e55b6b18a762141f255d3eea1e37 Mon Sep 17 00:00:00 2001 From: Lucas De Marchi Date: Wed, 14 Oct 2020 12:19:32 -0700 Subject: [PATCH] drm/i915/dg1: Enable DPLL for DG1 Add DG1 DPLL Enable register macro and use the macro to enable the correct DPLL based on PLL id. Although we use _MG_PLL1_ENABLE/_MG_PLL2_ENABLE these are rather combo phys. While at it, fix coding style: wrong newlines and use if/else chain v2: Rewrite original patch from Aditya Swarup based on refactors upstream Bspec: 49443, 49206 Cc: Clinton Taylor Cc: Matt Roper Cc: Aditya Swarup Signed-off-by: Lucas De Marchi Reviewed-by: Aditya Swarup Link: https://patchwork.freedesktop.org/patch/msgid/20201014191937.1266226-6-lucas.demarchi@intel.com --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++++---- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 2f412d2..eaef7a2 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -151,14 +151,14 @@ static i915_reg_t intel_combo_pll_enable_reg(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { - - if (IS_JSL_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4)) + if (IS_DG1(i915)) + return DG1_DPLL_ENABLE(pll->info->id); + else if (IS_JSL_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4)) return MG_PLL_ENABLE(0); return CNL_DPLL_ENABLE(pll->info->id); - - } + /** * intel_prepare_shared_dpll - call a dpll's prepare hook * @crtc_state: CRTC, and its state, which has a shared dpll diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0b67c86..49945e3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10316,6 +10316,10 @@ enum skl_power_gate { #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ _MG_PLL2_ENABLE) +/* DG1 PLL */ +#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ + _MG_PLL1_ENABLE, _MG_PLL2_ENABLE) + #define _MG_REFCLKIN_CTL_PORT1 0x16892C #define _MG_REFCLKIN_CTL_PORT2 0x16992C #define _MG_REFCLKIN_CTL_PORT3 0x16A92C -- 2.7.4