From 0dab98d9269355d3622c0949f27e2559892f2757 Mon Sep 17 00:00:00 2001
From: Saleem Abdulrasool <compnerd@compnerd.org>
Date: Fri, 25 Mar 2016 00:34:11 +0000
Subject: [PATCH] ARM: fix optimised division on WoA

We did not have an explicit branch to the continuation BB.  When the check was
hoisted, this could permit control follow to fall through into the division
trap.  Add the explicit branch to the continuation basic block to ensure that
code execution is correct.

llvm-svn: 264370
---
 llvm/lib/Target/ARM/ARMISelLowering.cpp   |  1 +
 llvm/test/CodeGen/ARM/Windows/division.ll | 35 ++++++++++++++++++++++++++++---
 2 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index dc34d47..0d9b77a 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -8064,6 +8064,7 @@ ARMTargetLowering::EmitLowered__dbzchk(MachineInstr *MI,
   BuildMI(*MBB, MI, DL, TII->get(ARM::tCBZ))
       .addReg(MI->getOperand(0).getReg())
       .addMBB(TrapBB);
+  AddDefaultPred(BuildMI(*MBB, MI, DL, TII->get(ARM::t2B)).addMBB(ContBB));
   MBB->addSuccessor(ContBB);
 
   MI->eraseFromParent();
diff --git a/llvm/test/CodeGen/ARM/Windows/division.ll b/llvm/test/CodeGen/ARM/Windows/division.ll
index 098226e..a3d467fc 100644
--- a/llvm/test/CodeGen/ARM/Windows/division.ll
+++ b/llvm/test/CodeGen/ARM/Windows/division.ll
@@ -9,8 +9,9 @@ entry:
 
 ; CHECK-LABEL: sdiv32:
 ; CHECK: cbz r0
-; CHECK: bl __rt_sdiv
+; CHECK: b
 ; CHECK: udf.w #249
+; CHECK: bl __rt_sdiv
 
 define arm_aapcs_vfpcc i32 @udiv32(i32 %divisor, i32 %divident) {
 entry:
@@ -20,8 +21,9 @@ entry:
 
 ; CHECK-LABEL: udiv32:
 ; CHECK: cbz r0
-; CHECK: bl __rt_udiv
+; CHECK: b
 ; CHECK: udf.w #249
+; CHECK: bl __rt_udiv
 
 define arm_aapcs_vfpcc i64 @sdiv64(i64 %divisor, i64 %divident) {
 entry:
@@ -32,8 +34,9 @@ entry:
 ; CHECK-LABEL: sdiv64:
 ; CHECK: orr.w r12, r0, r1
 ; CHECK-NEXT: cbz r12
-; CHECK: bl __rt_sdiv64
+; CHECK: b
 ; CHECK: udf.w #249
+; CHECK: bl __rt_sdiv64
 
 define arm_aapcs_vfpcc i64 @udiv64(i64 %divisor, i64 %divident) {
 entry:
@@ -44,6 +47,32 @@ entry:
 ; CHECK-LABEL: udiv64:
 ; CHECK: orr.w r12, r0, r1
 ; CHECK-NEXT: cbz r12
+; CHECK: b
+; CHECK: udf.w #249
 ; CHECK: bl __rt_udiv64
+
+declare arm_aapcs_vfpcc i32 @g(...)
+
+define arm_aapcs_vfpcc i32 @f(i32 %b, i32 %d) #0 {
+entry:
+  %tobool = icmp eq i32 %b, 0
+  br i1 %tobool, label %return, label %if.then
+
+if.then:
+  %call = tail call arm_aapcs_vfpcc i32 bitcast (i32 (...)* @g to i32 ()*)()
+  %rem = urem i32 %call, %d
+  br label %return
+
+return:
+  %retval.0 = phi i32 [ %rem, %if.then ], [ 0, %entry ]
+  ret i32 %retval.0
+}
+
+; CHECK-LABEL: f:
+; CHECK: cbz r0,
+; CHECK: cbz r4,
+; CHECK: b
 ; CHECK: udf.w #249
 
+attributes #0 = { optsize }
+
-- 
2.7.4