From 0da890e62cf14fef273500491d14fb8d980fe452 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Nicolai=20H=C3=A4hnle?= Date: Fri, 24 Jun 2016 01:11:09 +0200 Subject: [PATCH] radeonsi: drop the DRAW_PREAMBLE packet on Polaris MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit It will be removed from the firmware for the Polaris. Cc: 12.0 Reviewed-by: Alex Deucher Reviewed-by: Marek Olšák --- src/gallium/drivers/radeon/r600_cs.h | 22 ++++++++++++++++++++++ src/gallium/drivers/radeonsi/si_state_draw.c | 7 ++++++- 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeon/r600_cs.h b/src/gallium/drivers/radeon/r600_cs.h index 157d56c..72a91bf 100644 --- a/src/gallium/drivers/radeon/r600_cs.h +++ b/src/gallium/drivers/radeon/r600_cs.h @@ -97,6 +97,17 @@ static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned radeon_emit(cs, value); } +static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs, + unsigned reg, unsigned idx, + unsigned value) +{ + assert(reg >= R600_CONTEXT_REG_OFFSET); + assert(cs->current.cdw + 3 <= cs->current.max_dw); + radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); + radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); + radeon_emit(cs, value); +} + static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) { assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); @@ -125,4 +136,15 @@ static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned radeon_emit(cs, value); } +static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs, + unsigned reg, unsigned idx, + unsigned value) +{ + assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); + assert(cs->current.cdw + 3 <= cs->current.max_dw); + radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0)); + radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28)); + radeon_emit(cs, value); +} + #endif diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 5273718..712e3df 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -448,7 +448,11 @@ static void si_emit_draw_registers(struct si_context *sctx, if (prim != sctx->last_prim || ia_multi_vgt_param != sctx->last_multi_vgt_param || ls_hs_config != sctx->last_ls_hs_config) { - if (sctx->b.chip_class >= CIK) { + if (sctx->b.family >= CHIP_POLARIS10) { + radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param); + radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config); + radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim); + } else if (sctx->b.chip_class >= CIK) { radeon_emit(cs, PKT3(PKT3_DRAW_PREAMBLE, 2, 0)); radeon_emit(cs, prim); /* VGT_PRIMITIVE_TYPE */ radeon_emit(cs, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */ @@ -458,6 +462,7 @@ static void si_emit_draw_registers(struct si_context *sctx, radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param); radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config); } + sctx->last_prim = prim; sctx->last_multi_vgt_param = ia_multi_vgt_param; sctx->last_ls_hs_config = ls_hs_config; -- 2.7.4