From 0d96484165a42f95d2a894f7cfb9888674f45ce8 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 26 Aug 2019 00:05:21 -0700 Subject: [PATCH] intel/compiler: Use generic SEND for Gen7+ FB writes This takes care of generate_fb_write/fire_fb_write/brw_fb_WRITE's stuff earlier in the visitor. It will also make it easier to generate SENDSC messages with indirect extended descriptors in a few patches. Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_fs.cpp | 29 +++++++++++++++++++----- src/intel/compiler/brw_schedule_instructions.cpp | 5 ++++ 2 files changed, 28 insertions(+), 6 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 5aeffab..72393b7 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -4439,8 +4439,26 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, payload.nr = bld.shader->alloc.allocate(regs_written(load)); load->dst = payload; - inst->src[0] = payload; - inst->resize_sources(1); + uint32_t msg_ctl = brw_fb_write_msg_control(inst, prog_data); + uint32_t ex_desc = 0; + + inst->desc = + (inst->group / 16) ? (1 << 11) : 0 | /* rt slot group */ + brw_dp_write_desc(devinfo, inst->target, msg_ctl, + GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE, + inst->last_rt, false); + + inst->opcode = SHADER_OPCODE_SEND; + inst->resize_sources(3); + inst->sfid = GEN6_SFID_DATAPORT_RENDER_CACHE; + inst->src[0] = brw_imm_ud(inst->desc); + inst->src[1] = brw_imm_ud(ex_desc); + inst->src[2] = payload; + inst->mlen = regs_written(load); + inst->ex_mlen = 0; + inst->header_size = header_size; + inst->check_tdr = true; + inst->send_has_side_effects = true; } else { /* Send from the MRF */ load = bld.LOAD_PAYLOAD(fs_reg(MRF, 1, BRW_REGISTER_TYPE_F), @@ -4460,11 +4478,10 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, inst->resize_sources(0); } inst->base_mrf = 1; + inst->opcode = FS_OPCODE_FB_WRITE; + inst->mlen = regs_written(load); + inst->header_size = header_size; } - - inst->opcode = FS_OPCODE_FB_WRITE; - inst->mlen = regs_written(load); - inst->header_size = header_size; } static void diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp index 4fed149..08e8915 100644 --- a/src/intel/compiler/brw_schedule_instructions.cpp +++ b/src/intel/compiler/brw_schedule_instructions.cpp @@ -412,6 +412,11 @@ schedule_node::set_latency_gen7(bool is_haswell) latency = 14000; break; + case GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE: + /* completely fabricated number */ + latency = 600; + break; + default: unreachable("Unknown render cache message"); } -- 2.7.4