From 0d89e849bdf96dc424505c1bc84e24d504aee60c Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 15 Jul 2014 21:44:37 +0000 Subject: [PATCH] R600/SI: Fix select on i1 llvm-svn: 213096 --- llvm/lib/Target/R600/SIISelLowering.cpp | 3 +++ llvm/test/CodeGen/R600/and.ll | 9 +++++++++ llvm/test/CodeGen/R600/or.ll | 16 ++++++++++++++++ llvm/test/CodeGen/R600/select-i1.ll | 14 ++++++++++++++ llvm/test/CodeGen/R600/select.ll | 17 +++++++++-------- 5 files changed, 51 insertions(+), 8 deletions(-) create mode 100644 llvm/test/CodeGen/R600/select-i1.ll diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp index 56e760c..b107ed4 100644 --- a/llvm/lib/Target/R600/SIISelLowering.cpp +++ b/llvm/lib/Target/R600/SIISelLowering.cpp @@ -182,6 +182,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) : MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32 }; + setOperationAction(ISD::SELECT_CC, MVT::i1, Expand); + setOperationAction(ISD::SELECT, MVT::i1, Promote); + for (MVT VT : VecTypes) { for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) { switch(Op) { diff --git a/llvm/test/CodeGen/R600/and.ll b/llvm/test/CodeGen/R600/and.ll index cf11481..e20037e 100644 --- a/llvm/test/CodeGen/R600/and.ll +++ b/llvm/test/CodeGen/R600/and.ll @@ -80,6 +80,15 @@ define void @s_and_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { ret void } +; FIXME: Should use SGPRs +; FUNC-LABEL: @s_and_i1 +; SI: V_AND_B32 +define void @s_and_i1(i1 addrspace(1)* %out, i1 %a, i1 %b) { + %and = and i1 %a, %b + store i1 %and, i1 addrspace(1)* %out + ret void +} + ; FUNC-LABEL: @s_and_constant_i64 ; SI: S_AND_B64 define void @s_and_constant_i64(i64 addrspace(1)* %out, i64 %a) { diff --git a/llvm/test/CodeGen/R600/or.ll b/llvm/test/CodeGen/R600/or.ll index 91a70b7..3c3b475 100644 --- a/llvm/test/CodeGen/R600/or.ll +++ b/llvm/test/CodeGen/R600/or.ll @@ -127,3 +127,19 @@ define void @trunc_i64_or_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) { store i32 %trunc, i32 addrspace(1)* %out, align 8 ret void } + +; EG-CHECK: @or_i1 +; EG-CHECK: OR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}} + +; SI-CHECK: @or_i1 +; SI-CHECK: S_OR_B64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] +define void @or_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) { + %a = load float addrspace(1) * %in0 + %b = load float addrspace(1) * %in1 + %acmp = fcmp oge float %a, 0.000000e+00 + %bcmp = fcmp oge float %b, 0.000000e+00 + %or = or i1 %acmp, %bcmp + %result = select i1 %or, float %a, float %b + store float %result, float addrspace(1)* %out + ret void +} diff --git a/llvm/test/CodeGen/R600/select-i1.ll b/llvm/test/CodeGen/R600/select-i1.ll new file mode 100644 index 0000000..009dd7f --- /dev/null +++ b/llvm/test/CodeGen/R600/select-i1.ll @@ -0,0 +1,14 @@ +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s + +; FIXME: This should go in existing select.ll test, except the current testcase there is broken on SI + +; FUNC-LABEL: @select_i1 +; SI: V_CNDMASK_B32 +; SI-NOT: V_CNDMASK_B32 +define void @select_i1(i1 addrspace(1)* %out, i32 %cond, i1 %a, i1 %b) nounwind { + %cmp = icmp ugt i32 %cond, 5 + %sel = select i1 %cmp, i1 %a, i1 %b + store i1 %sel, i1 addrspace(1)* %out, align 4 + ret void +} + diff --git a/llvm/test/CodeGen/R600/select.ll b/llvm/test/CodeGen/R600/select.ll index f940142..7d51568 100644 --- a/llvm/test/CodeGen/R600/select.ll +++ b/llvm/test/CodeGen/R600/select.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + ; Normally icmp + select is optimized to select_cc, when this happens the ; DAGLegalizer never sees the select and doesn't have a chance to leaglize it. @@ -6,13 +7,13 @@ ; In order to avoid the select_cc optimization, this test case calculates the ; condition for the select in a separate basic block. -; CHECK-LABEL: @select -; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.X -; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.X -; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY -; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY -; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW -; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW +; FUNC-LABEL: @select +; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.X +; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.X +; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY +; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY +; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW +; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW define void @select (i32 addrspace(1)* %i32out, float addrspace(1)* %f32out, <2 x i32> addrspace(1)* %v2i32out, <2 x float> addrspace(1)* %v2f32out, <4 x i32> addrspace(1)* %v4i32out, <4 x float> addrspace(1)* %v4f32out, -- 2.7.4