From 0ce595a89a784fff14db723151b9ddb824a5a81d Mon Sep 17 00:00:00 2001 From: Mark Janes Date: Wed, 8 Feb 2023 15:47:20 -0800 Subject: [PATCH] intel: use generated helpers for Wa_1508744258 iris_disable_rhwo_optimization can only apply on gfxver 12.0, and has a version check to that affect. Add an assertion to warn us if the workaround ever applies to another version. Reviewed-by: Lionel Landwerlin Reviewed-by: Nanley Chery Part-of: --- src/gallium/drivers/iris/iris_resolve.c | 28 ++++++++++++++++------------ src/gallium/drivers/iris/iris_state.c | 7 +++++-- src/intel/vulkan/anv_blorp.c | 3 ++- src/intel/vulkan/genX_cmd_buffer.c | 5 ++--- src/intel/vulkan/genX_state.c | 6 +++--- 5 files changed, 28 insertions(+), 21 deletions(-) diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c index b768d7e..0611271 100644 --- a/src/gallium/drivers/iris/iris_resolve.c +++ b/src/gallium/drivers/iris/iris_resolve.c @@ -518,17 +518,19 @@ iris_resolve_color(struct iris_context *ice, iris_emit_end_of_pipe_sync(batch, "color resolve: pre-flush", PIPE_CONTROL_RENDER_TARGET_FLUSH); - /* Wa_1508744258 - * - * Disable RHWO by setting 0x7010[14] by default except during resolve - * pass. - * - * We implement global disabling of the RHWO optimization during - * iris_init_render_context. We toggle it around the blorp resolve call. - */ - assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE || - resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE); - batch->screen->vtbl.disable_rhwo_optimization(batch, false); + if (intel_needs_workaround(batch->screen->devinfo, 1508744258)) { + /* The suggested workaround is: + * + * Disable RHWO by setting 0x7010[14] by default except during resolve + * pass. + * + * We implement global disabling of the RHWO optimization during + * iris_init_render_context. We toggle it around the blorp resolve call. + */ + assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE || + resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE); + batch->screen->vtbl.disable_rhwo_optimization(batch, false); + } iris_batch_sync_region_start(batch); struct blorp_batch blorp_batch; @@ -541,7 +543,9 @@ iris_resolve_color(struct iris_context *ice, iris_emit_end_of_pipe_sync(batch, "color resolve: post-flush", PIPE_CONTROL_RENDER_TARGET_FLUSH); - batch->screen->vtbl.disable_rhwo_optimization(batch, true); + if (intel_needs_workaround(batch->screen->devinfo, 1508744258)) { + batch->screen->vtbl.disable_rhwo_optimization(batch, true); + } iris_batch_sync_region_end(batch); } diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index fed17a7..a7758e2 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -1078,6 +1078,7 @@ init_aux_map_state(struct iris_batch *batch); static void iris_disable_rhwo_optimization(struct iris_batch *batch, bool disable) { + assert(batch->screen->devinfo->verx10 == 120); #if GFX_VERx10 == 120 iris_emit_reg(batch, GENX(COMMON_SLICE_CHICKEN1), c1) { c1.RCCRHWOOptimizationDisable = disable; @@ -1228,8 +1229,8 @@ iris_init_render_context(struct iris_batch *batch) } #endif -#if GFX_VERx10 == 120 - /* Wa_1508744258 +#if INTEL_NEEDS_WORKAROUND_1508744258 + /* The suggested workaround is: * * Disable RHWO by setting 0x7010[14] by default except during resolve * pass. @@ -1244,7 +1245,9 @@ iris_init_render_context(struct iris_batch *batch) * field in the 3DSTATE_PS instruction). */ iris_disable_rhwo_optimization(batch, true); +#endif +#if GFX_VERx10 == 120 /* Wa_1806527549 says to disable the following HiZ optimization when the * depth buffer is D16_UNORM. We've found the WA to help with more depth * buffer configurations however, so we always disable it just to be safe. diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index f8d2b92..0c59e5e 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -1252,7 +1252,8 @@ exec_ccs_op(struct anv_cmd_buffer *cmd_buffer, case ISL_AUX_OP_FULL_RESOLVE: case ISL_AUX_OP_PARTIAL_RESOLVE: { /* Wa_1508744258: Enable RHWO optimization for resolves */ - const bool enable_rhwo_opt = cmd_buffer->device->info->verx10 == 120; + const bool enable_rhwo_opt = + intel_needs_workaround(cmd_buffer->device->info, 1508744258); if (enable_rhwo_opt) cmd_buffer->state.pending_rhwo_optimization_enabled = true; diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index b338377..e6fab0f 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1761,7 +1761,7 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, ALWAYS_INLINE void genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) { -#if GFX_VERx10 == 120 +#if INTEL_NEEDS_WA_1508744258 /* If we're changing the state of the RHWO optimization, we need to have * sb_stall+cs_stall. */ @@ -1809,8 +1809,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) cmd_buffer->state.current_pipeline, bits); -#if GFX_VERx10 == 120 - /* Wa_1508744258 handling */ +#if INTEL_NEEDS_WA_1508744258 if (rhwo_opt_change) { anv_batch_write_reg(&cmd_buffer->batch, GENX(COMMON_SLICE_CHICKEN1), c1) { c1.RCCRHWOOptimizationDisable = diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index 8c2f5f8..2d01f81 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -467,10 +467,10 @@ init_render_queue_state(struct anv_queue *queue) reg.HZDepthTestLEGEOptimizationDisable = true; reg.HZDepthTestLEGEOptimizationDisableMask = true; } +#endif - /* Wa_1508744258 - * - * Disable RHWO by setting 0x7010[14] by default except during resolve +#if INTEL_NEEDS_WA_1508744258 + /* Disable RHWO by setting 0x7010[14] by default except during resolve * pass. * * We implement global disabling of the optimization here and we toggle it -- 2.7.4