From 0c79cf1f486135929f4370b6d919be0facdc1c8e Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 31 Jul 2019 14:21:21 +0200 Subject: [PATCH] dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings Armada CP110 PCIe controller can have from one to four PHYs for configuring SERDES lanes (PCIe x1, PCIe x2 or PCIe x4). Describe the phys and phy-names properties in the bindings. Signed-off-by: Miquel Raynal Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/pci-armada8k.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt index 9e3fc15..8324a4e 100644 --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt @@ -17,6 +17,14 @@ Required properties: name must be "core" for the first clock and "reg" for the second one +Optional properties: +- phys: phandle(s) to PHY node(s) following the generic PHY bindings. + Either 1, 2 or 4 PHYs might be needed depending on the number of + PCIe lanes. +- phy-names: names of the PHYs corresponding to the number of lanes. + Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for + 2 PHYs. + Example: pcie@f2600000 { -- 2.7.4