From 0c1dad8fe3fb0bda7d07b9655479ee2c01e85cc3 Mon Sep 17 00:00:00 2001 From: Evoke Zhang Date: Tue, 12 Jun 2018 15:55:04 +0800 Subject: [PATCH] lcd: mipi-dsi: set clk lane only according to clk_always_hs [2/2] PD#168252: lcd: mipi-dsi: set clk lane only according to clk_always_hs, remove restrictions by operation mode. Change-Id: Icac07d74ae07d60edc6a6b507d06d962780e3984 Signed-off-by: Evoke Zhang --- .../media/vout/lcd/lcd_tablet/mipi_dsi_util.c | 38 ++++++++-------------- 1 file changed, 13 insertions(+), 25 deletions(-) diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.c index d72586c..4723b47 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.c +++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.c @@ -537,7 +537,7 @@ static void dsi_phy_init(struct dsi_phy_s *dphy, unsigned char lane_num) } } -static void set_dsi_phy_config(struct lcd_config_s *pconf) +static void set_dsi_phy_config(struct dsi_config_s *dconf) { if (lcd_debug_print_flag) LCDPR("%s\n", __func__); @@ -558,18 +558,13 @@ static void set_dsi_phy_config(struct lcd_config_s *pconf) dsi_host_write(MIPI_DSI_DWC_PHY_RSTZ_OS, 0xf); /* Analog */ - dsi_phy_init(&dsi_phy_config, pconf->lcd_control.mipi_config->lane_num); + dsi_phy_init(&dsi_phy_config, dconf->lane_num); /* Check the phylock/stopstateclklane to decide if the DPHY is ready */ check_phy_status(); /* Trigger a sync active for esc_clk */ dsi_phy_set_mask(MIPI_DSI_PHY_CTRL, (1 << 1)); - - /* Startup transfer, default lpclk */ - dsi_host_write(MIPI_DSI_DWC_LPCLK_CTRL_OS, - (0x1 << BIT_AUTOCLKLANE_CTRL) | - (0x1 << BIT_TXREQUESTCLKHS)); } static void startup_mipi_dsi_host(void) @@ -591,21 +586,16 @@ static void startup_mipi_dsi_host(void) mdelay(10); } -static void set_mipi_dsi_lpclk_ctrl(struct dsi_config_s *dconf, - unsigned int operation_mode) +static void mipi_dsi_lpclk_ctrl(struct dsi_config_s *dconf) { - unsigned int lpclk = 1; + unsigned int lpclk; - if (operation_mode == OPERATION_VIDEO_MODE) { - if (dconf->clk_always_hs) /* clk always hs */ - lpclk = 0; - else /* enable clk lp state */ - lpclk = 1; - } else { /* enable clk lp state */ - lpclk = 1; - } - dsi_host_setb(MIPI_DSI_DWC_LPCLK_CTRL_OS, - lpclk, BIT_AUTOCLKLANE_CTRL, 1); + /* when lpclk = 1, enable clk lp state */ + lpclk = (dconf->clk_always_hs) ? 0 : 1; + + dsi_host_write(MIPI_DSI_DWC_LPCLK_CTRL_OS, + (lpclk << BIT_AUTOCLKLANE_CTRL) | + (0x1 << BIT_TXREQUESTCLKHS)); } /* ************************************************************* @@ -1852,8 +1842,6 @@ static void mipi_dsi_link_on(struct lcd_config_s *pconf) op_mode_init = dconf->operation_mode_init; op_mode_disp = dconf->operation_mode_display; - set_mipi_dsi_lpclk_ctrl(dconf, op_mode_init); - if (dconf->dsi_init_on) { dsi_write_cmd(dconf->dsi_init_on); LCDPR("dsi init on\n"); @@ -1881,7 +1869,6 @@ static void mipi_dsi_link_on(struct lcd_config_s *pconf) */ op_mode_disp, /* DSI operation mode, video or command */ pconf); - set_mipi_dsi_lpclk_ctrl(dconf, op_mode_disp); } } @@ -1907,7 +1894,6 @@ void mipi_dsi_link_off(struct lcd_config_s *pconf) */ op_mode_init, /* DSI operation mode, video or command */ pconf); - set_mipi_dsi_lpclk_ctrl(dconf, op_mode_init); } #ifdef CONFIG_AMLOGIC_LCD_EXTERN @@ -2075,8 +2061,10 @@ static void mipi_dsi_host_on(struct lcd_config_s *pconf) 0, /* Chroma sub sample, only for YUV 422 or 420, even or odd */ op_mode_init, /* DSI operation mode, video or command */ pconf); - set_dsi_phy_config(pconf); + set_dsi_phy_config(pconf->lcd_control.mipi_config); + /* Startup transfer */ + mipi_dsi_lpclk_ctrl(pconf->lcd_control.mipi_config); mipi_dsi_link_on(pconf); if (lcd_debug_print_flag) -- 2.7.4