From 0c05bdfd09ea5e01e5d8e6de1260ef43446ab15f Mon Sep 17 00:00:00 2001 From: pcc Date: Thu, 26 Mar 2015 04:40:51 -0700 Subject: [PATCH] Use a different variant of CpuFeatures::FlushICache asm with clang. This variant avoids a constant pool entry, which can be problematic when LTO'ing. It is also slightly shorter. R=bmeurer@chromium.org,Jacob.Bramley@arm.com BUG=chromium:453195 LOG=n Review URL: https://codereview.chromium.org/986643004 Cr-Commit-Position: refs/heads/master@{#27474} --- src/arm/cpu-arm.cc | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/arm/cpu-arm.cc b/src/arm/cpu-arm.cc index 4a34070..4bbfd37 100644 --- a/src/arm/cpu-arm.cc +++ b/src/arm/cpu-arm.cc @@ -45,6 +45,18 @@ void CpuFeatures::FlushICache(void* start, size_t size) { register uint32_t end asm("r1") = beg + size; register uint32_t flg asm("r2") = 0; +#ifdef __clang__ + // This variant of the asm avoids a constant pool entry, which can be + // problematic when LTO'ing. It is also slightly shorter. + register uint32_t scno asm("r7") = __ARM_NR_cacheflush; + + asm volatile("svc 0\n" + : + : "r"(beg), "r"(end), "r"(flg), "r"(scno) + : "memory"); +#else + // Use a different variant of the asm with GCC because some versions doesn't + // support r7 as an asm input. asm volatile( // This assembly works for both ARM and Thumb targets. @@ -62,6 +74,7 @@ void CpuFeatures::FlushICache(void* start, size_t size) { : "r" (beg), "r" (end), "r" (flg), [scno] "i" (__ARM_NR_cacheflush) : "memory"); #endif +#endif } } } // namespace v8::internal -- 2.7.4