From 0bf3e6fae7f82b4f16fbcbb05a1ae47f7930e189 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Nicolai=20H=C3=A4hnle?= Date: Thu, 30 Aug 2018 17:06:52 +0200 Subject: [PATCH] radeonsi/gfx10: double the number of tessellation offchip buffers per SE Each gfx10 shader engine corresponds to two gfx9 shader engines, so scale the number of offchip buffers accordingly. Acked-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_pipe.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 7eaa400..c2cee02 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -1031,9 +1031,11 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws, */ unsigned max_offchip_buffers_per_se; + if (sscreen->info.chip_class >= GFX10) + max_offchip_buffers_per_se = 256; /* Only certain chips can use the maximum value. */ - if (sscreen->info.family == CHIP_VEGA12 || - sscreen->info.family == CHIP_VEGA20) + else if (sscreen->info.family == CHIP_VEGA12 || + sscreen->info.family == CHIP_VEGA20) max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64; else max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63; -- 2.7.4