From 0badd8f613fb6f505a059ea530fcbfb78947c00e Mon Sep 17 00:00:00 2001 From: Christopher Tetreault Date: Tue, 14 Apr 2020 10:34:35 -0700 Subject: [PATCH] [SVE] Remove calls to getBitWidth from ARM Reviewers: efriedma Reviewed By: efriedma Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D77904 --- llvm/lib/Target/ARM/ARMISelLowering.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 248c6ce..4807148 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -17584,7 +17584,7 @@ bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx, return false; assert(VectorTy->isVectorTy() && "VectorTy is not a vector type"); - unsigned BitWidth = cast(VectorTy)->getBitWidth(); + unsigned BitWidth = VectorTy->getPrimitiveSizeInBits().getFixedSize(); // We can do a store + vector extract on any vector that fits perfectly in a D // or Q register. if (BitWidth == 64 || BitWidth == 128) { @@ -18081,11 +18081,11 @@ static bool isHomogeneousAggregate(Type *Ty, HABaseType &Base, case HA_DOUBLE: return false; case HA_VECT64: - return VT->getBitWidth() == 64; + return VT->getPrimitiveSizeInBits().getFixedSize() == 64; case HA_VECT128: - return VT->getBitWidth() == 128; + return VT->getPrimitiveSizeInBits().getFixedSize() == 128; case HA_UNKNOWN: - switch (VT->getBitWidth()) { + switch (VT->getPrimitiveSizeInBits().getFixedSize()) { case 64: Base = HA_VECT64; return true; -- 2.7.4