From 0b92f897120c2fe70a37a108c6bed4b6468061bb Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Fri, 13 Mar 2020 10:48:02 +0100 Subject: [PATCH] net: phy: mscc: fix header defines and descriptions Cosmetic commit fixing the MSCC PHY header defines and descriptions, which were referring the to MSCC Ocelot MAC driver (see drivers/net/ethernet/mscc/). Signed-off-by: Antoine Tenart Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller --- drivers/net/phy/mscc/mscc_fc_buffer.h | 8 ++++---- drivers/net/phy/mscc/mscc_mac.h | 8 ++++---- drivers/net/phy/mscc/mscc_macsec.h | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/net/phy/mscc/mscc_fc_buffer.h b/drivers/net/phy/mscc/mscc_fc_buffer.h index 7e9c0e8..3803e82 100644 --- a/drivers/net/phy/mscc/mscc_fc_buffer.h +++ b/drivers/net/phy/mscc/mscc_fc_buffer.h @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* - * Microsemi Ocelot Switch driver + * Driver for Microsemi VSC85xx PHYs * * Copyright (C) 2019 Microsemi Corporation */ -#ifndef _MSCC_OCELOT_FC_BUFFER_H_ -#define _MSCC_OCELOT_FC_BUFFER_H_ +#ifndef _MSCC_PHY_FC_BUFFER_H_ +#define _MSCC_PHY_FC_BUFFER_H_ #define MSCC_FCBUF_ENA_CFG 0x00 #define MSCC_FCBUF_MODE_CFG 0x01 @@ -61,4 +61,4 @@ #define MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH(x) ((x) << 16) #define MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH_M GENMASK(31, 16) -#endif +#endif /* _MSCC_PHY_FC_BUFFER_H_ */ diff --git a/drivers/net/phy/mscc/mscc_mac.h b/drivers/net/phy/mscc/mscc_mac.h index 9420ee5..fcb5ba5 100644 --- a/drivers/net/phy/mscc/mscc_mac.h +++ b/drivers/net/phy/mscc/mscc_mac.h @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* - * Microsemi Ocelot Switch driver + * Driver for Microsemi VSC85xx PHYs * * Copyright (c) 2017 Microsemi Corporation */ -#ifndef _MSCC_OCELOT_LINE_MAC_H_ -#define _MSCC_OCELOT_LINE_MAC_H_ +#ifndef _MSCC_PHY_LINE_MAC_H_ +#define _MSCC_PHY_LINE_MAC_H_ #define MSCC_MAC_CFG_ENA_CFG 0x00 #define MSCC_MAC_CFG_MODE_CFG 0x01 @@ -156,4 +156,4 @@ #define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(x) (x) #define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M GENMASK(2, 0) -#endif /* _MSCC_OCELOT_LINE_MAC_H_ */ +#endif /* _MSCC_PHY_LINE_MAC_H_ */ diff --git a/drivers/net/phy/mscc/mscc_macsec.h b/drivers/net/phy/mscc/mscc_macsec.h index c606c9a..d078394 100644 --- a/drivers/net/phy/mscc/mscc_macsec.h +++ b/drivers/net/phy/mscc/mscc_macsec.h @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* - * Microsemi Ocelot Switch driver + * Driver for Microsemi VSC85xx PHYs * * Copyright (c) 2018 Microsemi Corporation */ -#ifndef _MSCC_OCELOT_MACSEC_H_ -#define _MSCC_OCELOT_MACSEC_H_ +#ifndef _MSCC_PHY_MACSEC_H_ +#define _MSCC_PHY_MACSEC_H_ #include @@ -321,4 +321,4 @@ struct macsec_flow { #define MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE_M GENMASK(31, 16) #define MACSEC_INTR_CTRL_STATUS_ROLLOVER BIT(5) -#endif +#endif /* _MSCC_PHY_MACSEC_H_ */ -- 2.7.4