From 0b74c840ddb09c71e15bb383d0aad3526db5fe72 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Sun, 7 Oct 2018 15:32:06 +0000 Subject: [PATCH] [DAGCombiner] allow undef elts in vector fabs/fneg matching This change is proposed as a part of D44548, but we need this independently to avoid regressions from improved undef propagation in SimplifyDemandedVectorElts(). llvm-svn: 343940 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +- llvm/test/CodeGen/X86/fp-logic.ll | 10 ++++------ 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index c91aa83..bf3236c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -9851,7 +9851,7 @@ static SDValue foldBitcastedFPLogic(SDNode *N, SelectionDAG &DAG, // Fold (bitcast int (and (bitcast fp X to int), 0x7fff...) to fp) -> fabs X // Fold (bitcast int (xor (bitcast fp X to int), 0x8000...) to fp) -> fneg X SDValue LogicOp0 = N0.getOperand(0); - ConstantSDNode *LogicOp1 = isConstOrConstSplat(N0.getOperand(1)); + ConstantSDNode *LogicOp1 = isConstOrConstSplat(N0.getOperand(1), true); if (LogicOp1 && LogicOp1->getAPIntValue() == SignMask && LogicOp0.getOpcode() == ISD::BITCAST && LogicOp0.getOperand(0).getValueType() == VT) diff --git a/llvm/test/CodeGen/X86/fp-logic.ll b/llvm/test/CodeGen/X86/fp-logic.ll index 59dbe7a..76a8eff 100644 --- a/llvm/test/CodeGen/X86/fp-logic.ll +++ b/llvm/test/CodeGen/X86/fp-logic.ll @@ -323,8 +323,7 @@ define <4 x float> @fadd_bitcast_fneg_vec(<4 x float> %x, <4 x float> %y) { define <4 x float> @fadd_bitcast_fneg_vec_undef_elts(<4 x float> %x, <4 x float> %y) { ; CHECK-LABEL: fadd_bitcast_fneg_vec_undef_elts: ; CHECK: # %bb.0: -; CHECK-NEXT: xorps {{.*}}(%rip), %xmm1 -; CHECK-NEXT: addps %xmm1, %xmm0 +; CHECK-NEXT: subps %xmm1, %xmm0 ; CHECK-NEXT: retq %bc1 = bitcast <4 x float> %y to <4 x i32> %xor = xor <4 x i32> %bc1, @@ -345,11 +344,10 @@ define <4 x float> @fsub_bitcast_fneg_vec(<4 x float> %x, <4 x float> %y) { ret <4 x float> %fsub } -define <4 x float> @fsub_bitcast_fneg_vec_elts(<4 x float> %x, <4 x float> %y) { -; CHECK-LABEL: fsub_bitcast_fneg_vec_elts: +define <4 x float> @fsub_bitcast_fneg_vec_undef_elts(<4 x float> %x, <4 x float> %y) { +; CHECK-LABEL: fsub_bitcast_fneg_vec_undef_elts: ; CHECK: # %bb.0: -; CHECK-NEXT: xorps {{.*}}(%rip), %xmm1 -; CHECK-NEXT: subps %xmm1, %xmm0 +; CHECK-NEXT: addps %xmm1, %xmm0 ; CHECK-NEXT: retq %bc1 = bitcast <4 x float> %y to <4 x i32> %xor = xor <4 x i32> %bc1, -- 2.7.4