From 0b6464efe3d367c316ff90df0a5bce609cd21134 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=EA=B9=80=EC=88=98=EC=A7=84/=EB=8F=99=EC=9E=91=EC=A0=9C?= =?utf8?q?=EC=96=B4Lab=28SR=29/Engineer/=EC=82=BC=EC=84=B1=EC=A0=84?= =?utf8?q?=EC=9E=90?= Date: Wed, 5 Sep 2018 17:24:12 +0900 Subject: [PATCH] [neurun] Enable compile option Wall/Wextra/Werror for backend modules (#2604) This commit enables compile option Wall/Wextra/Werror for backend modules. Signed-off-by: sjsujinkim --- include/util/kernel/IndexIterator.h | 8 ++++---- runtimes/neurun/src/backend/acl_cl/CMakeLists.txt | 2 ++ runtimes/neurun/src/backend/acl_cl/InitializerGenerator.cc | 4 ++-- runtimes/neurun/src/backend/acl_cl/StageGenerator.cc | 3 +-- runtimes/neurun/src/backend/cpu/CMakeLists.txt | 2 ++ runtimes/neurun/src/backend/cpu/InitializerGenerator.cc | 6 +++--- runtimes/neurun/src/backend/cpu/StageGenerator.cc | 2 +- 7 files changed, 15 insertions(+), 12 deletions(-) diff --git a/include/util/kernel/IndexIterator.h b/include/util/kernel/IndexIterator.h index 7dab7d3..d016564 100644 --- a/include/util/kernel/IndexIterator.h +++ b/include/util/kernel/IndexIterator.h @@ -37,13 +37,13 @@ public: public: template IndexIterator &iter(Callable cb) { - for (uint32_t nth = 0; nth < _shape.N; ++nth) + for (int32_t nth = 0; nth < _shape.N; ++nth) { - for (uint32_t ch = 0; ch < _shape.C; ++ch) + for (int32_t ch = 0; ch < _shape.C; ++ch) { - for (uint32_t row = 0; row < _shape.H; ++row) + for (int32_t row = 0; row < _shape.H; ++row) { - for (uint32_t col = 0; col < _shape.W; ++col) + for (int32_t col = 0; col < _shape.W; ++col) { cb(nth, ch, row, col); } diff --git a/runtimes/neurun/src/backend/acl_cl/CMakeLists.txt b/runtimes/neurun/src/backend/acl_cl/CMakeLists.txt index 2a9fd66..d64c23a 100644 --- a/runtimes/neurun/src/backend/acl_cl/CMakeLists.txt +++ b/runtimes/neurun/src/backend/acl_cl/CMakeLists.txt @@ -10,6 +10,8 @@ target_link_libraries(${LIB_NEURUN_BACKEND_ACL_CL} arm_compute) target_link_libraries(${LIB_NEURUN_BACKEND_ACL_CL} nnfw_support_nnapi) target_link_libraries(${LIB_NEURUN_BACKEND_ACL_CL} ${LIB_NEURUN_KERNEL_ACL_CL}) +target_compile_options(${LIB_NEURUN_BACKEND_ACL_CL} PRIVATE -Wall -Wextra -Werror) + set_target_properties(${LIB_NEURUN_BACKEND_ACL_CL} PROPERTIES POSITION_INDEPENDENT_CODE ON) set_target_properties(${LIB_NEURUN_BACKEND_ACL_CL} PROPERTIES OUTPUT_NAME backend_acl_cl) install(TARGETS ${LIB_NEURUN_BACKEND_ACL_CL} DESTINATION lib/neurun) diff --git a/runtimes/neurun/src/backend/acl_cl/InitializerGenerator.cc b/runtimes/neurun/src/backend/acl_cl/InitializerGenerator.cc index 5804827..bf9876c 100644 --- a/runtimes/neurun/src/backend/acl_cl/InitializerGenerator.cc +++ b/runtimes/neurun/src/backend/acl_cl/InitializerGenerator.cc @@ -87,7 +87,7 @@ Initializer InitializerGenerator::generateBias(const graph::operation::Conv2D::I const auto bias_size = _ctx.at(bias_index).shape().asVector(); return [bias_base, bias_size](::arm_compute::ITensor &tensor) { - for (uint32_t n = 0; n < bias_size; ++n) + for (int32_t n = 0; n < bias_size; ++n) { const ::arm_compute::Coordinates coordinate{n}; @@ -109,7 +109,7 @@ Initializer InitializerGenerator::generateBias(const graph::operation::FullyConn const auto bias_size = _ctx.at(bias_index).shape().asVector(); return [bias_base, bias_size](::arm_compute::ITensor &tensor) { - for (uint32_t n = 0; n < bias_size; ++n) + for (int32_t n = 0; n < bias_size; ++n) { const ::arm_compute::Coordinates coordinate{n}; diff --git a/runtimes/neurun/src/backend/acl_cl/StageGenerator.cc b/runtimes/neurun/src/backend/acl_cl/StageGenerator.cc index 2fda73f..ca76447 100644 --- a/runtimes/neurun/src/backend/acl_cl/StageGenerator.cc +++ b/runtimes/neurun/src/backend/acl_cl/StageGenerator.cc @@ -120,7 +120,6 @@ Stage StageGenerator::generate(const graph::operation::Conv2D::Implicit::Node &n const auto ofm_shape = _ctx.at(ofm_index).shape().asFeature(); const auto ifm_shape = _ctx.at(ifm_index).shape().asFeature(); const auto ker_shape = _ctx.at(ker_index).shape().asKernel(); - const auto bias_size = _ctx.at(bias_index).shape().asVector(); const PaddingCode padding_type = static_cast(_ctx.at(padding_index).asScalar()); @@ -512,7 +511,7 @@ Stage StageGenerator::generate(const graph::operation::Softmax::Node &node) }; } -Stage StageGenerator::generate(const graph::operation::NOP::Node &node) +Stage StageGenerator::generate(const graph::operation::NOP::Node & /* node */) { // DO NOTHING return nullptr; diff --git a/runtimes/neurun/src/backend/cpu/CMakeLists.txt b/runtimes/neurun/src/backend/cpu/CMakeLists.txt index ba4efb1..95e9af6 100644 --- a/runtimes/neurun/src/backend/cpu/CMakeLists.txt +++ b/runtimes/neurun/src/backend/cpu/CMakeLists.txt @@ -12,6 +12,8 @@ target_link_libraries(${LIB_NEURUN_BACKEND_CPU} nnfw_util) target_link_libraries(${LIB_NEURUN_BACKEND_CPU} nnfw_support_nnapi) target_link_libraries(${LIB_NEURUN_BACKEND_CPU} ${LIB_NEURUN_KERNEL_CPU}) +target_compile_options(${LIB_NEURUN_BACKEND_CPU} PRIVATE -Wall -Wextra -Werror) + set_target_properties(${LIB_NEURUN_BACKEND_CPU} PROPERTIES POSITION_INDEPENDENT_CODE ON) set_target_properties(${LIB_NEURUN_BACKEND_CPU} PROPERTIES OUTPUT_NAME backend_cpu) install(TARGETS ${LIB_NEURUN_BACKEND_CPU} DESTINATION lib/neurun) diff --git a/runtimes/neurun/src/backend/cpu/InitializerGenerator.cc b/runtimes/neurun/src/backend/cpu/InitializerGenerator.cc index 05d2cc1..c524518 100644 --- a/runtimes/neurun/src/backend/cpu/InitializerGenerator.cc +++ b/runtimes/neurun/src/backend/cpu/InitializerGenerator.cc @@ -124,7 +124,7 @@ Initializer InitializerGenerator::generateBias(const graph::operation::Conv2D::I const auto bias_size = _ctx.at(bias_index).shape().asVector(); return [bias_base, bias_size](::arm_compute::ITensor &tensor) { - for (uint32_t n = 0; n < bias_size; ++n) + for (int32_t n = 0; n < bias_size; ++n) { const ::arm_compute::Coordinates coordinate{n}; @@ -151,7 +151,7 @@ Initializer InitializerGenerator::generateBias(const graph::operation::FullyConn case ::neurun::graph::operand::DataType::TENSOR_FLOAT32: { return [bias_base, bias_size](::arm_compute::ITensor &tensor) { - for (uint32_t n = 0; n < bias_size; ++n) + for (int32_t n = 0; n < bias_size; ++n) { const ::arm_compute::Coordinates coordinate{n}; @@ -167,7 +167,7 @@ Initializer InitializerGenerator::generateBias(const graph::operation::FullyConn case ::neurun::graph::operand::DataType::TENSOR_QUANT8_ASYMM: { return [bias_base, bias_size](::arm_compute::ITensor &tensor) { - for (uint32_t n = 0; n < bias_size; ++n) + for (int32_t n = 0; n < bias_size; ++n) { const ::arm_compute::Coordinates coordinate{n}; diff --git a/runtimes/neurun/src/backend/cpu/StageGenerator.cc b/runtimes/neurun/src/backend/cpu/StageGenerator.cc index def1e3c..6488a8d 100644 --- a/runtimes/neurun/src/backend/cpu/StageGenerator.cc +++ b/runtimes/neurun/src/backend/cpu/StageGenerator.cc @@ -509,7 +509,7 @@ Stage StageGenerator::generate(const graph::operation::Softmax::Node &node) }; } -Stage StageGenerator::generate(const graph::operation::NOP::Node &node) +Stage StageGenerator::generate(const graph::operation::NOP::Node & /* node */) { // DO NOTHING return nullptr; -- 2.7.4