From 0b4fdc81d15c1ff8acfe6fcdfcdd58a13fb3696e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 5 Dec 2005 01:11:20 +0000 Subject: [PATCH] add texrect support for r300 --- shared-core/r300_cmdbuf.c | 1 + shared-core/r300_reg.h | 1 + shared-core/radeon_drv.h | 3 ++- 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/shared-core/r300_cmdbuf.c b/shared-core/r300_cmdbuf.c index 623f1f4..475ce1d 100644 --- a/shared-core/r300_cmdbuf.c +++ b/shared-core/r300_cmdbuf.c @@ -211,6 +211,7 @@ void r300_init_reg_flags(void) ADD_RANGE(R300_TX_UNK1_0, 16); ADD_RANGE(R300_TX_SIZE_0, 16); ADD_RANGE(R300_TX_FORMAT_0, 16); + ADD_RANGE(R300_TX_PITCH_0, 16); /* Texture offset is dangerous and needs more checking */ ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET); ADD_RANGE(R300_TX_UNK4_0, 16); diff --git a/shared-core/r300_reg.h b/shared-core/r300_reg.h index c3e7ca3..8347131 100644 --- a/shared-core/r300_reg.h +++ b/shared-core/r300_reg.h @@ -801,6 +801,7 @@ I am fairly certain that they are correct unless stated otherwise in comments. # define R300_TX_FORMAT_YUV_MODE 0x00800000 +#define R300_TX_PITCH_0 0x4500 #define R300_TX_OFFSET_0 0x4540 /* BEGIN: Guess from R200 */ # define R300_TXO_ENDIAN_NO_SWAP (0 << 0) diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index bc9f3f2..1fdae23 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -87,10 +87,11 @@ R200_EMIT_PP_TXCTLALL_0-5 (replaces R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) * 1.19- Add support for gart table in FB memory and PCIE r300 + * 1.20- Add support for r300 texrect */ #define DRIVER_MAJOR 1 -#define DRIVER_MINOR 19 +#define DRIVER_MINOR 20 #define DRIVER_PATCHLEVEL 0 enum radeon_family { -- 2.7.4