From 0b01aebf5e658f3a9c026b194e7d60c0aa7066de Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 9 Nov 2022 11:16:00 -0800 Subject: [PATCH] [RISCV] Support BSET/BCLR/BINV in hasAllWUsers. These instructions set, clear, or invert a single bit. If their users don't use the upper 32 bits, they don't use the upper 32 bits of their input. Additionally the second operand BSET/BCLR/BINV is a shift amount which only uses 6 bits of the source. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D137452 --- llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp index 632f09c..d2e23a1 100644 --- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp +++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp @@ -139,6 +139,9 @@ static bool hasAllWUsers(const MachineInstr &OrigMI, MachineRegisterInfo &MRI) { break; case RISCV::SLL: + case RISCV::BSET: + case RISCV::BCLR: + case RISCV::BINV: // Operand 2 is the shift amount which uses 6 bits. if (OpIdx == 2) break; @@ -199,6 +202,9 @@ static bool hasAllWUsers(const MachineInstr &OrigMI, MachineRegisterInfo &MRI) { case RISCV::SH2ADD: case RISCV::SH3ADD: case RISCV::XNOR: + case RISCV::BSETI: + case RISCV::BCLRI: + case RISCV::BINVI: Worklist.push_back(UserMI); break; } -- 2.7.4