From 0ad83d222b0a4c3be676ca8708a4a565888b34fd Mon Sep 17 00:00:00 2001 From: Topi Pohjolainen Date: Fri, 1 Apr 2016 11:21:03 +0300 Subject: [PATCH] i965/blorp: Prepare sampling for gen9 v2 (Ken): Added switch cases for gen8/9 in texel_fetch(). These were wrongly introduced in blit-enabling patch. Signed-off-by: Topi Pohjolainen Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp index 444ba26..5243341 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp @@ -1629,12 +1629,19 @@ brw_blorp_blit_program::texel_fetch(struct brw_reg dst) SAMPLER_MESSAGE_ARG_U_INT, SAMPLER_MESSAGE_ARG_V_INT }; + static const sampler_message_arg gen9_ld_args[3] = { + SAMPLER_MESSAGE_ARG_U_INT, + SAMPLER_MESSAGE_ARG_V_INT, + SAMPLER_MESSAGE_ARG_ZERO_INT /* LOD */ + }; switch (brw->gen) { case 6: texture_lookup(dst, SHADER_OPCODE_TXF, gen6_args, s_is_zero ? 2 : 5); break; case 7: + case 8: + case 9: switch (key->tex_layout) { case INTEL_MSAA_LAYOUT_IMS: /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage @@ -1657,8 +1664,13 @@ brw_blorp_blit_program::texel_fetch(struct brw_reg dst) break; case INTEL_MSAA_LAYOUT_NONE: assert(s_is_zero); - texture_lookup(dst, SHADER_OPCODE_TXF, gen7_ld_args, - ARRAY_SIZE(gen7_ld_args)); + if (brw->gen < 9) { + texture_lookup(dst, SHADER_OPCODE_TXF, gen7_ld_args, + ARRAY_SIZE(gen7_ld_args)); + } else { + texture_lookup(dst, SHADER_OPCODE_TXF, gen9_ld_args, + ARRAY_SIZE(gen9_ld_args)); + } break; } break; -- 2.7.4