From 0a2b7b79fac8f66a881371728c6cf0f26959cb66 Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Thu, 27 Jun 2019 17:22:31 +0000 Subject: [PATCH] Revert "[CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 2)" *Appears* to break test-suite on http://lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/23790 FAIL: burg.execution_time FAIL: spiff.execution_time FAIL: employ.execution_time FAIL: llu.execution_time FAIL: gramschmidt.execution_time FAIL: fdtd-apml.execution_time This reverts commit r364563. llvm-svn: 364568 --- llvm/include/llvm/CodeGen/TargetLowering.h | 6 - llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 107 ---------------- llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll | 12 +- llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll | 20 ++- llvm/test/CodeGen/AArch64/urem-seteq.ll | 82 +++++++----- llvm/test/CodeGen/X86/jump_sign.ll | 10 +- ...ower-of-two-or-zero-when-comparing-with-zero.ll | 30 +++-- llvm/test/CodeGen/X86/urem-seteq-optsize.ll | 21 ++- llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll | 123 ++++++++++++------ llvm/test/CodeGen/X86/urem-seteq.ll | 141 ++++++++++++++------- 10 files changed, 288 insertions(+), 264 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index 3e6bb7d..cc23f58 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -4054,12 +4054,6 @@ private: SDValue N1, ISD::CondCode Cond, DAGCombinerInfo &DCI, const SDLoc &DL) const; - - SDValue prepareUREMEqFold(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, - DAGCombinerInfo &DCI, const SDLoc &DL, - SmallVectorImpl &Created) const; - SDValue buildUREMEqFold(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, - DAGCombinerInfo &DCI, const SDLoc &DL) const; }; /// Given an LLVM IR type and return type attributes, compute the return value diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 834cac0..0acac2b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -3460,18 +3460,6 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, return V; } - // Fold remainder of division by a constant. - if (N0.getOpcode() == ISD::UREM && N0.hasOneUse() && - (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { - AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes(); - - // When division is cheap or optimizing for minimum size, - // fall through to DIVREM creation by skipping this fold. - if (!isIntDivCheap(VT, Attr) && !Attr.hasFnAttribute(Attribute::MinSize)) - if (SDValue Folded = buildUREMEqFold(VT, N0, N1, Cond, DCI, dl)) - return Folded; - } - // Fold away ALL boolean setcc's. if (N0.getValueType().getScalarType() == MVT::i1 && foldBooleans) { SDValue Temp; @@ -4457,101 +4445,6 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, return DAG.getSelect(dl, VT, IsOne, N0, Q); } -/// Given an ISD::UREM used only by an ISD::SETEQ or ISD::SETNE -/// where the divisor is constant and the comparison target is zero, -/// return a DAG expression that will generate the same comparison result -/// using only multiplications, additions and shifts/rotations. -/// Ref: "Hacker's Delight" 10-17. -SDValue TargetLowering::buildUREMEqFold(EVT VT, SDValue REMNode, - SDValue CompNode, ISD::CondCode Cond, - DAGCombinerInfo &DCI, - const SDLoc &DL) const { - SmallVector Built; - if (SDValue Folded = - prepareUREMEqFold(VT, REMNode, CompNode, Cond, DCI, DL, Built)) { - for (SDNode *N : Built) - DCI.AddToWorklist(N); - return Folded; - } - - return SDValue(); -} - -SDValue -TargetLowering::prepareUREMEqFold(EVT VT, SDValue REMNode, SDValue CompNode, - ISD::CondCode Cond, DAGCombinerInfo &DCI, - const SDLoc &DL, - SmallVectorImpl &Created) const { - // fold (seteq/ne (urem N, D), 0) -> (setule/ugt (rotr (mul N, P), K), Q) - // - D must be constant with D = D0 * 2^K where D0 is odd and D0 != 1 - // - P is the multiplicative inverse of D0 modulo 2^W - // - Q = floor((2^W - 1) / D0) - // where W is the width of the common type of N and D. - assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && - "Only applicable for (in)equality comparisons."); - - EVT REMVT = REMNode->getValueType(0); - - // If MUL is unavailable, we cannot proceed in any case. - if (!isOperationLegalOrCustom(ISD::MUL, REMVT)) - return SDValue(); - - // TODO: Add non-uniform constant support. - ConstantSDNode *Divisor = isConstOrConstSplat(REMNode->getOperand(1)); - ConstantSDNode *CompTarget = isConstOrConstSplat(CompNode); - if (!Divisor || !CompTarget || Divisor->isNullValue() || - !CompTarget->isNullValue()) - return SDValue(); - - const APInt &D = Divisor->getAPIntValue(); - - // Decompose D into D0 * 2^K - unsigned K = D.countTrailingZeros(); - bool DivisorIsEven = (K != 0); - APInt D0 = D.lshr(K); - - // The fold is invalid when D0 == 1. - // This is reachable because visitSetCC happens before visitREM. - if (D0.isOneValue()) - return SDValue(); - - // P = inv(D0, 2^W) - // 2^W requires W + 1 bits, so we have to extend and then truncate. - unsigned W = D.getBitWidth(); - APInt P = D0.zext(W + 1) - .multiplicativeInverse(APInt::getHighBitsSet(W + 1, 1)) - .trunc(W); - - // Q = floor((2^W - 1) / D0) - APInt Q = APInt::getAllOnesValue(W).udiv(D0); - - SelectionDAG &DAG = DCI.DAG; - - SDValue PVal = DAG.getConstant(P, DL, REMVT); - SDValue QVal = DAG.getConstant(Q, DL, REMVT); - // (mul N, P) - SDValue Op1 = DAG.getNode(ISD::MUL, DL, REMVT, REMNode->getOperand(0), PVal); - Created.push_back(Op1.getNode()); - - // Rotate right only if D was even. - if (DivisorIsEven) { - // We need ROTR to do this. - if (!isOperationLegalOrCustom(ISD::ROTR, REMVT)) - return SDValue(); - SDValue ShAmt = - DAG.getConstant(K, DL, getShiftAmountTy(REMVT, DAG.getDataLayout())); - SDNodeFlags Flags; - Flags.setExact(true); - // UREM: (rotr (mul N, P), K) - Op1 = DAG.getNode(ISD::ROTR, DL, REMVT, Op1, ShAmt, Flags); - Created.push_back(Op1.getNode()); - } - - // UREM: (setule/setugt (rotr (mul N, P), K), Q) - return DAG.getSetCC(DL, VT, Op1, QVal, - ((Cond == ISD::SETEQ) ? ISD::SETULE : ISD::SETUGT)); -} - bool TargetLowering:: verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const { if (!isa(Op.getOperand(0))) { diff --git a/llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll b/llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll index ea098ec..0d3f0fa 100644 --- a/llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll +++ b/llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll @@ -26,13 +26,13 @@ define i32 @test_optsize(i32 %X) optsize nounwind readnone { ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #52429 ; CHECK-NEXT: movk w8, #52428, lsl #16 -; CHECK-NEXT: mov w9, #13108 -; CHECK-NEXT: movk w9, #13107, lsl #16 -; CHECK-NEXT: mul w8, w0, w8 -; CHECK-NEXT: mov w10, #-10 -; CHECK-NEXT: cmp w8, w9 +; CHECK-NEXT: umull x8, w0, w8 +; CHECK-NEXT: lsr x8, x8, #34 +; CHECK-NEXT: add w8, w8, w8, lsl #2 +; CHECK-NEXT: mov w9, #-10 +; CHECK-NEXT: cmp w0, w8 ; CHECK-NEXT: mov w8, #42 -; CHECK-NEXT: csel w0, w8, w10, lo +; CHECK-NEXT: csel w0, w8, w9, eq ; CHECK-NEXT: ret %rem = urem i32 %X, 5 %cmp = icmp eq i32 %rem, 0 diff --git a/llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll b/llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll index 7621050..6f28581 100644 --- a/llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll +++ b/llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll @@ -9,9 +9,13 @@ define <4 x i32> @test_urem_odd_vec_i32(<4 x i32> %X) nounwind readnone { ; CHECK-NEXT: mov w8, #52429 ; CHECK-NEXT: movk w8, #52428, lsl #16 ; CHECK-NEXT: dup v2.4s, w8 -; CHECK-NEXT: movi v1.16b, #51 -; CHECK-NEXT: mul v0.4s, v0.4s, v2.4s -; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s +; CHECK-NEXT: umull2 v3.2d, v0.4s, v2.4s +; CHECK-NEXT: umull v2.2d, v0.2s, v2.2s +; CHECK-NEXT: uzp2 v2.4s, v2.4s, v3.4s +; CHECK-NEXT: movi v1.4s, #5 +; CHECK-NEXT: ushr v2.4s, v2.4s, #2 +; CHECK-NEXT: mls v0.4s, v2.4s, v1.4s +; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 ; CHECK-NEXT: movi v1.4s, #1 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret @@ -27,9 +31,13 @@ define <8 x i16> @test_urem_odd_vec_i16(<8 x i16> %X) nounwind readnone { ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #52429 ; CHECK-NEXT: dup v2.8h, w8 -; CHECK-NEXT: movi v1.16b, #51 -; CHECK-NEXT: mul v0.8h, v0.8h, v2.8h -; CHECK-NEXT: cmhs v0.8h, v1.8h, v0.8h +; CHECK-NEXT: umull2 v3.4s, v0.8h, v2.8h +; CHECK-NEXT: umull v2.4s, v0.4h, v2.4h +; CHECK-NEXT: uzp2 v2.8h, v2.8h, v3.8h +; CHECK-NEXT: movi v1.8h, #5 +; CHECK-NEXT: ushr v2.8h, v2.8h, #2 +; CHECK-NEXT: mls v0.8h, v2.8h, v1.8h +; CHECK-NEXT: cmeq v0.8h, v0.8h, #0 ; CHECK-NEXT: movi v1.8h, #1 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/AArch64/urem-seteq.ll b/llvm/test/CodeGen/AArch64/urem-seteq.ll index 9b1b7a7..c5483a2 100644 --- a/llvm/test/CodeGen/AArch64/urem-seteq.ll +++ b/llvm/test/CodeGen/AArch64/urem-seteq.ll @@ -10,11 +10,11 @@ define i32 @test_urem_odd(i32 %X) nounwind readnone { ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #52429 ; CHECK-NEXT: movk w8, #52428, lsl #16 -; CHECK-NEXT: mov w9, #13108 -; CHECK-NEXT: mul w8, w0, w8 -; CHECK-NEXT: movk w9, #13107, lsl #16 -; CHECK-NEXT: cmp w8, w9 -; CHECK-NEXT: cset w0, lo +; CHECK-NEXT: umull x8, w0, w8 +; CHECK-NEXT: lsr x8, x8, #34 +; CHECK-NEXT: add w8, w8, w8, lsl #2 +; CHECK-NEXT: cmp w0, w8 +; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: ret %urem = urem i32 %X, 5 %cmp = icmp eq i32 %urem, 0 @@ -26,11 +26,14 @@ define i32 @test_urem_odd(i32 %X) nounwind readnone { define i32 @test_urem_odd_bit30(i32 %X) nounwind readnone { ; CHECK-LABEL: test_urem_odd_bit30: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #43691 -; CHECK-NEXT: movk w8, #27306, lsl #16 -; CHECK-NEXT: mul w8, w0, w8 -; CHECK-NEXT: cmp w8, #4 // =4 -; CHECK-NEXT: cset w0, lo +; CHECK-NEXT: mov w8, #-11 +; CHECK-NEXT: umull x8, w0, w8 +; CHECK-NEXT: mov w9, #3 +; CHECK-NEXT: lsr x8, x8, #62 +; CHECK-NEXT: movk w9, #16384, lsl #16 +; CHECK-NEXT: msub w8, w8, w9, w0 +; CHECK-NEXT: cmp w8, #0 // =0 +; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: ret %urem = urem i32 %X, 1073741827 %cmp = icmp eq i32 %urem, 0 @@ -42,11 +45,14 @@ define i32 @test_urem_odd_bit30(i32 %X) nounwind readnone { define i32 @test_urem_odd_bit31(i32 %X) nounwind readnone { ; CHECK-LABEL: test_urem_odd_bit31: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #43691 -; CHECK-NEXT: movk w8, #10922, lsl #16 -; CHECK-NEXT: mul w8, w0, w8 -; CHECK-NEXT: cmp w8, #2 // =2 -; CHECK-NEXT: cset w0, lo +; CHECK-NEXT: mov w8, w0 +; CHECK-NEXT: lsl x9, x8, #30 +; CHECK-NEXT: sub x8, x9, x8 +; CHECK-NEXT: lsr x8, x8, #61 +; CHECK-NEXT: mov w9, #-2147483645 +; CHECK-NEXT: msub w8, w8, w9, w0 +; CHECK-NEXT: cmp w8, #0 // =0 +; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: ret %urem = urem i32 %X, 2147483651 %cmp = icmp eq i32 %urem, 0 @@ -63,15 +69,16 @@ define i32 @test_urem_odd_bit31(i32 %X) nounwind readnone { define i16 @test_urem_even(i16 %X) nounwind readnone { ; CHECK-LABEL: test_urem_even: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w9, #28087 +; CHECK-NEXT: mov w10, #9363 +; CHECK-NEXT: ubfx w9, w0, #1, #15 +; CHECK-NEXT: movk w10, #37449, lsl #16 +; CHECK-NEXT: umull x9, w9, w10 ; CHECK-NEXT: and w8, w0, #0xffff -; CHECK-NEXT: movk w9, #46811, lsl #16 -; CHECK-NEXT: mul w8, w8, w9 -; CHECK-NEXT: mov w9, #18724 -; CHECK-NEXT: ror w8, w8, #1 -; CHECK-NEXT: movk w9, #9362, lsl #16 -; CHECK-NEXT: cmp w8, w9 -; CHECK-NEXT: cset w0, hi +; CHECK-NEXT: lsr x9, x9, #34 +; CHECK-NEXT: mov w10, #14 +; CHECK-NEXT: msub w8, w9, w10, w8 +; CHECK-NEXT: cmp w8, #0 // =0 +; CHECK-NEXT: cset w0, ne ; CHECK-NEXT: ret %urem = urem i16 %X, 14 %cmp = icmp ne i16 %urem, 0 @@ -83,12 +90,14 @@ define i16 @test_urem_even(i16 %X) nounwind readnone { define i32 @test_urem_even_bit30(i32 %X) nounwind readnone { ; CHECK-LABEL: test_urem_even_bit30: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #20165 -; CHECK-NEXT: movk w8, #64748, lsl #16 -; CHECK-NEXT: mul w8, w0, w8 -; CHECK-NEXT: ror w8, w8, #3 -; CHECK-NEXT: cmp w8, #32 // =32 -; CHECK-NEXT: cset w0, lo +; CHECK-NEXT: mov w8, #-415 +; CHECK-NEXT: umull x8, w0, w8 +; CHECK-NEXT: mov w9, #104 +; CHECK-NEXT: lsr x8, x8, #62 +; CHECK-NEXT: movk w9, #16384, lsl #16 +; CHECK-NEXT: msub w8, w8, w9, w0 +; CHECK-NEXT: cmp w8, #0 // =0 +; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: ret %urem = urem i32 %X, 1073741928 %cmp = icmp eq i32 %urem, 0 @@ -100,12 +109,15 @@ define i32 @test_urem_even_bit30(i32 %X) nounwind readnone { define i32 @test_urem_even_bit31(i32 %X) nounwind readnone { ; CHECK-LABEL: test_urem_even_bit31: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #64251 -; CHECK-NEXT: movk w8, #47866, lsl #16 -; CHECK-NEXT: mul w8, w0, w8 -; CHECK-NEXT: ror w8, w8, #1 -; CHECK-NEXT: cmp w8, #4 // =4 -; CHECK-NEXT: cset w0, lo +; CHECK-NEXT: mov w8, #65435 +; CHECK-NEXT: movk w8, #32767, lsl #16 +; CHECK-NEXT: umull x8, w0, w8 +; CHECK-NEXT: mov w9, #102 +; CHECK-NEXT: lsr x8, x8, #62 +; CHECK-NEXT: movk w9, #32768, lsl #16 +; CHECK-NEXT: msub w8, w8, w9, w0 +; CHECK-NEXT: cmp w8, #0 // =0 +; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: ret %urem = urem i32 %X, 2147483750 %cmp = icmp eq i32 %urem, 0 diff --git a/llvm/test/CodeGen/X86/jump_sign.ll b/llvm/test/CodeGen/X86/jump_sign.ll index a4dc7a0..5243546 100644 --- a/llvm/test/CodeGen/X86/jump_sign.ll +++ b/llvm/test/CodeGen/X86/jump_sign.ll @@ -236,11 +236,13 @@ define void @func_o() nounwind uwtable { ; CHECK-NEXT: jne .LBB12_8 ; CHECK-NEXT: # %bb.4: # %if.end29 ; CHECK-NEXT: movzwl (%eax), %eax -; CHECK-NEXT: imull $-13107, %eax, %eax # imm = 0xCCCD -; CHECK-NEXT: rorw %ax ; CHECK-NEXT: movzwl %ax, %eax -; CHECK-NEXT: cmpl $13108, %eax # imm = 0x3334 -; CHECK-NEXT: jae .LBB12_5 +; CHECK-NEXT: imull $52429, %eax, %ecx # imm = 0xCCCD +; CHECK-NEXT: shrl $18, %ecx +; CHECK-NEXT: andl $-2, %ecx +; CHECK-NEXT: leal (%ecx,%ecx,4), %ecx +; CHECK-NEXT: cmpw %cx, %ax +; CHECK-NEXT: jne .LBB12_5 ; CHECK-NEXT: .LBB12_8: # %if.then44 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al diff --git a/llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll b/llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll index c160807..ac3ec5e 100644 --- a/llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll +++ b/llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll @@ -40,12 +40,16 @@ define i1 @p2_scalar_shifted_urem_by_const(i32 %x, i32 %y) { ; CHECK-LABEL: p2_scalar_shifted_urem_by_const: ; CHECK: # %bb.0: ; CHECK-NEXT: movl %esi, %ecx +; CHECK-NEXT: # kill: def $edi killed $edi def $rdi ; CHECK-NEXT: andl $1, %edi ; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx ; CHECK-NEXT: shll %cl, %edi -; CHECK-NEXT: imull $-1431655765, %edi, %eax # imm = 0xAAAAAAAB -; CHECK-NEXT: cmpl $1431655766, %eax # imm = 0x55555556 -; CHECK-NEXT: setb %al +; CHECK-NEXT: movl $2863311531, %eax # imm = 0xAAAAAAAB +; CHECK-NEXT: imulq %rdi, %rax +; CHECK-NEXT: shrq $33, %rax +; CHECK-NEXT: leal (%rax,%rax,2), %eax +; CHECK-NEXT: cmpl %eax, %edi +; CHECK-NEXT: sete %al ; CHECK-NEXT: retq %t0 = and i32 %x, 1 ; clearly a power-of-two or zero %t1 = shl i32 %t0, %y ; will still be a power-of-two or zero with any %y @@ -58,12 +62,16 @@ define i1 @p3_scalar_shifted2_urem_by_const(i32 %x, i32 %y) { ; CHECK-LABEL: p3_scalar_shifted2_urem_by_const: ; CHECK: # %bb.0: ; CHECK-NEXT: movl %esi, %ecx +; CHECK-NEXT: # kill: def $edi killed $edi def $rdi ; CHECK-NEXT: andl $2, %edi ; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx ; CHECK-NEXT: shll %cl, %edi -; CHECK-NEXT: imull $-1431655765, %edi, %eax # imm = 0xAAAAAAAB -; CHECK-NEXT: cmpl $1431655766, %eax # imm = 0x55555556 -; CHECK-NEXT: setb %al +; CHECK-NEXT: movl $2863311531, %eax # imm = 0xAAAAAAAB +; CHECK-NEXT: imulq %rdi, %rax +; CHECK-NEXT: shrq $33, %rax +; CHECK-NEXT: leal (%rax,%rax,2), %eax +; CHECK-NEXT: cmpl %eax, %edi +; CHECK-NEXT: sete %al ; CHECK-NEXT: retq %t0 = and i32 %x, 2 ; clearly a power-of-two or zero %t1 = shl i32 %t0, %y ; will still be a power-of-two or zero with any %y @@ -202,10 +210,14 @@ define <4 x i1> @p8_vector_urem_by_const__nonsplat_undef3(<4 x i32> %x, <4 x i32 define i1 @n0_urem_of_maybe_not_power_of_two(i32 %x, i32 %y) { ; CHECK-LABEL: n0_urem_of_maybe_not_power_of_two: ; CHECK: # %bb.0: +; CHECK-NEXT: # kill: def $edi killed $edi def $rdi ; CHECK-NEXT: andl $3, %edi -; CHECK-NEXT: imull $-1431655765, %edi, %eax # imm = 0xAAAAAAAB -; CHECK-NEXT: cmpl $1431655766, %eax # imm = 0x55555556 -; CHECK-NEXT: setb %al +; CHECK-NEXT: movl $2863311531, %eax # imm = 0xAAAAAAAB +; CHECK-NEXT: imulq %rdi, %rax +; CHECK-NEXT: shrq $33, %rax +; CHECK-NEXT: leal (%rax,%rax,2), %eax +; CHECK-NEXT: cmpl %eax, %edi +; CHECK-NEXT: sete %al ; CHECK-NEXT: retq %t0 = and i32 %x, 3 ; up to two bits set, not power-of-two %t1 = urem i32 %t0, 3 diff --git a/llvm/test/CodeGen/X86/urem-seteq-optsize.ll b/llvm/test/CodeGen/X86/urem-seteq-optsize.ll index 54a90b8..9cc450b 100644 --- a/llvm/test/CodeGen/X86/urem-seteq-optsize.ll +++ b/llvm/test/CodeGen/X86/urem-seteq-optsize.ll @@ -47,10 +47,15 @@ define i32 @test_minsize(i32 %X) optsize minsize nounwind readnone { define i32 @test_optsize(i32 %X) optsize nounwind readnone { ; X86-LABEL: test_optsize: ; X86: # %bb.0: -; X86-NEXT: imull $-858993459, {{[0-9]+}}(%esp), %eax # imm = 0xCCCCCCCD -; X86-NEXT: cmpl $858993460, %eax # imm = 0x33333334 +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl $-858993459, %edx # imm = 0xCCCCCCCD +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: mull %edx +; X86-NEXT: shrl $2, %edx +; X86-NEXT: leal (%edx,%edx,4), %eax +; X86-NEXT: cmpl %eax, %ecx ; X86-NEXT: movl $42, %eax -; X86-NEXT: jb .LBB1_2 +; X86-NEXT: je .LBB1_2 ; X86-NEXT: # %bb.1: ; X86-NEXT: movl $-10, %eax ; X86-NEXT: .LBB1_2: @@ -58,11 +63,15 @@ define i32 @test_optsize(i32 %X) optsize nounwind readnone { ; ; X64-LABEL: test_optsize: ; X64: # %bb.0: -; X64-NEXT: imull $-858993459, %edi, %eax # imm = 0xCCCCCCCD -; X64-NEXT: cmpl $858993460, %eax # imm = 0x33333334 +; X64-NEXT: movl %edi, %eax +; X64-NEXT: movl $3435973837, %ecx # imm = 0xCCCCCCCD +; X64-NEXT: imulq %rax, %rcx +; X64-NEXT: shrq $34, %rcx +; X64-NEXT: leal (%rcx,%rcx,4), %eax +; X64-NEXT: cmpl %eax, %edi ; X64-NEXT: movl $42, %ecx ; X64-NEXT: movl $-10, %eax -; X64-NEXT: cmovbl %ecx, %eax +; X64-NEXT: cmovel %ecx, %eax ; X64-NEXT: retq %rem = urem i32 %X, 5 %cmp = icmp eq i32 %rem, 0 diff --git a/llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll b/llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll index bc96920..22fc26e 100644 --- a/llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll +++ b/llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll @@ -11,48 +11,84 @@ define <4 x i32> @test_urem_odd_vec_i32(<4 x i32> %X) nounwind readnone { ; CHECK-SSE2-LABEL: test_urem_odd_vec_i32: ; CHECK-SSE2: # %bb.0: ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [3435973837,3435973837,3435973837,3435973837] -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] -; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0 -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2 -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3] -; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0 -; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0 -; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0 +; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3] +; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] +; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3 +; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3] +; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] +; CHECK-SSE2-NEXT: psrld $2, %xmm2 +; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm1 +; CHECK-SSE2-NEXT: pslld $2, %xmm1 +; CHECK-SSE2-NEXT: paddd %xmm2, %xmm1 +; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 +; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 +; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: retq ; ; CHECK-SSE41-LABEL: test_urem_odd_vec_i32: ; CHECK-SSE41: # %bb.0: -; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0 -; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,858993459,858993459,858993459] -; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1 +; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] +; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = [3435973837,3435973837,3435973837,3435973837] +; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm1 +; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm2 +; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] +; CHECK-SSE41-NEXT: psrld $2, %xmm2 +; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm2 +; CHECK-SSE41-NEXT: psubd %xmm2, %xmm0 +; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: retq ; ; CHECK-AVX1-LABEL: test_urem_odd_vec_i32: ; CHECK-AVX1: # %bb.0: -; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0 -; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1 +; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] +; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [3435973837,3435973837,3435973837,3435973837] +; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm1, %xmm1 +; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm0, %xmm2 +; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] +; CHECK-AVX1-NEXT: vpsrld $2, %xmm1, %xmm1 +; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1 +; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 +; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: retq ; ; CHECK-AVX2-LABEL: test_urem_odd_vec_i32: ; CHECK-AVX2: # %bb.0: -; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [3435973837,3435973837,3435973837,3435973837] -; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0 -; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [858993459,858993459,858993459,858993459] -; CHECK-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm1 +; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] +; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [3435973837,3435973837,3435973837,3435973837] +; CHECK-AVX2-NEXT: vpmuludq %xmm2, %xmm1, %xmm1 +; CHECK-AVX2-NEXT: vpmuludq %xmm2, %xmm0, %xmm2 +; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3] +; CHECK-AVX2-NEXT: vpsrld $2, %xmm1, %xmm1 +; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [5,5,5,5] +; CHECK-AVX2-NEXT: vpmulld %xmm2, %xmm1, %xmm1 +; CHECK-AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX2-NEXT: retq ; ; CHECK-AVX512VL-LABEL: test_urem_odd_vec_i32: ; CHECK-AVX512VL: # %bb.0: -; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0 -; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm1 +; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] +; CHECK-AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm2 = [3435973837,3435973837,3435973837,3435973837] +; CHECK-AVX512VL-NEXT: vpmuludq %xmm2, %xmm1, %xmm1 +; CHECK-AVX512VL-NEXT: vpmuludq %xmm2, %xmm0, %xmm2 +; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3] +; CHECK-AVX512VL-NEXT: vpsrld $2, %xmm1, %xmm1 +; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm1, %xmm1 +; CHECK-AVX512VL-NEXT: vpsubd %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX512VL-NEXT: retq @@ -64,28 +100,25 @@ define <4 x i32> @test_urem_odd_vec_i32(<4 x i32> %X) nounwind readnone { ; Like test_urem_odd_vec_i32, but with 8 x i16 vectors. define <8 x i16> @test_urem_odd_vec_i16(<8 x i16> %X) nounwind readnone { -; CHECK-SSE2-LABEL: test_urem_odd_vec_i16: -; CHECK-SSE2: # %bb.0: -; CHECK-SSE2-NEXT: pmullw {{.*}}(%rip), %xmm0 -; CHECK-SSE2-NEXT: psubusw {{.*}}(%rip), %xmm0 -; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 -; CHECK-SSE2-NEXT: pcmpeqw %xmm1, %xmm0 -; CHECK-SSE2-NEXT: psrlw $15, %xmm0 -; CHECK-SSE2-NEXT: retq -; -; CHECK-SSE41-LABEL: test_urem_odd_vec_i16: -; CHECK-SSE41: # %bb.0: -; CHECK-SSE41-NEXT: pmullw {{.*}}(%rip), %xmm0 -; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [13107,13107,13107,13107,13107,13107,13107,13107] -; CHECK-SSE41-NEXT: pminuw %xmm0, %xmm1 -; CHECK-SSE41-NEXT: pcmpeqw %xmm1, %xmm0 -; CHECK-SSE41-NEXT: psrlw $15, %xmm0 -; CHECK-SSE41-NEXT: retq +; CHECK-SSE-LABEL: test_urem_odd_vec_i16: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: movdqa {{.*#+}} xmm1 = [52429,52429,52429,52429,52429,52429,52429,52429] +; CHECK-SSE-NEXT: pmulhuw %xmm0, %xmm1 +; CHECK-SSE-NEXT: psrlw $2, %xmm1 +; CHECK-SSE-NEXT: pmullw {{.*}}(%rip), %xmm1 +; CHECK-SSE-NEXT: psubw %xmm1, %xmm0 +; CHECK-SSE-NEXT: pxor %xmm1, %xmm1 +; CHECK-SSE-NEXT: pcmpeqw %xmm1, %xmm0 +; CHECK-SSE-NEXT: psrlw $15, %xmm0 +; CHECK-SSE-NEXT: retq ; ; CHECK-AVX-LABEL: test_urem_odd_vec_i16: ; CHECK-AVX: # %bb.0: -; CHECK-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 -; CHECK-AVX-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm1 +; CHECK-AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1 +; CHECK-AVX-NEXT: vpsrlw $2, %xmm1, %xmm1 +; CHECK-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1 +; CHECK-AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; CHECK-AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 ; CHECK-AVX-NEXT: vpsrlw $15, %xmm0, %xmm0 ; CHECK-AVX-NEXT: retq @@ -181,9 +214,17 @@ define <4 x i32> @test_urem_even_vec_i32(<4 x i32> %X) nounwind readnone { ; ; CHECK-AVX512VL-LABEL: test_urem_even_vec_i32: ; CHECK-AVX512VL: # %bb.0: -; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0 -; CHECK-AVX512VL-NEXT: vprord $1, %xmm0, %xmm0 -; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm1 +; CHECK-AVX512VL-NEXT: vpsrld $1, %xmm0, %xmm1 +; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] +; CHECK-AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm3 = [2454267027,2454267027,2454267027,2454267027] +; CHECK-AVX512VL-NEXT: vpmuludq %xmm3, %xmm2, %xmm2 +; CHECK-AVX512VL-NEXT: vpmuludq %xmm3, %xmm1, %xmm1 +; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3] +; CHECK-AVX512VL-NEXT: vpsrld $2, %xmm1, %xmm1 +; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm1, %xmm1 +; CHECK-AVX512VL-NEXT: vpsubd %xmm1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX512VL-NEXT: retq diff --git a/llvm/test/CodeGen/X86/urem-seteq.ll b/llvm/test/CodeGen/X86/urem-seteq.ll index 71dc5c7..469c985 100644 --- a/llvm/test/CodeGen/X86/urem-seteq.ll +++ b/llvm/test/CodeGen/X86/urem-seteq.ll @@ -9,18 +9,27 @@ define i32 @test_urem_odd(i32 %X) nounwind readnone { ; X86-LABEL: test_urem_odd: ; X86: # %bb.0: -; X86-NEXT: imull $-858993459, {{[0-9]+}}(%esp), %ecx # imm = 0xCCCCCCCD +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl $-858993459, %edx # imm = 0xCCCCCCCD +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: mull %edx +; X86-NEXT: shrl $2, %edx +; X86-NEXT: leal (%edx,%edx,4), %edx ; X86-NEXT: xorl %eax, %eax -; X86-NEXT: cmpl $858993460, %ecx # imm = 0x33333334 -; X86-NEXT: setb %al +; X86-NEXT: cmpl %edx, %ecx +; X86-NEXT: sete %al ; X86-NEXT: retl ; ; X64-LABEL: test_urem_odd: ; X64: # %bb.0: -; X64-NEXT: imull $-858993459, %edi, %ecx # imm = 0xCCCCCCCD +; X64-NEXT: movl %edi, %eax +; X64-NEXT: movl $3435973837, %ecx # imm = 0xCCCCCCCD +; X64-NEXT: imulq %rax, %rcx +; X64-NEXT: shrq $34, %rcx +; X64-NEXT: leal (%rcx,%rcx,4), %ecx ; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpl $858993460, %ecx # imm = 0x33333334 -; X64-NEXT: setb %al +; X64-NEXT: cmpl %ecx, %edi +; X64-NEXT: sete %al ; X64-NEXT: retq %urem = urem i32 %X, 5 %cmp = icmp eq i32 %urem, 0 @@ -32,18 +41,27 @@ define i32 @test_urem_odd(i32 %X) nounwind readnone { define i32 @test_urem_odd_bit30(i32 %X) nounwind readnone { ; X86-LABEL: test_urem_odd_bit30: ; X86: # %bb.0: -; X86-NEXT: imull $1789569707, {{[0-9]+}}(%esp), %ecx # imm = 0x6AAAAAAB +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl $-11, %edx +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: mull %edx +; X86-NEXT: shrl $30, %edx +; X86-NEXT: imull $1073741827, %edx, %edx # imm = 0x40000003 ; X86-NEXT: xorl %eax, %eax -; X86-NEXT: cmpl $4, %ecx -; X86-NEXT: setb %al +; X86-NEXT: cmpl %edx, %ecx +; X86-NEXT: sete %al ; X86-NEXT: retl ; ; X64-LABEL: test_urem_odd_bit30: ; X64: # %bb.0: -; X64-NEXT: imull $1789569707, %edi, %ecx # imm = 0x6AAAAAAB +; X64-NEXT: movl %edi, %eax +; X64-NEXT: movl $4294967285, %ecx # imm = 0xFFFFFFF5 +; X64-NEXT: imulq %rax, %rcx +; X64-NEXT: shrq $62, %rcx +; X64-NEXT: imull $1073741827, %ecx, %ecx # imm = 0x40000003 ; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpl $4, %ecx -; X64-NEXT: setb %al +; X64-NEXT: cmpl %ecx, %edi +; X64-NEXT: sete %al ; X64-NEXT: retq %urem = urem i32 %X, 1073741827 %cmp = icmp eq i32 %urem, 0 @@ -55,18 +73,28 @@ define i32 @test_urem_odd_bit30(i32 %X) nounwind readnone { define i32 @test_urem_odd_bit31(i32 %X) nounwind readnone { ; X86-LABEL: test_urem_odd_bit31: ; X86: # %bb.0: -; X86-NEXT: imull $715827883, {{[0-9]+}}(%esp), %ecx # imm = 0x2AAAAAAB +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl $1073741823, %edx # imm = 0x3FFFFFFF +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: mull %edx +; X86-NEXT: shrl $29, %edx +; X86-NEXT: imull $-2147483645, %edx, %edx # imm = 0x80000003 ; X86-NEXT: xorl %eax, %eax -; X86-NEXT: cmpl $2, %ecx -; X86-NEXT: setb %al +; X86-NEXT: cmpl %edx, %ecx +; X86-NEXT: sete %al ; X86-NEXT: retl ; ; X64-LABEL: test_urem_odd_bit31: ; X64: # %bb.0: -; X64-NEXT: imull $715827883, %edi, %ecx # imm = 0x2AAAAAAB +; X64-NEXT: movl %edi, %eax +; X64-NEXT: movq %rax, %rcx +; X64-NEXT: shlq $30, %rcx +; X64-NEXT: subq %rax, %rcx +; X64-NEXT: shrq $61, %rcx +; X64-NEXT: imull $-2147483645, %ecx, %ecx # imm = 0x80000003 ; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpl $2, %ecx -; X64-NEXT: setb %al +; X64-NEXT: cmpl %ecx, %edi +; X64-NEXT: sete %al ; X64-NEXT: retq %urem = urem i32 %X, 2147483651 %cmp = icmp eq i32 %urem, 0 @@ -83,23 +111,35 @@ define i32 @test_urem_odd_bit31(i32 %X) nounwind readnone { define i16 @test_urem_even(i16 %X) nounwind readnone { ; X86-LABEL: test_urem_even: ; X86: # %bb.0: -; X86-NEXT: imull $28087, {{[0-9]+}}(%esp), %eax # imm = 0x6DB7 -; X86-NEXT: rorw %ax -; X86-NEXT: movzwl %ax, %ecx +; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: shrl %eax +; X86-NEXT: imull $18725, %eax, %eax # imm = 0x4925 +; X86-NEXT: shrl $17, %eax +; X86-NEXT: movl %eax, %edx +; X86-NEXT: shll $4, %edx +; X86-NEXT: subl %eax, %edx +; X86-NEXT: subl %eax, %edx ; X86-NEXT: xorl %eax, %eax -; X86-NEXT: cmpl $9362, %ecx # imm = 0x2492 -; X86-NEXT: seta %al +; X86-NEXT: cmpw %dx, %cx +; X86-NEXT: setne %al ; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: retl ; ; X64-LABEL: test_urem_even: ; X64: # %bb.0: -; X64-NEXT: imull $28087, %edi, %eax # imm = 0x6DB7 -; X64-NEXT: rorw %ax -; X64-NEXT: movzwl %ax, %ecx +; X64-NEXT: movzwl %di, %ecx +; X64-NEXT: movl %ecx, %eax +; X64-NEXT: shrl %eax +; X64-NEXT: imull $18725, %eax, %eax # imm = 0x4925 +; X64-NEXT: shrl $17, %eax +; X64-NEXT: movl %eax, %edx +; X64-NEXT: shll $4, %edx +; X64-NEXT: subl %eax, %edx +; X64-NEXT: subl %eax, %edx ; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpl $9362, %ecx # imm = 0x2492 -; X64-NEXT: seta %al +; X64-NEXT: cmpw %dx, %cx +; X64-NEXT: setne %al ; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: retq %urem = urem i16 %X, 14 @@ -112,20 +152,27 @@ define i16 @test_urem_even(i16 %X) nounwind readnone { define i32 @test_urem_even_bit30(i32 %X) nounwind readnone { ; X86-LABEL: test_urem_even_bit30: ; X86: # %bb.0: -; X86-NEXT: imull $-51622203, {{[0-9]+}}(%esp), %ecx # imm = 0xFCEC4EC5 -; X86-NEXT: rorl $3, %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl $-415, %edx # imm = 0xFE61 +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: mull %edx +; X86-NEXT: shrl $30, %edx +; X86-NEXT: imull $1073741928, %edx, %edx # imm = 0x40000068 ; X86-NEXT: xorl %eax, %eax -; X86-NEXT: cmpl $32, %ecx -; X86-NEXT: setb %al +; X86-NEXT: cmpl %edx, %ecx +; X86-NEXT: sete %al ; X86-NEXT: retl ; ; X64-LABEL: test_urem_even_bit30: ; X64: # %bb.0: -; X64-NEXT: imull $-51622203, %edi, %ecx # imm = 0xFCEC4EC5 -; X64-NEXT: rorl $3, %ecx +; X64-NEXT: movl %edi, %eax +; X64-NEXT: movl $4294966881, %ecx # imm = 0xFFFFFE61 +; X64-NEXT: imulq %rax, %rcx +; X64-NEXT: shrq $62, %rcx +; X64-NEXT: imull $1073741928, %ecx, %ecx # imm = 0x40000068 ; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpl $32, %ecx -; X64-NEXT: setb %al +; X64-NEXT: cmpl %ecx, %edi +; X64-NEXT: sete %al ; X64-NEXT: retq %urem = urem i32 %X, 1073741928 %cmp = icmp eq i32 %urem, 0 @@ -137,20 +184,26 @@ define i32 @test_urem_even_bit30(i32 %X) nounwind readnone { define i32 @test_urem_even_bit31(i32 %X) nounwind readnone { ; X86-LABEL: test_urem_even_bit31: ; X86: # %bb.0: -; X86-NEXT: imull $-1157956869, {{[0-9]+}}(%esp), %ecx # imm = 0xBAFAFAFB -; X86-NEXT: rorl %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl $2147483547, %edx # imm = 0x7FFFFF9B +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: mull %edx +; X86-NEXT: shrl $30, %edx +; X86-NEXT: imull $-2147483546, %edx, %edx # imm = 0x80000066 ; X86-NEXT: xorl %eax, %eax -; X86-NEXT: cmpl $4, %ecx -; X86-NEXT: setb %al +; X86-NEXT: cmpl %edx, %ecx +; X86-NEXT: sete %al ; X86-NEXT: retl ; ; X64-LABEL: test_urem_even_bit31: ; X64: # %bb.0: -; X64-NEXT: imull $-1157956869, %edi, %ecx # imm = 0xBAFAFAFB -; X64-NEXT: rorl %ecx +; X64-NEXT: movl %edi, %eax +; X64-NEXT: imulq $2147483547, %rax, %rax # imm = 0x7FFFFF9B +; X64-NEXT: shrq $62, %rax +; X64-NEXT: imull $-2147483546, %eax, %ecx # imm = 0x80000066 ; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpl $4, %ecx -; X64-NEXT: setb %al +; X64-NEXT: cmpl %ecx, %edi +; X64-NEXT: sete %al ; X64-NEXT: retq %urem = urem i32 %X, 2147483750 %cmp = icmp eq i32 %urem, 0 -- 2.7.4