From 0988488ed461f5a862f23f9840e0750bef07f11c Mon Sep 17 00:00:00 2001
From: Anton Afanasyev <anton.a.afanasyev@gmail.com>
Date: Wed, 18 Aug 2021 09:09:05 +0300
Subject: [PATCH] [Test][AggressiveInstCombine] Add one more test for shift
 truncation

Add test for which `OrigBitWidth != SrcBitWidth`
(https://reviews.llvm.org/D108091#2950131)
---
 .../AggressiveInstCombine/trunc_shifts.ll          | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll b/llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll
index 3d8cae8..14a797d 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll
@@ -92,6 +92,36 @@ define i32 @shl_check_no_overflow(i32 %call62, i16 %call63) {
   ret i32 %conv68
 }
 
+define i16 @shl_smaller_bitwidth(i8 %x) {
+; CHECK-LABEL: @shl_smaller_bitwidth(
+; CHECK-NEXT:    [[ZEXT:%.*]] = zext i8 [[X:%.*]] to i16
+; CHECK-NEXT:    [[SHL:%.*]] = shl i16 [[ZEXT]], 1
+; CHECK-NEXT:    [[AND:%.*]] = and i16 [[SHL]], 42
+; CHECK-NEXT:    ret i16 [[AND]]
+;
+  %zext = zext i8 %x to i16
+  %shl = shl i16 %zext, 1
+  %zext2 = zext i16 %shl to i32
+  %and = and i32 %zext2, 42
+  %trunc = trunc i32 %and to i16
+  ret i16 %trunc
+}
+
+define i16 @shl_larger_bitwidth(i8 %x) {
+; CHECK-LABEL: @shl_larger_bitwidth(
+; CHECK-NEXT:    [[ZEXT:%.*]] = zext i8 [[X:%.*]] to i16
+; CHECK-NEXT:    [[SHL:%.*]] = shl i16 [[ZEXT]], 1
+; CHECK-NEXT:    [[AND:%.*]] = and i16 [[SHL]], 42
+; CHECK-NEXT:    ret i16 [[AND]]
+;
+  %zext = zext i8 %x to i64
+  %shl = shl i64 %zext, 1
+  %zext2 = trunc i64 %shl to i32
+  %and = and i32 %zext2, 42
+  %trunc = trunc i32 %and to i16
+  ret i16 %trunc
+}
+
 define <2 x i16> @shl_vector(<2 x i8> %x) {
 ; CHECK-LABEL: @shl_vector(
 ; CHECK-NEXT:    [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
-- 
2.7.4