From 09606d6a635b15ae08d596bedaa5bd88d7f8ea1a Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 31 Jan 2022 09:08:05 -0800 Subject: [PATCH] [RISCV] Update the computeKnownBitsForTargetNode for RISCVISD::READ_VLENB to consider Zve/Zvl. We had previously hardcoded this to assume that vector registers are 128 bits. This was true when only V existed, but after Zve extensions were added this became incorrect. This patch adjusts it to support 128, 64, or 32 bit vectors depending on Zvl. The 128-bit limit is artificial, but we don't have any test coverage showing that we larger values so I was being conservative. None of our lit tests depend on this code today due to the custom lowering of ISD::VSCALE that inserts the appropriate left or right shift to convert from VLENB to VSCALE. That code was added after this code in computeKnownBitsForTargetNode. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D118582 --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 11 ++++++++--- llvm/lib/Target/RISCV/RISCVSubtarget.h | 1 + 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 4225ae4..de24058 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -8274,12 +8274,17 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, } break; } - case RISCVISD::READ_VLENB: - // We assume VLENB is at least 16 bytes. - Known.Zero.setLowBits(4); + case RISCVISD::READ_VLENB: { + // If we know the minimum VLen from Zvl extensions, we can use that to + // determine the trailing zeros of VLENB. + // FIXME: Limit to 128 bit vectors until we have more testing. + unsigned MinVLenB = std::min(128U, Subtarget.getMinVLen()) / 8; + if (MinVLenB > 0) + Known.Zero.setLowBits(Log2_32(MinVLenB)); // We assume VLENB is no more than 65536 / 8 bytes. Known.Zero.setBitsFrom(14); break; + } case ISD::INTRINSIC_W_CHAIN: case ISD::INTRINSIC_WO_CHAIN: { unsigned IntNo = diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index 044dda0..34c6e8e 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -195,6 +195,7 @@ public: return 0; } + unsigned getMinVLen() const { return ZvlLen; } RISCVABI::ABI getTargetABI() const { return TargetABI; } bool isRegisterReservedByUser(Register i) const { assert(i < RISCV::NUM_TARGET_REGS && "Register out of range"); -- 2.7.4