From 094e80882c898fbb95446c96a799abbe38f9baac Mon Sep 17 00:00:00 2001 From: "chenglin.bi" Date: Thu, 7 Apr 2022 19:08:59 +0800 Subject: [PATCH] [AMDGPU] Regenerate xor3-i1-const.ll test(NFC) --- llvm/test/CodeGen/AMDGPU/xor3-i1-const.ll | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/xor3-i1-const.ll b/llvm/test/CodeGen/AMDGPU/xor3-i1-const.ll index 5291cc7..73bde62 100644 --- a/llvm/test/CodeGen/AMDGPU/xor3-i1-const.ll +++ b/llvm/test/CodeGen/AMDGPU/xor3-i1-const.ll @@ -1,10 +1,24 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; This test used to crash -; GCN-LABEL: {{^}}xor3_i1_const: -; GCN: s_xor_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], -1 -; GCN: s_xor_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], -1 define amdgpu_ps float @xor3_i1_const(float inreg %arg1, i32 inreg %arg2) { +; GCN-LABEL: xor3_i1_const: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: v_mov_b32_e32 v1, 0x42640000 +; GCN-NEXT: s_mov_b32 m0, s1 +; GCN-NEXT: v_cmp_lt_f32_e64 s[2:3], s0, 0 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1 +; GCN-NEXT: v_interp_p2_f32 v0, v0, attr0.x +; GCN-NEXT: s_and_b64 s[2:3], s[2:3], vcc +; GCN-NEXT: v_cmp_gt_f32_e64 s[0:1], 0, v0 +; GCN-NEXT: s_xor_b64 s[4:5], s[2:3], -1 +; GCN-NEXT: s_and_b64 s[0:1], s[0:1], s[4:5] +; GCN-NEXT: s_xor_b64 s[2:3], s[0:1], s[2:3] +; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], -1 +; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s[0:1] +; GCN-NEXT: ; return to shader part epilog main_body: %tmp26 = fcmp nsz olt float %arg1, 0.000000e+00 %tmp28 = call nsz float @llvm.amdgcn.interp.p2(float undef, float undef, i32 0, i32 0, i32 %arg2) -- 2.7.4