From 087e98aab0ac9ceebe09449348f47c1fb3b18b6d Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 20 Apr 2021 17:27:24 +0100 Subject: [PATCH] [PhaseOrdering] Add second test case for PR36760 --- llvm/test/Transforms/PhaseOrdering/pr36760.ll | 33 +++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/llvm/test/Transforms/PhaseOrdering/pr36760.ll b/llvm/test/Transforms/PhaseOrdering/pr36760.ll index 5f8fb9f..80997dc 100644 --- a/llvm/test/Transforms/PhaseOrdering/pr36760.ll +++ b/llvm/test/Transforms/PhaseOrdering/pr36760.ll @@ -33,3 +33,36 @@ return: %3 = load i64, i64* %retval, align 8 ret i64 %3 } + +define i64 @PR36760_2(i64 %a) #0 { +; CHECK-LABEL: @PR36760_2( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = icmp slt i64 [[A:%.*]], -1 +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP0]], i64 [[A]], i64 -1 +; CHECK-NEXT: [[RETVAL_0:%.*]] = xor i64 [[TMP1]], -1 +; CHECK-NEXT: ret i64 [[RETVAL_0]] +; +entry: + %retval = alloca i64, align 8 + %a.addr = alloca i64, align 8 + store i64 %a, i64* %a.addr, align 8 + %0 = load i64, i64* %a.addr, align 8 + %cmp = icmp sge i64 %0, 0 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + store i64 0, i64* %retval, align 8 + br label %return + +if.end: ; preds = %entry + %1 = load i64, i64* %a.addr, align 8 + %shr = ashr i64 %1, 63 + %2 = load i64, i64* %a.addr, align 8 + %xor = xor i64 %shr, %2 + store i64 %xor, i64* %retval, align 8 + br label %return + +return: ; preds = %if.end, %if.then + %3 = load i64, i64* %retval, align 8 + ret i64 %3 +} -- 2.7.4