From 084aab04cc60e5eab32287d0483c33e12c92da87 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Jouni=20H=C3=B6gander?= Date: Thu, 1 Dec 2022 09:23:08 +0200 Subject: [PATCH] drm/i915/psr: Add continuous full frame bit together with single MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Currently we are observing occasionally display flickering or complete freeze. This is narrowed down to be caused by single full frame update (SFF). SFF bit after it's written gets cleared by HW in subsequent vblank i.e. when the update is sent to the panel. SFF bit is required to be written together with partial frame update (PFU) bit. After the SFF bit gets cleared by the HW psr2 man trk ctl register still contains PFU bit. If there is subsequent update for any reason we will end up having selective update/fetch configuration where start line is 0 and end line is 0. Also selective fetch configuration for the planes is not properly performed. This seems to be causing problems with some panels. Using CFF without SFF doesn't work either because it may happen that psr2 man track ctl register is overwritten by next update before vblank triggers sending the update. This is causing problems to psr_invalidate/flush. Using CFF and SFF together solves the problems as SFF is cleared only by HW in subsequent vblank and the update gets sent. Fix the flickering/freeze issue by keeping CFF bit as set when PSR2 is enabled unless there is a properly configured selective update via atomic commit. v2: - Improve commit message and comments - No functional changes This is also workaround for HSD 14014971508 Cc: Ville Syrjälä Cc: José Roberto de Souza Cc: Mika Kahola Reported-by: Lee Shawn C Signed-off-by: Jouni Högander Tested-by: Lee Shawn C Signed-off-by: Stanislav Lisovskiy Link: https://patchwork.freedesktop.org/patch/msgid/20221201072308.1905679-1-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 9820e5f..d0d7742 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1521,7 +1521,8 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), man_trk_ctl_enable_bit_get(dev_priv) | man_trk_ctl_partial_frame_bit_get(dev_priv) | - man_trk_ctl_single_full_frame_bit_get(dev_priv)); + man_trk_ctl_single_full_frame_bit_get(dev_priv) | + man_trk_ctl_continuos_full_frame(dev_priv)); /* * Display WA #0884: skl+ @@ -1635,11 +1636,8 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, val |= man_trk_ctl_partial_frame_bit_get(dev_priv); if (full_update) { - /* - * Not applying Wa_14014971508:adlp,mtl as we do not support the - * feature that requires this workaround. - */ val |= man_trk_ctl_single_full_frame_bit_get(dev_priv); + val |= man_trk_ctl_continuos_full_frame(dev_priv); goto exit; } @@ -2318,12 +2316,15 @@ static void _psr_flush_handle(struct intel_dp *intel_dp) /* can we turn CFF off? */ if (intel_dp->psr.busy_frontbuffer_bits == 0) { u32 val = man_trk_ctl_enable_bit_get(dev_priv) | - man_trk_ctl_partial_frame_bit_get(dev_priv) | - man_trk_ctl_single_full_frame_bit_get(dev_priv); + man_trk_ctl_partial_frame_bit_get(dev_priv) | + man_trk_ctl_single_full_frame_bit_get(dev_priv) | + man_trk_ctl_continuos_full_frame(dev_priv); /* - * turn continuous full frame off and do a single - * full frame + * Set psr2_sel_fetch_cff_enabled as false to allow selective + * updates. Still keep cff bit enabled as we don't have proper + * SU configuration in case update is sent for any reason after + * sff bit gets cleared by the HW on next vblank. */ intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), val); -- 2.7.4