From 0837f63fd2f00ab32b98ec18ba6adf6be7fa003e Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Mon, 17 Nov 2014 16:34:47 +0000 Subject: [PATCH] [Reassociate] Update test cases due to r222142. llvm-svn: 222144 --- clang/test/CodeGen/aarch64-neon-intrinsics.c | 4 ++-- clang/test/CodeGen/bmi-builtins.c | 8 ++++---- clang/test/CodeGen/builtins-arm-exclusive.c | 8 ++++---- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/clang/test/CodeGen/aarch64-neon-intrinsics.c b/clang/test/CodeGen/aarch64-neon-intrinsics.c index b120779..31ac847 100644 --- a/clang/test/CodeGen/aarch64-neon-intrinsics.c +++ b/clang/test/CodeGen/aarch64-neon-intrinsics.c @@ -8172,13 +8172,13 @@ int64_t test_vcltzd_s64(int64_t a) { int64_t test_vtstd_s64(int64_t a, int64_t b) { // CHECK-LABEL: test_vtstd_s64 -// CHECK: {{cmtst d[0-9]+, d[0-9]+, d[0-9]+|tst x1, x0}} +// CHECK: {{cmtst d[0-9]+, d[0-9]+, d[0-9]+|tst x0, x1}} return (int64_t)vtstd_s64(a, b); } uint64_t test_vtstd_u64(uint64_t a, uint64_t b) { // CHECK-LABEL: test_vtstd_u64 -// CHECK: {{cmtst d[0-9]+, d[0-9]+, d[0-9]+|tst x1, x0}} +// CHECK: {{cmtst d[0-9]+, d[0-9]+, d[0-9]+|tst x0, x1}} return (uint64_t)vtstd_u64(a, b); } diff --git a/clang/test/CodeGen/bmi-builtins.c b/clang/test/CodeGen/bmi-builtins.c index 92332e3..6a59239 100644 --- a/clang/test/CodeGen/bmi-builtins.c +++ b/clang/test/CodeGen/bmi-builtins.c @@ -20,7 +20,7 @@ unsigned short test__tzcnt_u16(unsigned short __X) { unsigned int test__andn_u32(unsigned int __X, unsigned int __Y) { // CHECK: [[DEST:%.*]] = xor i32 %{{.*}}, -1 - // CHECK-NEXT: %{{.*}} = and i32 %{{.*}}, [[DEST]] + // CHECK-NEXT: %{{.*}} = and i32 [[DEST]], %{{.*}} return __andn_u32(__X, __Y); } @@ -54,7 +54,7 @@ unsigned int test__tzcnt_u32(unsigned int __X) { unsigned long long test__andn_u64(unsigned long __X, unsigned long __Y) { // CHECK: [[DEST:%.*]] = xor i64 %{{.*}}, -1 - // CHECK-NEXT: %{{.*}} = and i64 %{{.*}}, [[DEST]] + // CHECK-NEXT: %{{.*}} = and i64 [[DEST]], %{{.*}} return __andn_u64(__X, __Y); } @@ -95,7 +95,7 @@ unsigned short test_tzcnt_u16(unsigned short __X) { unsigned int test_andn_u32(unsigned int __X, unsigned int __Y) { // CHECK: [[DEST:%.*]] = xor i32 %{{.*}}, -1 - // CHECK-NEXT: %{{.*}} = and i32 %{{.*}}, [[DEST]] + // CHECK-NEXT: %{{.*}} = and i32 [[DEST]], %{{.*}} return _andn_u32(__X, __Y); } @@ -130,7 +130,7 @@ unsigned int test_tzcnt_u32(unsigned int __X) { unsigned long long test_andn_u64(unsigned long __X, unsigned long __Y) { // CHECK: [[DEST:%.*]] = xor i64 %{{.*}}, -1 - // CHECK-NEXT: %{{.*}} = and i64 %{{.*}}, [[DEST]] + // CHECK-NEXT: %{{.*}} = and i64 [[DEST]], %{{.*}} return _andn_u64(__X, __Y); } diff --git a/clang/test/CodeGen/builtins-arm-exclusive.c b/clang/test/CodeGen/builtins-arm-exclusive.c index 2b10238..e2df429 100644 --- a/clang/test/CodeGen/builtins-arm-exclusive.c +++ b/clang/test/CodeGen/builtins-arm-exclusive.c @@ -94,7 +94,7 @@ int test_ldrex(char *addr, long long *addr64, float *addrfloat) { // CHECK: [[RESHI64:%.*]] = zext i32 [[RESHI]] to i64 // CHECK: [[RESLO64:%.*]] = zext i32 [[RESLO]] to i64 // CHECK: [[RESHIHI:%.*]] = shl nuw i64 [[RESHI64]], 32 -// CHECK: [[INTRES:%.*]] = or i64 [[RESHIHI]], [[RESLO64]] +// CHECK: [[INTRES:%.*]] = or i64 [[RESLO64]], [[RESHIHI]] // CHECK: bitcast i64 [[INTRES]] to double // CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.aarch64.ldxr.p0i64(i64* [[ADDR64]]) @@ -178,7 +178,7 @@ int test_ldaex(char *addr, long long *addr64, float *addrfloat) { // CHECK: [[RESHI64:%.*]] = zext i32 [[RESHI]] to i64 // CHECK: [[RESLO64:%.*]] = zext i32 [[RESLO]] to i64 // CHECK: [[RESHIHI:%.*]] = shl nuw i64 [[RESHI64]], 32 -// CHECK: [[INTRES:%.*]] = or i64 [[RESHIHI]], [[RESLO64]] +// CHECK: [[INTRES:%.*]] = or i64 [[RESLO64]], [[RESHIHI]] // CHECK: bitcast i64 [[INTRES]] to double // CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.aarch64.ldaxr.p0i64(i64* [[ADDR64]]) @@ -323,7 +323,7 @@ __int128 test_ldrex_128(__int128 *addr) { // CHECK-ARM64: [[RESHI64:%.*]] = zext i64 [[RESHI]] to i128 // CHECK-ARM64: [[RESLO64:%.*]] = zext i64 [[RESLO]] to i128 // CHECK-ARM64: [[RESHIHI:%.*]] = shl nuw i128 [[RESHI64]], 64 -// CHECK-ARM64: [[INTRES:%.*]] = or i128 [[RESHIHI]], [[RESLO64]] +// CHECK-ARM64: [[INTRES:%.*]] = or i128 [[RESLO64]], [[RESHIHI]] // CHECK-ARM64: ret i128 [[INTRES]] } @@ -349,7 +349,7 @@ __int128 test_ldaex_128(__int128 *addr) { // CHECK-ARM64: [[RESHI64:%.*]] = zext i64 [[RESHI]] to i128 // CHECK-ARM64: [[RESLO64:%.*]] = zext i64 [[RESLO]] to i128 // CHECK-ARM64: [[RESHIHI:%.*]] = shl nuw i128 [[RESHI64]], 64 -// CHECK-ARM64: [[INTRES:%.*]] = or i128 [[RESHIHI]], [[RESLO64]] +// CHECK-ARM64: [[INTRES:%.*]] = or i128 [[RESLO64]], [[RESHIHI]] // CHECK-ARM64: ret i128 [[INTRES]] } -- 2.7.4