From 083798e2702f9b12828ba9d3ee4d1486340a2cb5 Mon Sep 17 00:00:00 2001 From: Ping Deng Date: Mon, 30 May 2022 02:52:40 +0000 Subject: [PATCH] [LegalizeTypes][VP] Add integer promotion support for vp.fptosi/vp.fptoui Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D125760 --- .../CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 20 +++++++++++++++++--- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll | 22 ++++++++++++++++++++++ .../CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll | 13 +++++++++++++ .../CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll | 13 +++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll | 22 ++++++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll | 13 +++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll | 13 +++++++++++++ 7 files changed, 113 insertions(+), 3 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 686de39..123ccfd 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -135,6 +135,8 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { case ISD::ZERO_EXTEND: case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; + case ISD::VP_FPTOSI: + case ISD::VP_FPTOUI: case ISD::STRICT_FP_TO_SINT: case ISD::STRICT_FP_TO_UINT: case ISD::FP_TO_SINT: @@ -669,6 +671,11 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { TLI.isOperationLegalOrCustom(ISD::STRICT_FP_TO_SINT, NVT)) NewOpc = ISD::STRICT_FP_TO_SINT; + if (N->getOpcode() == ISD::VP_FPTOUI && + !TLI.isOperationLegal(ISD::VP_FPTOUI, NVT) && + TLI.isOperationLegalOrCustom(ISD::VP_FPTOSI, NVT)) + NewOpc = ISD::VP_FPTOSI; + SDValue Res; if (N->isStrictFPOpcode()) { Res = DAG.getNode(NewOpc, dl, {NVT, MVT::Other}, @@ -676,8 +683,12 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { // Legalize the chain result - switch anything that used the old chain to // use the new one. ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); - } else + } else if (NewOpc == ISD::VP_FPTOSI || NewOpc == ISD::VP_FPTOUI) { + Res = DAG.getNode(NewOpc, dl, NVT, {N->getOperand(0), N->getOperand(1), + N->getOperand(2)}); + } else { Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0)); + } // Assert that the converted value fits in the original type. If it doesn't // (eg: because the value being converted is too big), then the result of the @@ -687,8 +698,11 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { // before legalization: fp-to-uint16, 65534. -> 0xfffe // after legalization: fp-to-sint32, 65534. -> 0x0000fffe return DAG.getNode((N->getOpcode() == ISD::FP_TO_UINT || - N->getOpcode() == ISD::STRICT_FP_TO_UINT) ? - ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, + N->getOpcode() == ISD::STRICT_FP_TO_UINT || + N->getOpcode() == ISD::VP_FPTOUI) + ? ISD::AssertZext + : ISD::AssertSext, + dl, NVT, Res, DAG.getValueType(N->getValueType(0).getScalarType())); } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll index 566fcdb..5a7edd2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll @@ -44,6 +44,28 @@ define <2 x i1> @fp2si_v2f32_v2i1(<2 x float> %x) { ret <2 x i1> %z } +define <2 x i15> @fp2si_v2f32_v2i15(<2 x float> %x) { +; CHECK-LABEL: fp2si_v2f32_v2i15: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 +; CHECK-NEXT: ret + %z = fptosi <2 x float> %x to <2 x i15> + ret <2 x i15> %z +} + +define <2 x i15> @fp2ui_v2f32_v2i15(<2 x float> %x) { +; CHECK-LABEL: fp2ui_v2f32_v2i15: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 +; CHECK-NEXT: ret + %z = fptoui <2 x float> %x to <2 x i15> + ret <2 x i15> %z +} + define <2 x i1> @fp2ui_v2f32_v2i1(<2 x float> %x) { ; CHECK-LABEL: fp2ui_v2f32_v2i1: ; CHECK: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll index d833523..423e123 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll @@ -4,6 +4,19 @@ ; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+experimental-zvfh \ ; RUN: -riscv-v-vector-bits-min=128 < %s | FileCheck %s +declare <4 x i7> @llvm.vp.fptosi.v4i7.v4f16(<4 x half>, <4 x i1>, i32) + +define <4 x i7> @vfptosi_v4i7_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vfptosi_v4i7_v4f16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 +; CHECK-NEXT: ret + %v = call <4 x i7> @llvm.vp.fptosi.v4i7.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl) + ret <4 x i7> %v +} + declare <4 x i8> @llvm.vp.fptosi.v4i8.v4f16(<4 x half>, <4 x i1>, i32) define <4 x i8> @vfptosi_v4i8_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) { diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll index 0f96789..2f97d38 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll @@ -4,6 +4,19 @@ ; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+experimental-zvfh \ ; RUN: -riscv-v-vector-bits-min=128 < %s | FileCheck %s +declare <4 x i7> @llvm.vp.fptoui.v4i7.v4f16(<4 x half>, <4 x i1>, i32) + +define <4 x i7> @vfptoui_v4i7_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vfptoui_v4i7_v4f16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 +; CHECK-NEXT: ret + %v = call <4 x i7> @llvm.vp.fptoui.v4i7.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl) + ret <4 x i7> %v +} + declare <4 x i8> @llvm.vp.fptoui.v4i8.v4f16(<4 x half>, <4 x i1>, i32) define <4 x i8> @vfptoui_v4i8_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) { diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll index 6808110..d73b6f6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll @@ -16,6 +16,28 @@ define @vfptosi_nxv1f16_nxv1i1( %va) { ret %evec } +define @vfptosi_nxv1f16_nxv1i7( %va) { +; CHECK-LABEL: vfptosi_nxv1f16_nxv1i7: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 +; CHECK-NEXT: ret + %evec = fptosi %va to + ret %evec +} + +define @vfptoui_nxv1f16_nxv1i7( %va) { +; CHECK-LABEL: vfptoui_nxv1f16_nxv1i7: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 +; CHECK-NEXT: ret + %evec = fptoui %va to + ret %evec +} + define @vfptoui_nxv1f16_nxv1i1( %va) { ; CHECK-LABEL: vfptoui_nxv1f16_nxv1i1: ; CHECK: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll index 9686bc1..72d0d40 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll @@ -2,6 +2,19 @@ ; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+experimental-zvfh < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+experimental-zvfh < %s | FileCheck %s +declare @llvm.vp.fptosi.v4i7.v4f16(, , i32) + +define @vfptosi_v4i7_v4f16( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vfptosi_v4i7_v4f16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 +; CHECK-NEXT: ret + %v = call @llvm.vp.fptosi.v4i7.v4f16( %va, %m, i32 %evl) + ret %v +} + declare @llvm.vp.fptosi.nxv2i8.nxv2f16(, , i32) define @vfptosi_nxv2i8_nxv2f16( %va, %m, i32 zeroext %evl) { diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll index 9a64cd8..1d1995a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll @@ -2,6 +2,19 @@ ; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+experimental-zvfh < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+experimental-zvfh < %s | FileCheck %s +declare @llvm.vp.fptoui.v4i7.v4f16(, , i32) + +define @vfptoui_v4i7_v4f16( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vfptoui_v4i7_v4f16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 +; CHECK-NEXT: ret + %v = call @llvm.vp.fptoui.v4i7.v4f16( %va, %m, i32 %evl) + ret %v +} + declare @llvm.vp.fptoui.nxv2i8.nxv2f16(, , i32) define @vfptoui_nxv2i8_nxv2f16( %va, %m, i32 zeroext %evl) { -- 2.7.4