From 0831f57afe27021ff08dd24b8e77f2f1d4597c08 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Mon, 2 Apr 2018 15:06:55 +0000 Subject: [PATCH] [Hexagon] Clean up some code in HexagonAsmPrinter, NFC llvm-svn: 328981 --- llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp | 85 +++++++++++++++------------ llvm/lib/Target/Hexagon/HexagonAsmPrinter.h | 16 +++-- 2 files changed, 53 insertions(+), 48 deletions(-) diff --git a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp index 5be2cc9..6b836e2 100644 --- a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -62,10 +62,6 @@ void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI, #define DEBUG_TYPE "asm-printer" -static cl::opt AlignCalls( - "hexagon-align-calls", cl::Hidden, cl::init(true), - cl::desc("Insert falign after call instruction for Hexagon target")); - // Given a scalar register return its pair. inline static unsigned getHexagonRegisterPair(unsigned Reg, const MCRegisterInfo *RI) { @@ -76,16 +72,13 @@ inline static unsigned getHexagonRegisterPair(unsigned Reg, return Pair; } -HexagonAsmPrinter::HexagonAsmPrinter(TargetMachine &TM, - std::unique_ptr Streamer) - : AsmPrinter(TM, std::move(Streamer)) {} - void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNo); switch (MO.getType()) { - default: llvm_unreachable (""); + default: + llvm_unreachable (""); case MachineOperand::MO_Register: O << HexagonInstPrinter::getRegisterName(MO.getReg()); return; @@ -112,8 +105,8 @@ void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, // for the case in which the basic block is reachable by a fall through but // through an indirect from a jump table. In this case, the jump table // will contain a label not defined by AsmPrinter. -bool HexagonAsmPrinter:: -isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const { +bool HexagonAsmPrinter::isBlockOnlyReachableByFallthrough( + const MachineBasicBlock *MBB) const { if (MBB->hasAddressTaken()) return false; return AsmPrinter::isBlockOnlyReachableByFallthrough(MBB); @@ -167,7 +160,8 @@ bool HexagonAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, } bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, - unsigned OpNo, unsigned AsmVariant, + unsigned OpNo, + unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) { if (ExtraCode && ExtraCode[0]) @@ -183,10 +177,10 @@ bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, if (Offset.isImm()) { if (Offset.getImm()) - O << " + #" << Offset.getImm(); - } - else + O << "+#" << Offset.getImm(); + } else { llvm_unreachable("Unimplemented"); + } return false; } @@ -285,7 +279,8 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8; switch (Inst.getOpcode()) { - default: return; + default: + return; case Hexagon::A2_iconst: { Inst.setOpcode(Hexagon::A2_addi); @@ -300,30 +295,40 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, break; } - case Hexagon::A2_tfrf: + case Hexagon::A2_tfrf: { + const MCConstantExpr *Zero = MCConstantExpr::create(0, OutContext); Inst.setOpcode(Hexagon::A2_paddif); - Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext))); + Inst.addOperand(MCOperand::createExpr(Zero)); break; + } - case Hexagon::A2_tfrt: + case Hexagon::A2_tfrt: { + const MCConstantExpr *Zero = MCConstantExpr::create(0, OutContext); Inst.setOpcode(Hexagon::A2_paddit); - Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext))); + Inst.addOperand(MCOperand::createExpr(Zero)); break; + } - case Hexagon::A2_tfrfnew: + case Hexagon::A2_tfrfnew: { + const MCConstantExpr *Zero = MCConstantExpr::create(0, OutContext); Inst.setOpcode(Hexagon::A2_paddifnew); - Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext))); + Inst.addOperand(MCOperand::createExpr(Zero)); break; + } - case Hexagon::A2_tfrtnew: + case Hexagon::A2_tfrtnew: { + const MCConstantExpr *Zero = MCConstantExpr::create(0, OutContext); Inst.setOpcode(Hexagon::A2_padditnew); - Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext))); + Inst.addOperand(MCOperand::createExpr(Zero)); break; + } - case Hexagon::A2_zxtb: + case Hexagon::A2_zxtb: { + const MCConstantExpr *C255 = MCConstantExpr::create(255, OutContext); Inst.setOpcode(Hexagon::A2_andir); - Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(255, OutContext))); + Inst.addOperand(MCOperand::createExpr(C255)); break; + } // "$dst = CONST64(#$src1)", case Hexagon::CONST64: @@ -525,10 +530,12 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, bool Success = MO.getExpr()->evaluateAsAbsolute(Imm); if (Success && Imm < 0) { const MCExpr *MOne = MCConstantExpr::create(-1, OutContext); - TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(MOne, OutContext))); + const HexagonMCExpr *E = HexagonMCExpr::create(MOne, OutContext); + TmpInst.addOperand(MCOperand::createExpr(E)); } else { const MCExpr *Zero = MCConstantExpr::create(0, OutContext); - TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(Zero, OutContext))); + const HexagonMCExpr *E = HexagonMCExpr::create(Zero, OutContext); + TmpInst.addOperand(MCOperand::createExpr(E)); } TmpInst.addOperand(MO); MappedInst = TmpInst; @@ -569,9 +576,9 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, MO.setReg(High); // Add a new operand for the second register in the pair. MappedInst.addOperand(MCOperand::createReg(Low)); - MappedInst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew) - ? Hexagon::C2_ccombinewnewt - : Hexagon::C2_ccombinewnewf); + MappedInst.setOpcode(Inst.getOpcode() == Hexagon::A2_tfrptnew + ? Hexagon::C2_ccombinewnewt + : Hexagon::C2_ccombinewnewf); return; } @@ -615,6 +622,7 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, MappedInst = TmpInst; return; } + case Hexagon::V6_vdd0: { MCInst TmpInst; assert (Inst.getOperand(0).isReg() && @@ -627,6 +635,7 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, MappedInst = TmpInst; return; } + case Hexagon::V6_vL32Ub_pi: case Hexagon::V6_vL32b_cur_pi: case Hexagon::V6_vL32b_nt_cur_pi: @@ -735,12 +744,10 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, case Hexagon::V6_vS32b_srls_pi: MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext); return; - } } -/// printMachineInstruction -- Print out a single Hexagon MI in Darwin syntax to -/// the current output stream. +/// Print out a single Hexagon MI to the current output stream. void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) { MCInst MCB; MCB.setOpcode(Hexagon::BUNDLE); @@ -764,11 +771,11 @@ void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) { if (MI->isBundle() && HII.getBundleNoShuf(*MI)) HexagonMCInstrInfo::setMemReorderDisabled(MCB); - bool Ok = HexagonMCInstrInfo::canonicalizePacket( - MCII, *Subtarget, OutStreamer->getContext(), MCB, nullptr); - assert(Ok); - (void)Ok; - if(HexagonMCInstrInfo::bundleSize(MCB) == 0) + MCContext &Ctx = OutStreamer->getContext(); + bool Ok = HexagonMCInstrInfo::canonicalizePacket(MCII, *Subtarget, Ctx, + MCB, nullptr); + assert(Ok); (void)Ok; + if (HexagonMCInstrInfo::bundleSize(MCB) == 0) return; OutStreamer->EmitInstruction(MCB, getSubtargetInfo()); } diff --git a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.h b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.h index 4b88656..d0629d1 100644 --- a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.h +++ b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.h @@ -18,7 +18,8 @@ #include "HexagonSubtarget.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/MachineFunction.h" -#include +#include "llvm/MC/MCStreamer.h" +#include namespace llvm { @@ -32,7 +33,8 @@ class TargetMachine; public: explicit HexagonAsmPrinter(TargetMachine &TM, - std::unique_ptr Streamer); + std::unique_ptr Streamer) + : AsmPrinter(TM, std::move(Streamer)) {} bool runOnMachineFunction(MachineFunction &Fn) override { Subtarget = &Fn.getSubtarget(); @@ -43,13 +45,11 @@ class TargetMachine; return "Hexagon Assembly Printer"; } - bool isBlockOnlyReachableByFallthrough( - const MachineBasicBlock *MBB) const override; + bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) + const override; void EmitInstruction(const MachineInstr *MI) override; - - void HexagonProcessInstruction(MCInst &Inst, - const MachineInstr &MBB); + void HexagonProcessInstruction(MCInst &Inst, const MachineInstr &MBB); void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O); bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, @@ -58,8 +58,6 @@ class TargetMachine; bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS) override; - - static const char *getRegisterName(unsigned RegNo); }; } // end namespace llvm -- 2.7.4