From 0821c8824bc11162b0f62c6cf5b48ae972803ab4 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Mon, 19 Jul 2021 16:20:44 +0100 Subject: [PATCH] [AMDGPU] Pre-commit test case for D106284 This test case shows the scheduler wrongly reordering two buffer accesses that might alias. --- llvm/test/CodeGen/AMDGPU/buffer-schedule.ll | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/llvm/test/CodeGen/AMDGPU/buffer-schedule.ll b/llvm/test/CodeGen/AMDGPU/buffer-schedule.ll index 65328e9f642f..b77e5c739d32 100644 --- a/llvm/test/CodeGen/AMDGPU/buffer-schedule.ll +++ b/llvm/test/CodeGen/AMDGPU/buffer-schedule.ll @@ -44,10 +44,27 @@ define amdgpu_cs void @_amdgpu_cs_main(<3 x i32> inreg %arg3, <3 x i32> %arg5) { ret void } +; FIXME: the first load and store should not be reordered because they might +; alias depending on the value of %off +; GCN-LABEL: {{^}}test1: +; GCN: buffer_load_dword +; GCN: buffer_store_dword +; GCN: buffer_store_dword +define amdgpu_cs void @test1(<4 x i32> inreg %buf, i32 %off) { +.entry: + call void @llvm.amdgcn.raw.buffer.store.i32(i32 0, <4 x i32> %buf, i32 8, i32 0, i32 0) + %val = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> %buf, i32 %off, i32 0, i32 0) + call void @llvm.amdgcn.raw.buffer.store.i32(i32 %val, <4 x i32> %buf, i32 0, i32 0, i32 0) + ret void +} + declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #2 declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #3 +declare i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32>, i32, i32, i32) #2 + +declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32) #3 + attributes #2 = { nounwind readonly } attributes #3 = { nounwind writeonly } - -- 2.34.1