From 0800e23ecf42b8323c226041f3982cd7856061c9 Mon Sep 17 00:00:00 2001 From: Wilco Dijkstra Date: Wed, 18 Sep 2019 18:22:55 +0000 Subject: [PATCH] [ARM] Cleanup highpart multiply patterns Cleanup the various highpart multiply patterns using iterators. As a result the signed and unsigned variants and the pre-Armv6 multiply operand constraints are all handled in a single pattern and simple expander. gcc/ * config/arm/arm.md (smulsi3_highpart): Use and iterators. (smulsi3_highpart_nov6): Remove pattern. (smulsi3_highpart_v6): Likewise. (umulsi3_highpart): Likewise. (umulsi3_highpart_nov6): Likewise. (umulsi3_highpart_v6): Likewise. (mull_high): Add new combined multiply pattern. From-SVN: r275899 --- gcc/ChangeLog | 10 +++++++ gcc/config/arm/arm.md | 80 +++++++-------------------------------------------- 2 files changed, 21 insertions(+), 69 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 13d5cb9..8b76a62 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -8,6 +8,16 @@ 2019-09-18 Wilco Dijkstra + * config/arm/arm.md (smulsi3_highpart): Use and iterators. + (smulsi3_highpart_nov6): Remove pattern. + (smulsi3_highpart_v6): Likewise. + (umulsi3_highpart): Likewise. + (umulsi3_highpart_nov6): Likewise. + (umulsi3_highpart_v6): Likewise. + (mull_high): Add new combined multiply pattern. + +2019-09-18 Wilco Dijkstra + * config/arm/arm.md (arm_mulsi3): Remove pattern. (arm_mulsi3_v6): Likewise. (mulsi3addsi_v6): Likewise. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 4ffc771..b47e196 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1895,92 +1895,34 @@ (set_attr "predicable" "yes")] ) -(define_expand "smulsi3_highpart" +(define_expand "mulsi3_highpart" [(parallel [(set (match_operand:SI 0 "s_register_operand") (truncate:SI (lshiftrt:DI (mult:DI - (sign_extend:DI (match_operand:SI 1 "s_register_operand")) - (sign_extend:DI (match_operand:SI 2 "s_register_operand"))) + (SE:DI (match_operand:SI 1 "s_register_operand")) + (SE:DI (match_operand:SI 2 "s_register_operand"))) (const_int 32)))) (clobber (match_scratch:SI 3 ""))])] "TARGET_32BIT" "" ) -(define_insn "*smulsi3_highpart_nov6" - [(set (match_operand:SI 0 "s_register_operand" "=&r,&r") +(define_insn "*mull_high" + [(set (match_operand:SI 0 "s_register_operand" "=r,&r,&r") (truncate:SI (lshiftrt:DI (mult:DI - (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r")) - (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r"))) + (SE:DI (match_operand:SI 1 "s_register_operand" "%r,0,r")) + (SE:DI (match_operand:SI 2 "s_register_operand" "r,r,r"))) (const_int 32)))) - (clobber (match_scratch:SI 3 "=&r,&r"))] - "TARGET_32BIT && !arm_arch6" - "smull%?\\t%3, %0, %2, %1" - [(set_attr "type" "smull") - (set_attr "predicable" "yes")] -) - -(define_insn "*smulsi3_highpart_v6" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (truncate:SI - (lshiftrt:DI - (mult:DI - (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")) - (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))) - (const_int 32)))) - (clobber (match_scratch:SI 3 "=r"))] - "TARGET_32BIT && arm_arch6" - "smull%?\\t%3, %0, %2, %1" - [(set_attr "type" "smull") - (set_attr "predicable" "yes")] -) - -(define_expand "umulsi3_highpart" - [(parallel - [(set (match_operand:SI 0 "s_register_operand") - (truncate:SI - (lshiftrt:DI - (mult:DI - (zero_extend:DI (match_operand:SI 1 "s_register_operand")) - (zero_extend:DI (match_operand:SI 2 "s_register_operand"))) - (const_int 32)))) - (clobber (match_scratch:SI 3 ""))])] + (clobber (match_scratch:SI 3 "=r,&r,&r"))] "TARGET_32BIT" - "" -) - -(define_insn "*umulsi3_highpart_nov6" - [(set (match_operand:SI 0 "s_register_operand" "=&r,&r") - (truncate:SI - (lshiftrt:DI - (mult:DI - (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r")) - (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r"))) - (const_int 32)))) - (clobber (match_scratch:SI 3 "=&r,&r"))] - "TARGET_32BIT && !arm_arch6" - "umull%?\\t%3, %0, %2, %1" + "mull%?\\t%3, %0, %2, %1" [(set_attr "type" "umull") - (set_attr "predicable" "yes")] -) - -(define_insn "*umulsi3_highpart_v6" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (truncate:SI - (lshiftrt:DI - (mult:DI - (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")) - (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))) - (const_int 32)))) - (clobber (match_scratch:SI 3 "=r"))] - "TARGET_32BIT && arm_arch6" - "umull%?\\t%3, %0, %2, %1" - [(set_attr "type" "umull") - (set_attr "predicable" "yes")] + (set_attr "predicable" "yes") + (set_attr "arch" "v6,nov6,nov6")] ) (define_insn "mulhisi3" -- 2.7.4