From 076a9dc99a2c694260b66fe02e832d7a161a95ee Mon Sep 17 00:00:00 2001 From: Shengchen Kan Date: Sun, 20 Mar 2022 12:00:25 +0800 Subject: [PATCH] [X86][NFC] Rename hasCMOV() to canUseCMOV(), hasLAHFSAHF() to canUseLAHFSAHF() To make them less like other feature functions. This is a follow-up patch for D121978. --- llvm/lib/Target/X86/X86FastISel.cpp | 2 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 4 ++-- llvm/lib/Target/X86/X86ISelLowering.cpp | 14 +++++++------- llvm/lib/Target/X86/X86InstrInfo.cpp | 2 +- llvm/lib/Target/X86/X86InstrInfo.td | 4 ++-- llvm/lib/Target/X86/X86Subtarget.cpp | 2 +- llvm/lib/Target/X86/X86Subtarget.h | 6 ++++-- 7 files changed, 18 insertions(+), 16 deletions(-) diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index cbdb732..2e40ad1 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -2036,7 +2036,7 @@ bool X86FastISel::X86SelectDivRem(const Instruction *I) { /// the select. bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) { // Check if the subtarget supports these instructions. - if (!Subtarget->hasCMOV()) + if (!Subtarget->canUseCMOV()) return false; // FIXME: Add support for i8. diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index ea421b7..e9a1c30 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -5514,7 +5514,7 @@ void X86DAGToDAGISel::Select(SDNode *Node) { MVT CmpVT = N0.getSimpleValueType(); // Floating point needs special handling if we don't have FCOMI. - if (Subtarget->hasCMOV()) + if (Subtarget->canUseCMOV()) break; bool IsSignaling = Node->getOpcode() == X86ISD::STRICT_FCMPS; @@ -5554,7 +5554,7 @@ void X86DAGToDAGISel::Select(SDNode *Node) { // Move AH into flags. // Some 64-bit targets lack SAHF support, but they do support FCOMI. - assert(Subtarget->hasLAHFSAHF() && + assert(Subtarget->canUseLAHFSAHF() && "Target doesn't support SAHF or FCOMI?"); SDValue AH = CurDAG->getCopyToReg(Chain, dl, X86::AH, Extract, SDValue()); Chain = AH; diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 212cb98..5e6ffbe 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -200,7 +200,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, } // Integer absolute. - if (Subtarget.hasCMOV()) { + if (Subtarget.canUseCMOV()) { setOperationAction(ISD::ABS , MVT::i16 , Custom); setOperationAction(ISD::ABS , MVT::i32 , Custom); if (Subtarget.is64Bit()) @@ -23466,7 +23466,7 @@ X86TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor, // Only perform this transform if CMOV is supported otherwise the select // below will become a branch. - if (!Subtarget.hasCMOV()) + if (!Subtarget.canUseCMOV()) return SDValue(); // fold (sdiv X, pow2) @@ -24662,7 +24662,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { return (Op1.getOpcode() == ISD::CTTZ_ZERO_UNDEF && Op1.hasOneUse() && Op1.getOperand(0) == CmpOp0 && isAllOnesConstant(Op2)); }; - if (Subtarget.hasCMOV() && (VT == MVT::i32 || VT == MVT::i64) && + if (Subtarget.canUseCMOV() && (VT == MVT::i32 || VT == MVT::i64) && ((CondCode == X86::COND_NE && MatchFFSMinus1(Op1, Op2)) || (CondCode == X86::COND_E && MatchFFSMinus1(Op2, Op1)))) { // Keep Cmp. @@ -24690,7 +24690,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { DAG.getTargetConstant(X86::COND_B, DL, MVT::i8), Sub.getValue(1)); return DAG.getNode(ISD::OR, DL, VT, SBB, Y); - } else if (!Subtarget.hasCMOV() && CondCode == X86::COND_E && + } else if (!Subtarget.canUseCMOV() && CondCode == X86::COND_E && Cmp.getOperand(0).getOpcode() == ISD::AND && isOneConstant(Cmp.getOperand(0).getOperand(1))) { SDValue Src1, Src2; @@ -24745,7 +24745,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { SDValue Cmp = Cond.getOperand(1); bool IllegalFPCMov = false; if (VT.isFloatingPoint() && !VT.isVector() && - !isScalarFPTypeInSSEReg(VT) && Subtarget.hasCMOV()) // FPStack? + !isScalarFPTypeInSSEReg(VT) && Subtarget.canUseCMOV()) // FPStack? IllegalFPCMov = !hasFPCMov(cast(CC)->getSExtValue()); if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || @@ -24826,7 +24826,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { // legal, but EmitLoweredSelect() can not deal with these extensions // being inserted between two CMOV's. (in i16 case too TBN) // https://bugs.llvm.org/show_bug.cgi?id=40974 - if ((Op.getValueType() == MVT::i8 && Subtarget.hasCMOV()) || + if ((Op.getValueType() == MVT::i8 && Subtarget.canUseCMOV()) || (Op.getValueType() == MVT::i16 && !X86::mayFoldLoad(Op1, Subtarget) && !X86::mayFoldLoad(Op2, Subtarget))) { Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1); @@ -45111,7 +45111,7 @@ static SDValue combineCMov(SDNode *N, SelectionDAG &DAG, if (!(FalseOp.getValueType() == MVT::f80 || (FalseOp.getValueType() == MVT::f64 && !Subtarget.hasSSE2()) || (FalseOp.getValueType() == MVT::f32 && !Subtarget.hasSSE1())) || - !Subtarget.hasCMOV() || hasFPCMov(CC)) { + !Subtarget.canUseCMOV() || hasFPCMov(CC)) { SDValue Ops[] = {FalseOp, TrueOp, DAG.getTargetConstant(CC, DL, MVT::i8), Flags}; return DAG.getNode(X86ISD::CMOV, DL, N->getValueType(0), Ops); diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 50b26a0..095c5e7 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -3463,7 +3463,7 @@ bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const { // Not all subtargets have cmov instructions. - if (!Subtarget.hasCMOV()) + if (!Subtarget.canUseCMOV()) return false; if (Cond.size() != 1) return false; diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 87ebdb3..f464b72 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -875,8 +875,8 @@ def relocImm : ComplexPattern; -def HasCMOV : Predicate<"Subtarget->hasCMOV()">; -def NoCMOV : Predicate<"!Subtarget->hasCMOV()">; +def HasCMOV : Predicate<"Subtarget->canUseCMOV()">; +def NoCMOV : Predicate<"!Subtarget->canUseCMOV()">; def HasMMX : Predicate<"Subtarget->hasMMX()">; def Has3DNow : Predicate<"Subtarget->hasThreeDNow()">; diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp index 3105a5b..0d091ad 100644 --- a/llvm/lib/Target/X86/X86Subtarget.cpp +++ b/llvm/lib/Target/X86/X86Subtarget.cpp @@ -359,7 +359,7 @@ const RegisterBankInfo *X86Subtarget::getRegBankInfo() const { } bool X86Subtarget::enableEarlyIfConversion() const { - return hasCMOV() && X86EarlyIfConv; + return canUseCMOV() && X86EarlyIfConv; } void X86Subtarget::getPostRAMutations( diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h index 8b2ac68..80c2d0d 100644 --- a/llvm/lib/Target/X86/X86Subtarget.h +++ b/llvm/lib/Target/X86/X86Subtarget.h @@ -640,9 +640,10 @@ public: return hasCX16() && is64Bit(); } bool hasNOPL() const { return HasNOPL; } + bool hasCMOV() const { return HasCMOV; } // SSE codegen depends on cmovs, and all SSE1+ processors support them. // All 64-bit processors support cmov. - bool hasCMOV() const { return HasCMOV || X86SSELevel >= SSE1 || is64Bit(); } + bool canUseCMOV() const { return hasCMOV() || hasSSE1() || is64Bit(); } bool hasSSE1() const { return X86SSELevel >= SSE1; } bool hasSSE2() const { return X86SSELevel >= SSE2; } bool hasSSE3() const { return X86SSELevel >= SSE3; } @@ -705,7 +706,8 @@ public: return hasSSE1() || (hasPRFCHW() && !hasThreeDNow()) || hasPREFETCHWT1(); } bool hasRDSEED() const { return HasRDSEED; } - bool hasLAHFSAHF() const { return HasLAHFSAHF64 || !is64Bit(); } + bool hasLAHFSAHF() const { return HasLAHFSAHF64; } + bool canUseLAHFSAHF() const { return hasLAHFSAHF() || !is64Bit(); } bool hasMWAITX() const { return HasMWAITX; } bool hasCLZERO() const { return HasCLZERO; } bool hasCLDEMOTE() const { return HasCLDEMOTE; } -- 2.7.4