From 073294d3ef20d0dbeffcc38aff3d69eda624ee75 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Mon, 22 Jun 2015 17:01:22 -0700 Subject: [PATCH] i965/fs: Plumb compiler debug logging through brw_compiler Reviewed-by: Kenneth Graunke Reviewed-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_fs.cpp | 13 +++++++++---- src/mesa/drivers/dri/i965/brw_shader.cpp | 26 ++++++++++++++++++++++++++ src/mesa/drivers/dri/i965/brw_shader.h | 1 + 3 files changed, 36 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 3b311ca..0c11a9e 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -710,7 +710,9 @@ fs_visitor::no16(const char *msg) } else { simd16_unsupported = true; - perf_debug("SIMD16 shader failed to compile: %s", msg); + struct brw_compiler *compiler = brw->intelScreen->compiler; + compiler->shader_perf_log(brw, + "SIMD16 shader failed to compile: %s", msg); } } @@ -3800,9 +3802,12 @@ fs_visitor::allocate_registers() fail("Failure to register allocate. Reduce number of " "live scalar values to avoid this."); } else { - perf_debug("%s shader triggered register spilling. " - "Try reducing the number of live scalar values to " - "improve performance.\n", stage_name); + struct brw_compiler *compiler = brw->intelScreen->compiler; + compiler->shader_perf_log(brw, + "%s shader triggered register spilling. " + "Try reducing the number of live scalar " + "values to improve performance.\n", + stage_name); } /* Since we're out of heuristics, just go spill registers until we diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 6bc9dd9..42d6236 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -47,6 +47,31 @@ shader_debug_log_mesa(void *data, const char *fmt, ...) va_end(args); } +static void +shader_perf_log_mesa(void *data, const char *fmt, ...) +{ + struct brw_context *brw = (struct brw_context *)data; + + va_list args; + va_start(args, fmt); + + if (unlikely(INTEL_DEBUG & DEBUG_PERF)) { + va_list args_copy; + va_copy(args_copy, args); + vfprintf(stderr, fmt, args_copy); + va_end(args_copy); + } + + if (brw->perf_debug) { + GLuint msg_id = 0; + _mesa_gl_vdebug(&brw->ctx, &msg_id, + MESA_DEBUG_SOURCE_SHADER_COMPILER, + MESA_DEBUG_TYPE_PERFORMANCE, + MESA_DEBUG_SEVERITY_MEDIUM, fmt, args); + } + va_end(args); +} + struct brw_compiler * brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo) { @@ -54,6 +79,7 @@ brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo) compiler->devinfo = devinfo; compiler->shader_debug_log = shader_debug_log_mesa; + compiler->shader_perf_log = shader_perf_log_mesa; brw_fs_alloc_reg_sets(compiler); brw_vec4_alloc_reg_set(compiler); diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h index 30cca5c..fe510e7 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.h +++ b/src/mesa/drivers/dri/i965/brw_shader.h @@ -88,6 +88,7 @@ struct brw_compiler { } fs_reg_sets[2]; void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3); + void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3); }; enum PACKED register_file { -- 2.7.4