From 0699caae0f373930716ae91123adf255eac36ac4 Mon Sep 17 00:00:00 2001 From: Renlin Li Date: Mon, 26 Jan 2015 15:42:15 +0000 Subject: [PATCH] [AARCH64]Fix TLS local exec model addressing code generation inconsistency. gcc/ * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Correct the comment. * config/aarch64/aarch64.md * (tlsle_small_): Add left shift 12-bit for higher part. From-SVN: r220116 --- gcc/ChangeLog | 7 +++++++ gcc/config/aarch64/aarch64.c | 4 ++-- gcc/config/aarch64/aarch64.md | 2 +- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a567617..57fb5f1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2015-01-26 Renlin Li + + * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Correct + the comment. + * config/aarch64/aarch64.md (tlsle_small_): Add left shift 12-bit + for higher part. + 2015-01-26 Richard Biener PR middle-end/64764 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index dd49fcd..b923fdb 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -818,8 +818,8 @@ tls_symbolic_operand_type (rtx addr) Local Exec: mrs tp, tpidr_el0 - add t0, tp, #:tprel_hi12:imm - add t0, #:tprel_lo12_nc:imm + add t0, tp, #:tprel_hi12:imm, lsl #12 + add t0, t0, #:tprel_lo12_nc:imm */ static void diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index bc49fbe..b81ecb2 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4224,7 +4224,7 @@ (match_operand 2 "aarch64_tls_le_symref" "S")] UNSPEC_GOTSMALLTLS))] "" - "add\\t%0, %1, #%G2\;add\\t%0, %0, #%L2" + "add\\t%0, %1, #%G2, lsl #12\;add\\t%0, %0, #%L2" [(set_attr "type" "alu_sreg") (set_attr "length" "8")] ) -- 2.7.4