From 068ca03a3e0a906891babb64591012349cd86361 Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 6 Aug 2009 05:27:40 +0000 Subject: [PATCH] mips.h (TARGET_SYNC_AFTER_SC): New macro. 2009-08-04 David Daney * config/mips/mips.h (TARGET_SYNC_AFTER_SC): New macro. * mips_output_sync_loop (mips_output_sync_loop): Only emit trailing sync if TARGET_SYNC_AFTER_SC. From-SVN: r150513 --- gcc/ChangeLog | 6 ++++++ gcc/config/mips/mips.c | 12 ++++++++++-- gcc/config/mips/mips.h | 10 +++++++++- 3 files changed, 25 insertions(+), 3 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 077929d..db42dad 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2009-08-04 David Daney + + * config/mips/mips.h (TARGET_SYNC_AFTER_SC): New macro. + * mips_output_sync_loop (mips_output_sync_loop): Only emit + trailing sync if TARGET_SYNC_AFTER_SC. + 2009-08-05 David Daney * gcc/config/mips/sync.md (sync_compare_and_swap, diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index ade652c..1b9c6e7 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -10764,9 +10764,17 @@ mips_output_sync_loop (bool barrier_before, output_asm_insn ("sync", NULL); /* Use branch-likely instructions to work around the LL/SC R10000 errata. */ mips_branch_likely = TARGET_FIX_R10000; - output_asm_insn (loop, operands); - return "sync"; + /* If the target needs a sync after the loop, emit the loop now and + return the sync. */ + + if (TARGET_SYNC_AFTER_SC) + { + output_asm_insn (loop, operands); + loop = "sync"; + } + + return loop; } /* Return the assembly code for DIV or DDIV instruction DIVISION, which has diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 4ce9be3..89f9056 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -337,7 +337,15 @@ enum mips_code_readable_setting { in use. */ #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16) #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16) - + +/* False if SC acts as a memory barrier with respect to itself, + otherwise a SYNC will be emitted after SC for atomic operations + that require ordering between the SC and following loads and + stores. It does not tell anything about ordering of loads and + stores prior to and following the SC, only about the SC itself and + those loads and stores follow it. */ +#define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON) + /* IRIX specific stuff. */ #define TARGET_IRIX 0 #define TARGET_IRIX6 0 -- 2.7.4