From 0636aec3305ebc9a8ada43cd536615e4ea107be3 Mon Sep 17 00:00:00 2001 From: Alexey Baturo Date: Sun, 31 Jul 2022 13:39:08 +0300 Subject: [PATCH] [RISC-V][HWASAN] Add intrinsics required for HWASAN support for RISC-V Reviewed By: vitalybuka Differential Revision: https://reviews.llvm.org/D131340 --- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 9b5154d..9b536e8 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1666,6 +1666,13 @@ def : Pat<(trap), (UNIMP)>; // debugger if possible. def : Pat<(debugtrap), (EBREAK)>; +let Predicates = [IsRV64], Uses = [X5], + Defs = [X1, X6, X7, X28, X29, X30, X31] in +def HWASAN_CHECK_MEMACCESS_SHORTGRANULES + : Pseudo<(outs), (ins GPRJALR:$ptr, i32imm:$accessinfo), + [(int_hwasan_check_memaccess_shortgranules X5, GPRJALR:$ptr, + (i32 timm:$accessinfo))]>; + /// Simple optimization def : Pat<(add GPR:$rs1, (AddiPair:$rs2)), (ADDI (ADDI GPR:$rs1, (AddiPairImmLarge AddiPair:$rs2)), -- 2.7.4