From 05db279f528435890314d11737d706719269c8be Mon Sep 17 00:00:00 2001 From: Simon Atanasyan Date: Thu, 10 May 2018 16:01:36 +0000 Subject: [PATCH] [mips] Accept 32-bit offsets for ld/sd/lld commands This is a follow up to the rL330983. The patch teaches ld, sd, and lld commands accept 32-bit memory offsets by replacing `mem_simm16` operand to `mem_simmptr`. In fact, these commands should accept 64-bit offsets, but so large offsets require another command expanding and will be supported by a separate patch. Differential Revision: https://reviews.llvm.org/D46629 llvm-svn: 331997 --- llvm/lib/Target/Mips/Mips64InstrInfo.td | 6 +++--- llvm/lib/Target/Mips/Mips64r6InstrInfo.td | 2 +- llvm/test/MC/Mips/mips64-expansions.s | 32 +++++++++++++++++++++++++++++++ llvm/test/MC/Mips/mips64r6/invalid.s | 12 ++++++------ 4 files changed, 42 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index 8da35bb..710b5c2 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -189,9 +189,9 @@ def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>; let AdditionalPredicates = [NotInMicroMips] in { def LWu : MMRel, Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>, ISA_MIPS3; - def LD : LoadMemory<"ld", GPR64Opnd, mem_simm16, load, II_LD>, + def LD : LoadMemory<"ld", GPR64Opnd, mem_simmptr, load, II_LD>, LW_FM<0x37>, ISA_MIPS3; - def SD : StoreMemory<"sd", GPR64Opnd, mem_simm16, store, II_SD>, + def SD : StoreMemory<"sd", GPR64Opnd, mem_simmptr, store, II_SD>, LW_FM<0x3f>, ISA_MIPS3; } @@ -216,7 +216,7 @@ def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>, /// Load-linked, Store-conditional let AdditionalPredicates = [NotInMicroMips] in { - def LLD : LLBase<"lld", GPR64Opnd, mem_simm16>, LW_FM<0x34>, + def LLD : LLBase<"lld", GPR64Opnd, mem_simmptr>, LW_FM<0x34>, ISA_MIPS3_NOT_32R6_64R6; } def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6; diff --git a/llvm/lib/Target/Mips/Mips64r6InstrInfo.td b/llvm/lib/Target/Mips/Mips64r6InstrInfo.td index a192d07..853702c 100644 --- a/llvm/lib/Target/Mips/Mips64r6InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64r6InstrInfo.td @@ -73,7 +73,7 @@ class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU, mulhu>; class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>; class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMUL>; class LDPC_DESC : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3, II_LDPC>; -class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd, mem_simm16, II_LLD>; +class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd, mem_simmptr, II_LLD>; class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>; class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>; class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>; diff --git a/llvm/test/MC/Mips/mips64-expansions.s b/llvm/test/MC/Mips/mips64-expansions.s index f84ee8a..841593e 100644 --- a/llvm/test/MC/Mips/mips64-expansions.s +++ b/llvm/test/MC/Mips/mips64-expansions.s @@ -269,3 +269,35 @@ sym: # CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00] # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] # CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + +# Test ld/sd/lld with offsets exceed 16-bit size. + + ld $4, 0x8000 +# CHECK: lui $4, 1 +# CHECK-NEXT: addu $4, $4, $zero +# CHECK-NEXT: ld $4, -32768($4) + + ld $4, 0x20008($3) +# CHECK: lui $4, 2 +# CHECK-NEXT: addu $4, $4, $3 +# CHECK-NEXT: ld $4, 8($4) + + sd $4, 0x8000 +# CHECK: lui $1, 1 +# CHECK-NEXT: addu $1, $1, $zero +# CHECK-NEXT: sd $4, -32768($1) + + sd $4, 0x20008($3) +# CHECK: lui $1, 2 +# CHECK-NEXT: addu $1, $1, $3 +# CHECK-NEXT: sd $4, 8($1) + + lld $4, 0x8000 +# CHECK: lui $4, 1 +# CHECK-NEXT: addu $4, $4, $zero +# CHECK-NEXT: lld $4, -32768($4) + + lld $4, 0x20008($3) +# CHECK: lui $4, 2 +# CHECK-NEXT: addu $4, $4, $3 +# CHECK-NEXT: lld $4, 8($4) diff --git a/llvm/test/MC/Mips/mips64r6/invalid.s b/llvm/test/MC/Mips/mips64r6/invalid.s index e9cdc04..e355469 100644 --- a/llvm/test/MC/Mips/mips64r6/invalid.s +++ b/llvm/test/MC/Mips/mips64r6/invalid.s @@ -178,14 +178,14 @@ local_label: dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate - ld $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - ld $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + ld $2, 2147483648($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset + ld $2, -2147483649($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset ld $32, 65536($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number - lld $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lld $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - sd $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lld $2, -2147483649($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset + lld $2, 2147483648($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset + sd $2, -2147483649($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset lld $32, 4096($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number - sd $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + sd $2, 2147483648($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset sd $32, 65536($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number dsrl $2, $4, 64 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate dsrl $2, $4, -2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate -- 2.7.4