From 05da025f350cb83e1125d6a931ccf9a87223bb69 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Mon, 2 Sep 2019 14:44:51 -0400 Subject: [PATCH] etnaviv: fix two-sided stencil * Set missing STENCIL_CONFIG_EXT2 bits * Swap stencil sides when rendering CCW Fixes following deqp tests (which were 99% failing): dEQP-GLES2.functional.fragment_ops.depth_stencil.* Note: deqp tests require --deqp-gl-config-name=rgba8888d24s8ms0 Signed-off-by: Jonathan Marek Reviewed-by: Christian Gmeiner --- src/gallium/drivers/etnaviv/etnaviv_emit.c | 20 +++++++++------ src/gallium/drivers/etnaviv/etnaviv_internal.h | 4 +-- src/gallium/drivers/etnaviv/etnaviv_state.c | 10 +++++--- src/gallium/drivers/etnaviv/etnaviv_zsa.c | 34 ++++++++++++++------------ src/gallium/drivers/etnaviv/etnaviv_zsa.h | 6 +++-- 5 files changed, 44 insertions(+), 30 deletions(-) diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c b/src/gallium/drivers/etnaviv/etnaviv_emit.c index 74bc372..a9ed1f6 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_emit.c +++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c @@ -214,6 +214,8 @@ void etna_emit_state(struct etna_context *ctx) { struct etna_cmd_stream *stream = ctx->stream; + unsigned ccw = ctx->rasterizer->front_ccw; + /* Pre-reserve the command buffer space which we are likely to need. * This must cover all the state emitted below, and the following @@ -466,13 +468,14 @@ etna_emit_state(struct etna_context *ctx) /*01414*/ EMIT_STATE(PE_DEPTH_STRIDE, ctx->framebuffer.PE_DEPTH_STRIDE); } - if (unlikely(dirty & (ETNA_DIRTY_ZSA))) { - uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_OP; + + if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_RASTERIZER))) { + uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_OP[ccw]; /*01418*/ EMIT_STATE(PE_STENCIL_OP, val); } - if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_STENCIL_REF))) { - uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG; - /*0141C*/ EMIT_STATE(PE_STENCIL_CONFIG, val | ctx->stencil_ref.PE_STENCIL_CONFIG); + if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_STENCIL_REF | ETNA_DIRTY_RASTERIZER))) { + uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG[ccw]; + /*0141C*/ EMIT_STATE(PE_STENCIL_CONFIG, val | ctx->stencil_ref.PE_STENCIL_CONFIG[ccw]); } if (unlikely(dirty & (ETNA_DIRTY_ZSA))) { uint32_t val = etna_zsa_state(ctx->zsa)->PE_ALPHA_OP; @@ -511,8 +514,8 @@ etna_emit_state(struct etna_context *ctx) abort(); } } - if (unlikely(dirty & (ETNA_DIRTY_STENCIL_REF))) { - /*014A0*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT, ctx->stencil_ref.PE_STENCIL_CONFIG_EXT); + if (unlikely(dirty & (ETNA_DIRTY_STENCIL_REF | ETNA_DIRTY_RASTERIZER))) { + /*014A0*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT, ctx->stencil_ref.PE_STENCIL_CONFIG_EXT[ccw]); } if (unlikely(dirty & (ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER))) { struct etna_blend_state *blend = etna_blend_state(ctx->blend); @@ -528,6 +531,9 @@ etna_emit_state(struct etna_context *ctx) /*014B0*/ EMIT_STATE(PE_ALPHA_COLOR_EXT0, ctx->blend_color.PE_ALPHA_COLOR_EXT0); /*014B4*/ EMIT_STATE(PE_ALPHA_COLOR_EXT1, ctx->blend_color.PE_ALPHA_COLOR_EXT1); } + if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_RASTERIZER))) { + /*014B8*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT2, etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG_EXT2[ccw]); + } if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER)) && ctx->specs.halti >= 3) /*014BC*/ EMIT_STATE(PE_MEM_CONFIG, ctx->framebuffer.PE_MEM_CONFIG); if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_TS))) { diff --git a/src/gallium/drivers/etnaviv/etnaviv_internal.h b/src/gallium/drivers/etnaviv/etnaviv_internal.h index 1f70a1c..82315e0 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_internal.h +++ b/src/gallium/drivers/etnaviv/etnaviv_internal.h @@ -152,8 +152,8 @@ struct compiled_blend_color { /* Compiled pipe_stencil_ref */ struct compiled_stencil_ref { - uint32_t PE_STENCIL_CONFIG; - uint32_t PE_STENCIL_CONFIG_EXT; + uint32_t PE_STENCIL_CONFIG[2]; + uint32_t PE_STENCIL_CONFIG_EXT[2]; }; /* Compiled pipe_scissor_state */ diff --git a/src/gallium/drivers/etnaviv/etnaviv_state.c b/src/gallium/drivers/etnaviv/etnaviv_state.c index 4884865..c629aab 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_state.c +++ b/src/gallium/drivers/etnaviv/etnaviv_state.c @@ -52,10 +52,12 @@ etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref *s ctx->stencil_ref_s = *sr; - cs->PE_STENCIL_CONFIG = VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[0]); - /* rest of bits weaved in from depth_stencil_alpha */ - cs->PE_STENCIL_CONFIG_EXT = - VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[0]); + for (unsigned i = 0; i < 2; i++) { + cs->PE_STENCIL_CONFIG[i] = + VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[i]); + cs->PE_STENCIL_CONFIG_EXT[i] = + VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[!i]); + } ctx->dirty |= ETNA_DIRTY_STENCIL_REF; } diff --git a/src/gallium/drivers/etnaviv/etnaviv_zsa.c b/src/gallium/drivers/etnaviv/etnaviv_zsa.c index 4e72cd2..a677e25 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_zsa.c +++ b/src/gallium/drivers/etnaviv/etnaviv_zsa.c @@ -104,21 +104,25 @@ etna_zsa_state_create(struct pipe_context *pctx, COND(so->alpha.enabled, VIVS_PE_ALPHA_OP_ALPHA_TEST) | VIVS_PE_ALPHA_OP_ALPHA_FUNC(so->alpha.func) | VIVS_PE_ALPHA_OP_ALPHA_REF(etna_cfloat_to_uint8(so->alpha.ref_value)); - cs->PE_STENCIL_OP = - VIVS_PE_STENCIL_OP_FUNC_FRONT(so->stencil[0].func) | - VIVS_PE_STENCIL_OP_FUNC_BACK(so->stencil[1].func) | - VIVS_PE_STENCIL_OP_FAIL_FRONT(translate_stencil_op(so->stencil[0].fail_op)) | - VIVS_PE_STENCIL_OP_FAIL_BACK(translate_stencil_op(so->stencil[1].fail_op)) | - VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(translate_stencil_op(so->stencil[0].zfail_op)) | - VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(translate_stencil_op(so->stencil[1].zfail_op)) | - VIVS_PE_STENCIL_OP_PASS_FRONT(translate_stencil_op(so->stencil[0].zpass_op)) | - VIVS_PE_STENCIL_OP_PASS_BACK(translate_stencil_op(so->stencil[1].zpass_op)); - cs->PE_STENCIL_CONFIG = - translate_stencil_mode(so->stencil[0].enabled, so->stencil[1].enabled) | - VIVS_PE_STENCIL_CONFIG_MASK_FRONT(so->stencil[0].valuemask) | - VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT(so->stencil[0].writemask); - /* XXX back masks in VIVS_PE_DEPTH_CONFIG_EXT? */ - /* XXX VIVS_PE_STENCIL_CONFIG_REF_FRONT comes from pipe_stencil_ref */ + + for (unsigned i = 0; i < 2; i++) { + cs->PE_STENCIL_OP[i] = + VIVS_PE_STENCIL_OP_FUNC_FRONT(so->stencil[i].func) | + VIVS_PE_STENCIL_OP_FUNC_BACK(so->stencil[!i].func) | + VIVS_PE_STENCIL_OP_FAIL_FRONT(translate_stencil_op(so->stencil[i].fail_op)) | + VIVS_PE_STENCIL_OP_FAIL_BACK(translate_stencil_op(so->stencil[!i].fail_op)) | + VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(translate_stencil_op(so->stencil[i].zfail_op)) | + VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(translate_stencil_op(so->stencil[!i].zfail_op)) | + VIVS_PE_STENCIL_OP_PASS_FRONT(translate_stencil_op(so->stencil[i].zpass_op)) | + VIVS_PE_STENCIL_OP_PASS_BACK(translate_stencil_op(so->stencil[!i].zpass_op)); + cs->PE_STENCIL_CONFIG[i] = + translate_stencil_mode(so->stencil[i].enabled, so->stencil[!i].enabled) | + VIVS_PE_STENCIL_CONFIG_MASK_FRONT(so->stencil[i].valuemask) | + VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT(so->stencil[i].writemask); + cs->PE_STENCIL_CONFIG_EXT2[i] = + VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK(so->stencil[!i].valuemask) | + VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(so->stencil[!i].writemask); + } /* XXX does alpha/stencil test affect PE_COLOR_FORMAT_OVERWRITE? */ return cs; diff --git a/src/gallium/drivers/etnaviv/etnaviv_zsa.h b/src/gallium/drivers/etnaviv/etnaviv_zsa.h index 953a6a7..21a89c0 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_zsa.h +++ b/src/gallium/drivers/etnaviv/etnaviv_zsa.h @@ -35,8 +35,10 @@ struct etna_zsa_state { uint32_t PE_DEPTH_CONFIG; uint32_t PE_ALPHA_OP; - uint32_t PE_STENCIL_OP; - uint32_t PE_STENCIL_CONFIG; + uint32_t PE_STENCIL_OP[2]; + uint32_t PE_STENCIL_CONFIG[2]; + uint32_t PE_STENCIL_CONFIG_EXT2[2]; + }; static inline struct etna_zsa_state * -- 2.7.4