From 05d495014ecc0fe9951d1225af380f9a1f51058b Mon Sep 17 00:00:00 2001 From: Alan Modra Date: Sun, 14 Jul 2002 14:28:14 +0000 Subject: [PATCH] re PR target/7282 (unrecognizable insn) PR target/7282 * config/rs6000/rs6000.md (floatsidf2): Enable for POWERPC64. (floatunssidf2): Likewise. (floatsidf_ppc64): New insn_and_split. (floatunssidf_ppc64): Likewise. From-SVN: r55443 --- gcc/ChangeLog | 8 +++++++ gcc/config/rs6000/rs6000.md | 53 +++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 59 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 20e3988..14440b5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2002-07-14 Alan Modra + + PR target/7282 + * config/rs6000/rs6000.md (floatsidf2): Enable for POWERPC64. + (floatunssidf2): Likewise. + (floatsidf_ppc64): New insn_and_split. + (floatunssidf_ppc64): Likewise. + 2002-07-14 Andreas Jaeger * config.gcc (sh64): Remove unused diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 338bd86..aa7cb3a 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5350,9 +5350,18 @@ (clobber (match_dup 4)) (clobber (match_dup 5)) (clobber (match_dup 6))])] - "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT" " { + if (TARGET_POWERPC64) + { + rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); + rtx t1 = gen_reg_rtx (DImode); + rtx t2 = gen_reg_rtx (DImode); + emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2)); + DONE; + } + operands[2] = force_reg (SImode, GEN_INT (0x43300000)); operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode)); operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); @@ -5417,9 +5426,19 @@ (use (match_dup 3)) (clobber (match_dup 4)) (clobber (match_dup 5))])] - "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT" " { + if (TARGET_POWERPC64) + { + rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); + rtx t1 = gen_reg_rtx (DImode); + rtx t2 = gen_reg_rtx (DImode); + emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem, + t1, t2)); + DONE; + } + operands[2] = force_reg (SImode, GEN_INT (0x43300000)); operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); @@ -5535,6 +5554,36 @@ "fcfid %0,%1" [(set_attr "type" "fp")]) +(define_insn_and_split "floatsidf_ppc64" + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) + (clobber (match_operand:DI 2 "memory_operand" "=o")) + (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) + (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] + "TARGET_POWERPC64 && TARGET_HARD_FLOAT" + "#" + "" + [(set (match_dup 3) (sign_extend:DI (match_dup 1))) + (set (match_dup 2) (match_dup 3)) + (set (match_dup 4) (match_dup 2)) + (set (match_dup 0) (float:DF (match_dup 4)))] + "") + +(define_insn_and_split "floatunssidf_ppc64" + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) + (clobber (match_operand:DI 2 "memory_operand" "=o")) + (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) + (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] + "TARGET_POWERPC64 && TARGET_HARD_FLOAT" + "#" + "" + [(set (match_dup 3) (zero_extend:DI (match_dup 1))) + (set (match_dup 2) (match_dup 3)) + (set (match_dup 4) (match_dup 2)) + (set (match_dup 0) (float:DF (match_dup 4)))] + "") + (define_insn "fix_truncdfdi2" [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] -- 2.7.4