From 05baf681a3c2c5072b6992deb255c7835ba50689 Mon Sep 17 00:00:00 2001
From: Dmitry Preobrazhensky <dmitri.preobrazhenski@gmail.com>
Date: Fri, 11 Nov 2022 13:14:42 +0300
Subject: [PATCH] [AMDGPU][MC] Disable SGPRs as src operands of VOP3 VINTRP
 instructions

Differential Revision: https://reviews.llvm.org/D137575
---
 llvm/lib/Target/AMDGPU/VOP3Instructions.td |  4 +++
 llvm/test/MC/AMDGPU/vintrp-e64-err.s       | 45 ++++++++++++++++++++++++++++++
 2 files changed, 49 insertions(+)
 create mode 100644 llvm/test/MC/AMDGPU/vintrp-e64-err.s

diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index fdbdfe5..c412a18 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -59,6 +59,7 @@ class VOP3Interp<string OpName, VOPProfile P, list<dag> pattern = []> :
 }
 
 def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> {
+  let Src0Mod = FPVRegInputMods;
   let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
                    Attr:$attr, AttrChan:$attrchan,
                    clampmod0:$clamp, omod0:$omod);
@@ -108,6 +109,9 @@ class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
   let HasOMod = !ne(DstVT.Value, f16.Value);
   let HasHigh = 1;
 
+  let Src0Mod = FPVRegInputMods;
+  let Src2Mod = FPVRegInputMods;
+
   let Outs64 = (outs DstRC.RegClass:$vdst);
   let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret;
   let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret;
diff --git a/llvm/test/MC/AMDGPU/vintrp-e64-err.s b/llvm/test/MC/AMDGPU/vintrp-e64-err.s
new file mode 100644
index 0000000..7179e4b
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/vintrp-e64-err.s
@@ -0,0 +1,45 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --implicit-check-not=error:
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --implicit-check-not=error:
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck %s --implicit-check-not=error:
+
+v_interp_p1_f32_e64 v5, 0.5, attr0.w
+// CHECK: error: invalid operand for instruction
+
+v_interp_p1_f32_e64 v5, s1, attr0.w
+// CHECK: error: invalid operand for instruction
+
+v_interp_p1ll_f16 v5, 0.5, attr0.w
+// CHECK: error: invalid operand for instruction
+
+v_interp_p1ll_f16 v5, s1, attr0.w
+// CHECK: error: invalid operand for instruction
+
+v_interp_p1lv_f16 v5, 0.5, attr0.w, v3
+// CHECK: error: invalid operand for instruction
+
+v_interp_p1lv_f16 v5, s1, attr0.w, v3
+// CHECK: error: invalid operand for instruction
+
+v_interp_p1lv_f16 v5, v1, attr31.w, 0.5
+// CHECK: error: invalid operand for instruction
+
+v_interp_p1lv_f16 v5, v1, attr31.w, s1
+// CHECK: error: invalid operand for instruction
+
+v_interp_p2_f16 v5, 0.5, attr0.w, v3
+// CHECK: error: invalid operand for instruction
+
+v_interp_p2_f16 v5, s1, attr0.w, v3
+// CHECK: error: invalid operand for instruction
+
+v_interp_p2_f16 v5, v1, attr1.w, 0.5
+// CHECK: error: invalid operand for instruction
+
+v_interp_p2_f16 v5, v1, attr1.w, s1
+// CHECK: error: invalid operand for instruction
+
+v_interp_p2_f32_e64 v5, 0.5, attr31.w
+// CHECK: error: invalid operand for instruction
+
+v_interp_p2_f32_e64 v5, s1, attr31.w
+// CHECK: error: invalid operand for instruction
-- 
2.7.4