From 05a41340e56f716ef9f83006990f6eea153c5fe0 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 24 Feb 2022 11:17:09 +0000 Subject: [PATCH] ASoC: codecs: wsa-macro: setup soundwire clks correctly For SoundWire Frame sync to be generated correctly we need both MCLK and MCLKx2 (npl). Without pm runtime enabled these two clocks will remain on, however after adding pm runtime support its possible that NPl clock could be turned off even when SoundWire controller is active. Fix this by enabling mclk and npl clk when SoundWire clks are enabled. Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20220224111718.6264-8-srinivas.kandagatla@linaro.org Signed-off-by: Mark Brown --- sound/soc/codecs/lpass-wsa-macro.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/sound/soc/codecs/lpass-wsa-macro.c b/sound/soc/codecs/lpass-wsa-macro.c index c7b08a2..94b8e2c 100644 --- a/sound/soc/codecs/lpass-wsa-macro.c +++ b/sound/soc/codecs/lpass-wsa-macro.c @@ -2260,6 +2260,13 @@ static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable) struct regmap *regmap = wsa->regmap; if (enable) { + int ret; + + ret = clk_prepare_enable(wsa->mclk); + if (ret) { + dev_err(wsa->dev, "failed to enable mclk\n"); + return ret; + } wsa_macro_mclk_enable(wsa, true); /* reset swr ip */ @@ -2284,6 +2291,7 @@ static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable) regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, CDC_WSA_SWR_CLK_EN_MASK, 0); wsa_macro_mclk_enable(wsa, false); + clk_disable_unprepare(wsa->mclk); } return 0; @@ -2354,7 +2362,7 @@ static int wsa_macro_register_mclk_output(struct wsa_macro *wsa) struct clk_init_data init; int ret; - parent_clk_name = __clk_get_name(wsa->mclk); + parent_clk_name = __clk_get_name(wsa->npl); init.name = clk_name; init.ops = &swclk_gate_ops; -- 2.7.4