From 059b5d90770e32ba3d6d9a62acf74b352de7f421 Mon Sep 17 00:00:00 2001 From: Oliver McFadden Date: Mon, 9 Apr 2007 23:23:40 +0000 Subject: [PATCH] rs480: Renamed some unknown registers. See dri-devel list. --- shared-core/radeon_cp.c | 14 +++++++------- shared-core/radeon_drv.h | 4 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index a741eb7..bfc2d08 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -1289,7 +1289,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) dev_priv->gart_size); RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000); - RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_38, 0x1); + RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1); RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800); RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR, dev_priv->gart_info.bus_addr); @@ -1304,13 +1304,13 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) dev_priv->gart_size) & 0xffff0000) | (dev_priv->gart_vm_start >> 16))); - temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_38); - RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_38, temp); + temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE); + RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp); - RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_2E); - RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_2E, 0x1); - RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_2E); - RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_2E, 0x0); + RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH); + RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1); + RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH); + RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0); } } diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 950f682..00646c8 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -439,8 +439,8 @@ extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp, #define RADEON_IGPGART_UNK_18 0x18 #define RADEON_IGPGART_CTRL 0x2b #define RADEON_IGPGART_BASE_ADDR 0x2c -#define RADEON_IGPGART_UNK_2E 0x2e -#define RADEON_IGPGART_UNK_38 0x38 +#define RADEON_IGPGART_FLUSH 0x2e +#define RADEON_IGPGART_ENABLE 0x38 #define RADEON_IGPGART_UNK_39 0x39 -- 2.7.4