From 05915400b7f9933b95686116f2dc1370e7f96cfb Mon Sep 17 00:00:00 2001 From: Caroline Tice Date: Tue, 29 Jun 2021 14:50:10 -0700 Subject: [PATCH] [lldb] Replace SVE_PT* macros in NativeRegisterContextLinux_arm64.{cpp,h} with their equivalent defintions in LinuxPTraceDefines_arm64sve.h Commit 090306fc80dbf (August 2020) changed most of the arm64 SVE_PT* macros, but apparently did not make the changes in the NativeRegisterContextLinux_arm64.* files (or those files were pulled over from someplace else after that commit). This change replaces the macros NativeRegisterContextLinux_arm64.cpp with the replacement definitions in LinuxPTraceDefines_arm64sve.h. It also includes LinuxPTraceDefines_arm64sve.h in NativeRegisterContextLinux_arm64.h. Differential Revision: https://reviews.llvm.org/D104826 --- .../Linux/NativeRegisterContextLinux_arm64.cpp | 36 ++++++++++++---------- .../Linux/NativeRegisterContextLinux_arm64.h | 3 +- 2 files changed, 21 insertions(+), 18 deletions(-) diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp index f78c0d2..a0672a6 100644 --- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp +++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp @@ -58,7 +58,7 @@ NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux( switch (target_arch.GetMachine()) { case llvm::Triple::arm: return std::make_unique(target_arch, - native_thread); + native_thread); case llvm::Triple::aarch64: { // Configure register sets supported by this AArch64 target. // Read SVE header to check for SVE support. @@ -207,15 +207,15 @@ NativeRegisterContextLinux_arm64::ReadRegister(const RegisterInfo *reg_info, if (reg == GetRegisterInfo().GetRegNumFPSR()) { sve_reg_num = reg; if (m_sve_state == SVEState::Full) - offset = SVE_PT_SVE_FPSR_OFFSET(sve_vq_from_vl(m_sve_header.vl)); + offset = sve::PTraceFPSROffset(sve::vq_from_vl(m_sve_header.vl)); else if (m_sve_state == SVEState::FPSIMD) - offset = SVE_PT_FPSIMD_OFFSET + (32 * 16); + offset = sve::ptrace_fpsimd_offset + (32 * 16); } else if (reg == GetRegisterInfo().GetRegNumFPCR()) { sve_reg_num = reg; if (m_sve_state == SVEState::Full) - offset = SVE_PT_SVE_FPCR_OFFSET(sve_vq_from_vl(m_sve_header.vl)); + offset = sve::PTraceFPCROffset(sve::vq_from_vl(m_sve_header.vl)); else if (m_sve_state == SVEState::FPSIMD) - offset = SVE_PT_FPSIMD_OFFSET + (32 * 16) + 4; + offset = sve::ptrace_fpsimd_offset + (32 * 16) + 4; } else { // Extract SVE Z register value register number for this reg_info if (reg_info->value_regs && @@ -341,15 +341,15 @@ Status NativeRegisterContextLinux_arm64::WriteRegister( if (reg == GetRegisterInfo().GetRegNumFPSR()) { sve_reg_num = reg; if (m_sve_state == SVEState::Full) - offset = SVE_PT_SVE_FPSR_OFFSET(sve_vq_from_vl(m_sve_header.vl)); + offset = sve::PTraceFPSROffset(sve::vq_from_vl(m_sve_header.vl)); else if (m_sve_state == SVEState::FPSIMD) - offset = SVE_PT_FPSIMD_OFFSET + (32 * 16); + offset = sve::ptrace_fpsimd_offset + (32 * 16); } else if (reg == GetRegisterInfo().GetRegNumFPCR()) { sve_reg_num = reg; if (m_sve_state == SVEState::Full) - offset = SVE_PT_SVE_FPCR_OFFSET(sve_vq_from_vl(m_sve_header.vl)); + offset = sve::PTraceFPCROffset(sve::vq_from_vl(m_sve_header.vl)); else if (m_sve_state == SVEState::FPSIMD) - offset = SVE_PT_FPSIMD_OFFSET + (32 * 16) + 4; + offset = sve::ptrace_fpsimd_offset + (32 * 16) + 4; } else { // Extract SVE Z register value register number for this reg_info if (reg_info->value_regs && @@ -824,19 +824,21 @@ void NativeRegisterContextLinux_arm64::ConfigureRegisterContext() { if (error.Success()) { // If SVE is enabled thread can switch between SVEState::FPSIMD and // SVEState::Full on every stop. - if ((m_sve_header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD) + if ((m_sve_header.flags & sve::ptrace_regs_mask) == + sve::ptrace_regs_fpsimd) m_sve_state = SVEState::FPSIMD; - else if ((m_sve_header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE) + else if ((m_sve_header.flags & sve::ptrace_regs_mask) == + sve::ptrace_regs_sve) m_sve_state = SVEState::Full; // On every stop we configure SVE vector length by calling // ConfigureVectorLength regardless of current SVEState of this thread. uint32_t vq = RegisterInfoPOSIX_arm64::eVectorQuadwordAArch64SVE; if (sve_vl_valid(m_sve_header.vl)) - vq = sve_vq_from_vl(m_sve_header.vl); + vq = sve::vq_from_vl(m_sve_header.vl); GetRegisterInfo().ConfigureVectorLength(vq); - m_sve_ptrace_payload.resize(SVE_PT_SIZE(vq, SVE_PT_REGS_SVE)); + m_sve_ptrace_payload.resize(sve::PTraceSize(vq, sve::ptrace_regs_sve)); } } } @@ -852,19 +854,19 @@ uint32_t NativeRegisterContextLinux_arm64::CalculateSVEOffset( uint32_t sve_reg_offset = LLDB_INVALID_INDEX32; if (m_sve_state == SVEState::FPSIMD) { const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB]; - sve_reg_offset = - SVE_PT_FPSIMD_OFFSET + (reg - GetRegisterInfo().GetRegNumSVEZ0()) * 16; + sve_reg_offset = sve::ptrace_fpsimd_offset + + (reg - GetRegisterInfo().GetRegNumSVEZ0()) * 16; } else if (m_sve_state == SVEState::Full) { uint32_t sve_z0_offset = GetGPRSize() + 16; sve_reg_offset = - SVE_SIG_REGS_OFFSET + reg_info->byte_offset - sve_z0_offset; + sve::SigRegsOffset() + reg_info->byte_offset - sve_z0_offset; } return sve_reg_offset; } void *NativeRegisterContextLinux_arm64::GetSVEBuffer() { if (m_sve_state == SVEState::FPSIMD) - return m_sve_ptrace_payload.data() + SVE_PT_FPSIMD_OFFSET; + return m_sve_ptrace_payload.data() + sve::ptrace_fpsimd_offset; return m_sve_ptrace_payload.data(); } diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h index f19b047..6b56660 100644 --- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h +++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h @@ -12,6 +12,7 @@ #define lldb_NativeRegisterContextLinux_arm64_h #include "Plugins/Process/Linux/NativeRegisterContextLinux.h" +#include "Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h" #include "Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.h" #include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h" @@ -90,7 +91,7 @@ private: m_fpr; // floating-point registers including extended register sets. SVEState m_sve_state; - struct user_sve_header m_sve_header; + struct sve::user_sve_header m_sve_header; std::vector m_sve_ptrace_payload; bool m_refresh_hwdebug_info; -- 2.7.4