From 0537deb5cddbf8f4c512e848bfd0220b7ed29c3c Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Mon, 12 Feb 2018 22:19:24 +0000
Subject: [PATCH] [x86] add select test to show there's no single right answer
 (PR28968); NFC

llvm-svn: 324947
---
 llvm/test/CodeGen/X86/select-1-or-neg1.ll | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/select-1-or-neg1.ll

diff --git a/llvm/test/CodeGen/X86/select-1-or-neg1.ll b/llvm/test/CodeGen/X86/select-1-or-neg1.ll
new file mode 100644
index 0000000..b0244fe
--- /dev/null
+++ b/llvm/test/CodeGen/X86/select-1-or-neg1.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown                      | FileCheck %s --check-prefix=BASE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=slow-3ops-lea | FileCheck %s --check-prefix=SLOWLEA3
+
+; TODO: Should the 'cmpl' be 'dec' instead?
+; TODO: What if 'cmov' is 1 uop and full throughput (Ryzen)?
+
+define i32 @PR28968(i32 %x) {
+; BASE-LABEL: PR28968:
+; BASE:       # %bb.0:
+; BASE-NEXT:    xorl %eax, %eax
+; BASE-NEXT:    cmpl $1, %edi
+; BASE-NEXT:    sete %al
+; BASE-NEXT:    leal -1(%rax,%rax), %eax
+; BASE-NEXT:    retq
+;
+; SLOWLEA3-LABEL: PR28968:
+; SLOWLEA3:       # %bb.0:
+; SLOWLEA3-NEXT:    xorl %eax, %eax
+; SLOWLEA3-NEXT:    cmpl $1, %edi
+; SLOWLEA3-NEXT:    sete %al
+; SLOWLEA3-NEXT:    leal (%rax,%rax), %eax
+; SLOWLEA3-NEXT:    addl $-1, %eax
+; SLOWLEA3-NEXT:    retq
+  %cmp = icmp eq i32 %x, 1
+  %sel = select i1 %cmp, i32 1, i32 -1
+  ret i32 %sel
+}
+
-- 
2.7.4