From 052d1b7b66a745f8ae5971899a32aefc4a409865 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Fri, 15 Mar 2019 18:14:25 +0000 Subject: [PATCH] [InstCombine] add tests for logic of NaN fcmps; NFC llvm-svn: 356287 --- llvm/test/Transforms/InstCombine/and-fcmp.ll | 34 ++++++++++++++++++++++++++++ llvm/test/Transforms/InstCombine/or-fcmp.ll | 34 ++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/llvm/test/Transforms/InstCombine/and-fcmp.ll b/llvm/test/Transforms/InstCombine/and-fcmp.ll index d2c1f13..56954df 100644 --- a/llvm/test/Transforms/InstCombine/and-fcmp.ll +++ b/llvm/test/Transforms/InstCombine/and-fcmp.ll @@ -23,6 +23,40 @@ define <2 x i1> @PR1738_vec_undef(<2 x double> %x, <2 x double> %y) { ret <2 x i1> %or } +define i1 @PR41069(float %a, float %b, float %c, float %d) { +; CHECK-LABEL: @PR41069( +; CHECK-NEXT: [[ORD1:%.*]] = fcmp ord float [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: [[ORD2:%.*]] = fcmp ord float [[C:%.*]], 0.000000e+00 +; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD1]], [[ORD2]] +; CHECK-NEXT: [[ORD3:%.*]] = fcmp ord float [[D:%.*]], 0.000000e+00 +; CHECK-NEXT: [[R:%.*]] = and i1 [[AND]], [[ORD3]] +; CHECK-NEXT: ret i1 [[R]] +; + %ord1 = fcmp ord float %a, %b + %ord2 = fcmp ord float %c, 0.0 + %and = and i1 %ord1, %ord2 + %ord3 = fcmp ord float %d, 0.0 + %r = and i1 %and, %ord3 + ret i1 %r +} + +define <2 x i1> @PR41069_vec(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) { +; CHECK-LABEL: @PR41069_vec( +; CHECK-NEXT: [[ORD1:%.*]] = fcmp ord <2 x double> [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: [[ORD2:%.*]] = fcmp ord <2 x double> [[C:%.*]], +; CHECK-NEXT: [[AND:%.*]] = and <2 x i1> [[ORD1]], [[ORD2]] +; CHECK-NEXT: [[ORD3:%.*]] = fcmp ord <2 x double> [[D:%.*]], zeroinitializer +; CHECK-NEXT: [[R:%.*]] = and <2 x i1> [[AND]], [[ORD3]] +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %ord1 = fcmp ord <2 x double> %a, %b + %ord2 = fcmp ord <2 x double> %c, + %and = and <2 x i1> %ord1, %ord2 + %ord3 = fcmp ord <2 x double> %d, zeroinitializer + %r = and <2 x i1> %and, %ord3 + ret <2 x i1> %r +} + define i1 @PR15737(float %a, double %b) { ; CHECK-LABEL: @PR15737( ; CHECK-NEXT: [[CMP:%.*]] = fcmp ord float [[A:%.*]], 0.000000e+00 diff --git a/llvm/test/Transforms/InstCombine/or-fcmp.ll b/llvm/test/Transforms/InstCombine/or-fcmp.ll index fd46718..3887216 100644 --- a/llvm/test/Transforms/InstCombine/or-fcmp.ll +++ b/llvm/test/Transforms/InstCombine/or-fcmp.ll @@ -23,6 +23,40 @@ define <2 x i1> @PR1738_vec_undef(<2 x double> %x, <2 x double> %y) { ret <2 x i1> %or } +define i1 @PR41069(double %a, double %b, double %c, double %d) { +; CHECK-LABEL: @PR41069( +; CHECK-NEXT: [[UNO1:%.*]] = fcmp uno double [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: [[UNO2:%.*]] = fcmp uno double [[C:%.*]], 0.000000e+00 +; CHECK-NEXT: [[OR:%.*]] = or i1 [[UNO1]], [[UNO2]] +; CHECK-NEXT: [[UNO3:%.*]] = fcmp uno double [[D:%.*]], 0.000000e+00 +; CHECK-NEXT: [[R:%.*]] = or i1 [[OR]], [[UNO3]] +; CHECK-NEXT: ret i1 [[R]] +; + %uno1 = fcmp uno double %a, %b + %uno2 = fcmp uno double %c, 0.0 + %or = or i1 %uno1, %uno2 + %uno3 = fcmp uno double %d, 0.0 + %r = or i1 %or, %uno3 + ret i1 %r +} + +define <2 x i1> @PR41069_vec(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x float> %d) { +; CHECK-LABEL: @PR41069_vec( +; CHECK-NEXT: [[UNO1:%.*]] = fcmp uno <2 x float> [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: [[UNO2:%.*]] = fcmp uno <2 x float> [[C:%.*]], zeroinitializer +; CHECK-NEXT: [[OR:%.*]] = or <2 x i1> [[UNO1]], [[UNO2]] +; CHECK-NEXT: [[UNO3:%.*]] = fcmp uno <2 x float> [[D:%.*]], +; CHECK-NEXT: [[R:%.*]] = or <2 x i1> [[OR]], [[UNO3]] +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %uno1 = fcmp uno <2 x float> %a, %b + %uno2 = fcmp uno <2 x float> %c, zeroinitializer + %or = or <2 x i1> %uno1, %uno2 + %uno3 = fcmp uno <2 x float> %d, + %r = or <2 x i1> %or, %uno3 + ret <2 x i1> %r +} + define i1 @fcmp_uno_nonzero(float %x, float %y) { ; CHECK-LABEL: @fcmp_uno_nonzero( ; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno float [[X:%.*]], [[Y:%.*]] -- 2.7.4