From 052c5bf40a9fc9ffe1bb2669763d8a0d2dea2b2e Mon Sep 17 00:00:00 2001 From: Zarko Todorovski Date: Wed, 30 Sep 2020 11:03:03 -0400 Subject: [PATCH] [PPC] Do not emit extswsli in 32BIT mode when using -mcpu=pwr9 It looks like in some circumstances when compiling with `-mcpu=pwr9` we create an EXTSWSLI node when which causes llc to fail. No such error occurs in pwr8 or lower. This occurs in 32BIT AIX and BE Linux. the cause seems to be that the default return in combineSHL is to create an EXTSWSLI node. Adding a check for whether we are in PPC64 before that fixes the issue. Reviewed By: #powerpc, nemanjai Differential Revision: https://reviews.llvm.org/D87046 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 6 +++--- llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll | 28 ++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 3 deletions(-) create mode 100644 llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 75b5ec9..0efb035 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -16322,10 +16322,10 @@ SDValue PPCTargetLowering::combineSHL(SDNode *N, DAGCombinerInfo &DCI) const { SDValue N0 = N->getOperand(0); ConstantSDNode *CN1 = dyn_cast(N->getOperand(1)); - if (!Subtarget.isISA3_0() || + if (!Subtarget.isISA3_0() || !Subtarget.isPPC64() || N0.getOpcode() != ISD::SIGN_EXTEND || - N0.getOperand(0).getValueType() != MVT::i32 || - CN1 == nullptr || N->getValueType(0) != MVT::i64) + N0.getOperand(0).getValueType() != MVT::i32 || CN1 == nullptr || + N->getValueType(0) != MVT::i64) return SDValue(); // We can't save an operation here if the value is already extended, and diff --git a/llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll b/llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll new file mode 100644 index 0000000..8c6df8c --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll @@ -0,0 +1,28 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc \ +; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=32BIT + +; RUN: llc -verify-machineinstrs -mtriple=powerpc64 \ +; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=64BIT + +define dso_local void @foo(i32 %inta, i64* %long_intb) { + entry: + %conv = sext i32 %inta to i64 + %shl = shl nsw i64 %conv, 8 + store i64 %shl, i64* %long_intb, align 8 + ret void +} + +; CHECK-LABEL: foo: + +; 32BIT-DAG: srawi [[REG1:[0-9]+]], [[REG2:[0-9]+]], 31 +; 32BIT-DAG: rotlwi [[REG3:[0-9]+]], [[REG2]], 8 +; 32BIT-DAG: slwi [[REG4:[0-9]+]], [[REG2]], 8 +; 32BIT-DAG: rlwimi [[REG5:[0-9]+]], [[REG1]], 8, 0, 23 +; 32BIT-DAG: stw [[REG4]], 4([[REG6:[0-9]+]]) +; 32BIT-DAG: stw [[REG5]], 0([[REG6]]) +; 32BIT: blr + +; 64BIT: extswsli [[REG1:[0-9]+]], [[REG2:[0-9]+]], 8 +; 64BIT-NEXT: std [[REG1]], 0([[REG3:[0-9]+]]) +; 64BIT-NEXT: blr -- 2.7.4